style(Bundles): move bundles to Bundles.scala (#4247)

timing(VLSU): fix timing issues in `VLSU` (#4158)

## Two main issues were fixed:
**Timing issue caused by too long address calculations for vector
modules:**
- Solved by moving some of the logic

timing(VLSU): fix timing issues in `VLSU` (#4158)

## Two main issues were fixed:
**Timing issue caused by too long address calculations for vector
modules:**
- Solved by moving some of the logic to the previous cycle.

---

**Timing issue caused by long exception logic of load writeback to
`VLMergeBuffer`:**
- Add one cycle to the load writeback exception, now the same number of
cycles as the load write back data.

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fix(VLSU): fix vector exception writeback to 'MergeBuffer' logic (#4137)

Fixed the bug of abnormal signal loss when writing back.

Previously, we expected to compare only the ports of the writebacks

fix(VLSU): fix vector exception writeback to 'MergeBuffer' logic (#4137)

Fixed the bug of abnormal signal loss when writing back.

Previously, we expected to compare only the ports of the writebacks that
triggered the exception and pick the oldest.

But amazingly, I just realised that the implementation doesn't match the
annotation. The current implementation can be problematic in that if
the write-back port that did not have an exception is older, the port that
triggered the exception is not elected.

Use s3_exception to try to optimise timing.

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fix(VLSU): `mergebuffer` threshold was added (#4103)

To solve the stuckness caused by insufficient RAW, we use `threshold` to
control the execution of vector instructions.
When the mergebuffer has f

fix(VLSU): `mergebuffer` threshold was added (#4103)

To solve the stuckness caused by insufficient RAW, we use `threshold` to
control the execution of vector instructions.
When the mergebuffer has few free entries than it can hold in the flow,
we backpressure to make `IssueQueue` send the oldest `Uop` for us.

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feat(Zicclsm): refactoring misalign and support vector misalign

feat(NCst): support WMO access of NC st

fix(VLSU): new vstart calculation method is adopted

feat(rv64v): support first only fault instruction

feat(VLSU, Trigger): add vector segment access Trigger logic

feat(VLSU): element in which the exception occurs needs to retain its old value

feat(VLSU): set vstart when the support vector accesses anomalies

feat(Trigger): add vector memory access Trigger logic

fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retain

fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retained. And for exceptions detected after address translation, the
48-bit vaddr needs to be zero-extended or sign-extended according to
different modes(`GenExceptionVa`), and then write to *tval.

Also fix some connection bugs.

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feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault t

feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault traps that meet
both of the following conditions:
- the trap is caused by a G-stage translation which supports VS-stage
translation
- a nonzero value is written to mtval2/htval

"isForVSnonLeafPTE" is used only in exceptional circumstances that gpf
happens in the G-stage translation which supports VS-stage translation,
such as searching the non-leaf pte of VS-stage.

This patch adds support for writing proper value to mtinst/htinst when
specific trap occurs. And bump the nemu.

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fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exc

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exceptions in such cases.

Commit
https://github.com/OpenXiangShan/XiangShan/commit/c1b28b66879239a5b3a44741376f3b002e8ac834
has already fixed high address bits checking of jump target. This commit
fixes lsu part, checking full address in tlb and passing full address
directly to csr.

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fix(exception): Add guest page fault logic of misalign and vlsu (#3537)

In our previous design, we did not consider the handling of gpf of
unaligned & vector load and stores. This commit adds a fix

fix(exception): Add guest page fault logic of misalign and vlsu (#3537)

In our previous design, we did not consider the handling of gpf of
unaligned & vector load and stores. This commit adds a fix to correctly
return the guest paddr when gpf happens in the above instructions.

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Vsplit: optimize generate of ready for vector issue

VLSU: Modify the width of Veew when decode and remove some useless api (#3258)

VSplit: refactor addr aligned logic for Unit-Stride

VSplit: Optimised address generation

VLSU: fix the problem caused by the 'segmentUnit' not connecting with 'sbufferVecDifftestInfo'.

VLSU: fix bug of vector load/store split & support segment instruction exception (#3033)

* Support segment load/store exception.
* Fix handle of inactive element when split uop.

VLSU: remove wdcache port

for Vstore, don't need query dcache, because we write it to sbuffer

VSegmentUnit: rewrite dcache port

split dcache port into rdcache port for read data, wdcache port for sta

VLSU: fix vector exception vaddr calculation

This commit fix the bug of vector exception vaddr calculation, need to send exceptionVec to exceptionBuffer.