timing(VLSU): fix timing issues in `VLSU` (#4158)

## Two main issues were fixed:
**Timing issue caused by too long address calculations for vector
modules:**
- Solved by moving some of the logic

timing(VLSU): fix timing issues in `VLSU` (#4158)

## Two main issues were fixed:
**Timing issue caused by too long address calculations for vector
modules:**
- Solved by moving some of the logic to the previous cycle.

---

**Timing issue caused by long exception logic of load writeback to
`VLMergeBuffer`:**
- Add one cycle to the load writeback exception, now the same number of
cycles as the load write back data.

show more ...

timing(VSegmentUnit): duplicate latchVAddr (#4209)

* `latchVAddr` needs to index all dcache data sram from top to bottom,
which causes a large fanout, so duplicate `latchVaddr`

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
Wh

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
WhenContext. For example, when(cond1){XSDebug(cond2, pable)} to
XSDebug(cond1 && cond2, pable)

show more ...

feat(Zicclsm): refactoring misalign and support vector misalign

feat(pointer masking): support Ssnpm & Smnpm & Smmpm (#3921)

feat(pointer masking): support Ssnpm & Smnpm & Smmpm

area(MemBlock): remove redundant signals to optimise area (#3560)

optimise redundant signals to reduce MemBlock area.
1. optimise 'exceptionVec', selected by LduCfg or StaCfg;
2. optimise 'fuType'

area(MemBlock): remove redundant signals to optimise area (#3560)

optimise redundant signals to reduce MemBlock area.
1. optimise 'exceptionVec', selected by LduCfg or StaCfg;
2. optimise 'fuType', reassign the value when writeback Rob in pipeline,
so no longer saved in LSQ.
3. optimise 'uop.imm', vaddr is computed in StoreMisalignBuffer and
there is no need to store the uop.imm.

show more ...

fix(VSegmentUnit): 'isFof' should use `io.in` for judgement (#3819)

refactor(MemBlock): turn on `dontTouch` only when debugging (#3792)

This will result in the delivery of clean generated code and may remove
some of the pseudo-paths.

fix(VSegmentUnit): fix VSegment trigger logic.

fix(fof): always use tail undisturbed when vl updated by un-raised exception.

fix(fof): write back exception vl when exception occurs but vl not 0

fix(VsegmentUnit): pmp information should be invalid in page fault

When a page fault occurs, the information in the pmp response should be invalid and no access fault should be generated based on t

fix(VsegmentUnit): pmp information should be invalid in page fault

When a page fault occurs, the information in the pmp response should be invalid and no access fault should be generated based on the information in the pmp response.

show more ...

feat(rv64v): support first only fault instruction

feat(VLSU, Trigger): add vector segment access Trigger logic

fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retain

fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retained. And for exceptions detected after address translation, the
48-bit vaddr needs to be zero-extended or sign-extended according to
different modes(`GenExceptionVa`), and then write to *tval.

Also fix some connection bugs.

show more ...

feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault t

feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault traps that meet
both of the following conditions:
- the trap is caused by a G-stage translation which supports VS-stage
translation
- a nonzero value is written to mtval2/htval

"isForVSnonLeafPTE" is used only in exceptional circumstances that gpf
happens in the G-stage translation which supports VS-stage translation,
such as searching the non-leaf pte of VS-stage.

This patch adds support for writing proper value to mtinst/htinst when
specific trap occurs. And bump the nemu.

show more ...

fix(VSegmentUnit): wait for data from the sbufferOut to sbuffer (#3554)

Need to wait for the data in the pipeline stage sbufferOut to be sent to
the sbuffer before you can write back.

fix(exception): Add guest page fault logic of misalign and vlsu (#3537)

In our previous design, we did not consider the handling of gpf of
unaligned & vector load and stores. This commit adds a fix

fix(exception): Add guest page fault logic of misalign and vlsu (#3537)

In our previous design, we did not consider the handling of gpf of
unaligned & vector load and stores. This commit adds a fix to correctly
return the guest paddr when gpf happens in the above instructions.

show more ...

fix(VLSU): fix the logic when the segment store is sent to sbuffer (#3498)

timing(MemBlock): optimize MemBlock timing (#3467)

This PR optimizes the timing of MemBlock. Specific optimizations include
but are not limited to:
+ TLB use the redirect for the next cycle
+ Opt

timing(MemBlock): optimize MemBlock timing (#3467)

This PR optimizes the timing of MemBlock. Specific optimizations include
but are not limited to:
+ TLB use the redirect for the next cycle
+ Optimize VLSU feedback and redirect
+ Optimise ldCancel and writeback signal generation
+ Optimise TLB Query Vaddr/hlv/hlvx/valid etc
+ Delay MMIO Store writeback for 1 Cycle
+ Fix tlbNoQuery and pmp logic
+ Remove clock gating for s3_fast_rep
+ Remove wbq conflict check to LoadPipe/MainPipe
+ Remove Mux in dcache resp data
+ Optimise data generation logic of LoadUnit
+ Duplicate Register in LoadUnit for data writeback
+ Duplicate Register in loadPipe for missQueue enq
+ Add skid buffer in VLSU
+ Select data from metaArray at S1
+ Simplify the enqueuing logic of missQueue
+ Separately generate the ready logic of miss Queue
+ Relax the conditions valid for bankdataArray reads
+ Add Reg between Dcache Mainpipe with sms prefetcher
+ Optimise store exceptionBuffer pipeline

---------

Co-authored-by: weiding liu <[email protected]>
Co-authored-by: Charlie Liu <[email protected]>
Co-authored-by: good-circle <[email protected]>

show more ...

fix(VLSU): fix segment difftest arbiter logic (#3463)

fix(VLSU): Vector Unit-Stride instr should trigger misaligned exception (#3462)

RVA23: Support Zicclsm & Zama16b (Handling Unaligned Load Store by Hardware) (#3320)

This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches

--

RVA23: Support Zicclsm & Zama16b (Handling Unaligned Load Store by Hardware) (#3320)

This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches

---------

Co-authored-by: xiaofeibao <[email protected]>

show more ...

VSegmentUnit: refactor writeback valid for batter timing

VLSU: Modify the width of Veew when decode and remove some useless api (#3258)