lsqueue - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/mem/lsqueue

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
9576d543	02-Feb-2021	William Wang <[email protected]>	Merge remote-tracking branch 'origin/temp-mem-timing-merge' into mem-timing /XiangShan/block-inclusivecache-sifive /XiangShan/debug/Makefile /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/ftq/Ftq.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/DCache.scala /XiangShan/src/main/scala/xiangshan/cache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/StoreReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/tlb.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala LSQWrapper.scala LoadQueue.scala LoadQueueData.scala StoreQueue.scala StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/scala/cache/L1DTest/CoreAgent.scala /XiangShan/src/test/scala/cache/L1DTest/CoreTransatcion.scala /XiangShan/src/test/scala/cache/L1DTest/L1DTest.scala /XiangShan/src/test/scala/cache/L1plusCacheTest.scala /XiangShan/src/test/scala/cache/L2CacheNonInclusiveGetTest.scala /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/cache/ReplaceTest.scala /XiangShan/src/test/scala/cache/TLCTest/BigIntUtil.scala /XiangShan/src/test/scala/cache/TLCTest/FixedBlockFuzzer.scala /XiangShan/src/test/scala/cache/TLCTest/TLCAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTest.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTransaction.scala /XiangShan/src/test/scala/cache/TLCTest/TLMasterMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLSlaveMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLULAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLULMMIO.scala /XiangShan/src/test/scala/cache/UnalignedGetTest.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/frontend/RASTest.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala /XiangShan/src/test/scala/xiangshan/memend/SbufferTest.scala
bdf1357a	02-Feb-2021	William Wang <[email protected]>	Merge branch 'mem-timing' of https://github.com/RISCVERS/XiangShan into mem-timing /XiangShan/src/main/scala/xiangshan/PMA.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala
03f79dff	02-Feb-2021	LinJiawei <[email protected]>	LoadQueue: fix bug /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala LoadQueue.scala /XiangShan/src/test/csrc/emu.cpp
eb9add3c	02-Feb-2021	William Wang <[email protected]>	Merge remote-tracking branch 'origin/master' into temp-mem-timing-merge /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/ftq/Ftq.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/test/scala/cache/ReplaceTest.scala /XiangShan/src/test/scala/top/XSSim.scala
423b9255	31-Jan-2021	William Wang <[email protected]>	PMA: fix pma check logic /XiangShan/src/main/scala/xiangshan/PMA.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala
7830f711	01-Feb-2021	William Wang <[email protected]>	LSU: pre-generate fwd sqIdxMask for better timing /XiangShan/src/main/scala/xiangshan/mem/Memend.scala LSQWrapper.scala LoadQueue.scala StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala
53c7ab8b	01-Feb-2021	William Wang <[email protected]>	Merge remote-tracking branch 'origin/master' into mem-timing /XiangShan/block-inclusivecache-sifive /XiangShan/debug/Makefile /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/ftq/Ftq.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/DCache.scala /XiangShan/src/main/scala/xiangshan/cache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/StoreReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/tlb.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala LSQWrapper.scala LoadQueue.scala LoadQueueData.scala StoreQueue.scala StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/scala/cache/L1DTest/CoreAgent.scala /XiangShan/src/test/scala/cache/L1DTest/CoreTransatcion.scala /XiangShan/src/test/scala/cache/L1DTest/L1DTest.scala /XiangShan/src/test/scala/cache/L1plusCacheTest.scala /XiangShan/src/test/scala/cache/L2CacheNonInclusiveGetTest.scala /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/cache/TLCTest/BigIntUtil.scala /XiangShan/src/test/scala/cache/TLCTest/FixedBlockFuzzer.scala /XiangShan/src/test/scala/cache/TLCTest/TLCAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTest.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTransaction.scala /XiangShan/src/test/scala/cache/TLCTest/TLMasterMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLSlaveMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLULAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLULMMIO.scala /XiangShan/src/test/scala/cache/UnalignedGetTest.scala /XiangShan/src/test/scala/xiangshan/frontend/RASTest.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala /XiangShan/src/test/scala/xiangshan/memend/SbufferTest.scala
aa1bcedb	01-Feb-2021	wangkaifan <[email protected]>	Merge branch 'linux-debug' into dual-dev /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h
36380705	01-Feb-2021	wangkaifan <[email protected]>	Merge branch 'master' into dual-dev /XiangShan/block-inclusivecache-sifive /XiangShan/debug/Makefile /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/ftq/Ftq.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/DCache.scala /XiangShan/src/main/scala/xiangshan/cache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/StoreReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/tlb.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala LSQWrapper.scala LoadQueue.scala LoadQueueData.scala StoreQueue.scala StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/goldenmem.cpp /XiangShan/src/test/csrc/goldenmem.h /XiangShan/src/test/scala/cache/L1DTest/CoreAgent.scala /XiangShan/src/test/scala/cache/L1DTest/CoreTransatcion.scala /XiangShan/src/test/scala/cache/L1DTest/L1DTest.scala /XiangShan/src/test/scala/cache/L1plusCacheTest.scala /XiangShan/src/test/scala/cache/L2CacheNonInclusiveGetTest.scala /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/cache/TLCTest/BigIntUtil.scala /XiangShan/src/test/scala/cache/TLCTest/FixedBlockFuzzer.scala /XiangShan/src/test/scala/cache/TLCTest/TLCAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTest.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTransaction.scala /XiangShan/src/test/scala/cache/TLCTest/TLMasterMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLSlaveMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLULAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLULMMIO.scala /XiangShan/src/test/scala/cache/UnalignedGetTest.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/frontend/RASTest.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala /XiangShan/src/test/scala/xiangshan/memend/SbufferTest.scala
a31b14cd	31-Jan-2021	LinJiawei <[email protected]>	CtrlBlock: send exception flush to mem block after a 'RegNext' /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala LoadQueue.scala
9dd1ecc9	31-Jan-2021	William Wang <[email protected]>	Merge branch 'mem-timing' of https://github.com/RISCVERS/XiangShan into mem-timing LoadQueue.scala
efcd430c	31-Jan-2021	William Wang <[email protected]>	LoadQueue: split rollback check into 3 stages * stage 0 (store s1): paddr match & state check * stage 1 (store s2): seq check 1 * stage 2 (store s3): seq check 2, cancel check, fire final req LoadQueue.scala
779258b0	31-Jan-2021	William Wang <[email protected]>	LSQ: delay vaddrModule write for 1 cycle * It should have no side effect LoadQueue.scala StoreQueue.scala
9af83969	31-Jan-2021	LinJiawei <[email protected]>	LoadQueue: fix cancel count bug /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala LoadQueue.scala
6567ff05	31-Jan-2021	Yinan Xu <[email protected]>	load,store: don't mark the instruction as mmio if it has exceptions /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ftq/Ftq.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/tlb.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
83f06d02	30-Jan-2021	William Wang <[email protected]>	Merge branch 'mem-timing' of https://github.com/RISCVERS/XiangShan into mem-timing LoadQueue.scala StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
2490f0dd	30-Jan-2021	William Wang <[email protected]>	LoadQueue: check rollback.valid in store_s3 /XiangShan/.gitignore /XiangShan/Makefile /XiangShan/scripts/vlsi_mem_gen /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/PMA.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/test/csrc/compress.cpp /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala
3561ef19	30-Jan-2021	William Wang <[email protected]>	Merge branch 'opt-memblock' into mem-timing /XiangShan/.gitignore /XiangShan/Makefile /XiangShan/scripts/vlsi_mem_gen /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/PMA.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala LoadQueue.scala StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/test/csrc/compress.cpp /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala
2c87aa6f	29-Jan-2021	ljw <[email protected]>	Merge pull request #510 from RISCVERS/ftq Ftq: save pc and branch infos by fetch packet /XiangShan/.gitignore /XiangShan/Makefile /XiangShan/block-inclusivecache-sifive /XiangShan/scripts/vlsi_mem_gen /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/ftq/Ftq.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala LSQWrapper.scala LoadQueue.scala StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/compress.cpp /XiangShan/src/test/scala/cache/L1DTest/L1DTest.scala /XiangShan/src/test/scala/cache/TLCTest/TLCAgent.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/frontend/RASTest.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala
a18e52d8	29-Jan-2021	William Wang <[email protected]>	Merge remote-tracking branch 'origin/master' into temp-xspf /XiangShan/.gitignore /XiangShan/Makefile /XiangShan/block-inclusivecache-sifive /XiangShan/debug/Makefile /XiangShan/scripts/vlsi_mem_gen /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/DCache.scala /XiangShan/src/main/scala/xiangshan/cache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/StoreReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala LSQWrapper.scala LoadQueue.scala LoadQueueData.scala StoreQueue.scala StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/test/csrc/compress.cpp /XiangShan/src/test/scala/cache/L1DTest/CoreAgent.scala /XiangShan/src/test/scala/cache/L1DTest/CoreTransatcion.scala /XiangShan/src/test/scala/cache/L1DTest/L1DTest.scala /XiangShan/src/test/scala/cache/L1plusCacheTest.scala /XiangShan/src/test/scala/cache/L2CacheNonInclusiveGetTest.scala /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/cache/TLCTest/BigIntUtil.scala /XiangShan/src/test/scala/cache/TLCTest/FixedBlockFuzzer.scala /XiangShan/src/test/scala/cache/TLCTest/TLCAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTest.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTransaction.scala /XiangShan/src/test/scala/cache/TLCTest/TLMasterMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLSlaveMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLULAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLULMMIO.scala /XiangShan/src/test/scala/cache/UnalignedGetTest.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/memend/SbufferTest.scala
a153fb1a	29-Jan-2021	William Wang <[email protected]>	LSQ: add XSPerf /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala LoadQueue.scala StoreQueue.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala
6e063394	29-Jan-2021	LinJiawei <[email protected]>	Merge remote-tracking branch 'origin/master' into ftq /XiangShan/.gitignore /XiangShan/Makefile /XiangShan/block-inclusivecache-sifive /XiangShan/debug/Makefile /XiangShan/scripts/vlsi_mem_gen /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/ftq/Ftq.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/DCache.scala /XiangShan/src/main/scala/xiangshan/cache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/StoreReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala LoadQueue.scala StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/test/csrc/compress.cpp /XiangShan/src/test/scala/cache/L1DTest/CoreAgent.scala /XiangShan/src/test/scala/cache/L1DTest/CoreTransatcion.scala /XiangShan/src/test/scala/cache/L1DTest/L1DTest.scala /XiangShan/src/test/scala/cache/L1plusCacheTest.scala /XiangShan/src/test/scala/cache/L2CacheNonInclusiveGetTest.scala /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/cache/TLCTest/BigIntUtil.scala /XiangShan/src/test/scala/cache/TLCTest/FixedBlockFuzzer.scala /XiangShan/src/test/scala/cache/TLCTest/TLCAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTest.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTransaction.scala /XiangShan/src/test/scala/cache/TLCTest/TLMasterMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLSlaveMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLULAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLULMMIO.scala /XiangShan/src/test/scala/cache/UnalignedGetTest.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/memend/SbufferTest.scala
62f4671c	29-Jan-2021	Yinan Xu <[email protected]>	Merge remote-tracking branch 'origin/master' into L1DCacheReTest /XiangShan/.gitignore /XiangShan/Makefile /XiangShan/block-inclusivecache-sifive /XiangShan/scripts/vlsi_mem_gen /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala LSQWrapper.scala LoadQueue.scala StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/test/csrc/compress.cpp /XiangShan/src/test/scala/cache/L1DTest/L1DTest.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala
b5b78226	29-Jan-2021	William Wang <[email protected]>	LoadQueueData: wrap data in LQData8Module LSQWrapper.scala LoadQueueData.scala StoreQueueData.scala
c32387e4	28-Jan-2021	wangkaifan <[email protected]>	Merge branch 'dual-stable' into dual-dev /XiangShan/.gitignore /XiangShan/Makefile /XiangShan/scripts/vlsi_mem_gen /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/StreamPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala LSQWrapper.scala LoadQueue.scala LoadQueueData.scala StoreQueue.scala StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/test/csrc/compress.cpp /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/goldenmem.cpp /XiangShan/src/test/csrc/goldenmem.h /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala
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