<verifi>:ICache add condition for multiple-hit

<timing> move pmp check in p3

<bug-fix> ICache: add set-conflict check for r0

icache: fix compilation errors

fix missUnit fanout

* latch arbiter out before entering dataArray, without which will causes
write valid ( state_reg ) fanout to every bit of WEM and D of SRAM

Optimize ICache s2_hit_reg and Ftq timing

* copy Ftq to ICache read valid signal

* move sram read data and miss data selection to IFU (after predecode)

ftq: optimize to itlb and to prefetch timing

* copy address select signal for every copied port
* add 1 more copy for itlb request use
* add 1 cycle latency for ftq_pc_mem read before sending to IPr

ftq: optimize to itlb and to prefetch timing

* copy address select signal for every copied port
* add 1 more copy for itlb request use
* add 1 cycle latency for ftq_pc_mem read before sending to IPrefetch

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<bug-fix> fix icache op read/write bug

<bug-fix> ICacheMainPipe: fix pmp af condition

* this bug is caused by trigger wait_state for a hit pmp af req

ICache: separate dataArray into 2-way SRAM

* <bug-fix>: fix port_1_read_0 condition

ftq: move toICache copied registers in ftq

IFU: add ICache ready

<bug-fix>: fix port_1_read_0 condition

ICache: only separate dataArray to 4 × 2-way banks

ftq, icache: fix compilation errors

ftq: copy bpu bypass write registers

* FtqToICache add bypass write signal and use bypass signal

IFU/IPrefetch/ReplacePipe: adjust meta/data access

* IFU: ignore ICache access bundle

* ICacheMainPipe: expand meta/data access output to 4 identical vector
output, each output is connected to a co

IFU/IPrefetch/ReplacePipe: adjust meta/data access

* IFU: ignore ICache access bundle

* ICacheMainPipe: expand meta/data access output to 4 identical vector
output, each output is connected to a copied register trigger by FTQ
requests

* IPrefetch/ReplacePipe: expand meta/data access outpu to 4 indentical
vector output, and each output is triggered by the same signal group

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ICache: separate meta/data to 4 2-way banks

* add ICachPartWayArray to wrap a part-way module

* SRAM array array_0 array_1: width × 1/4 and depth stay unchanged

[WIP]FTQ: add icache req port

* separate ifu req and icache req for timing optimization

* both ifu ftq_req_ready and icache ftq_req_ready depend on each other

* ifu and icache has pc_mem register

[WIP]FTQ: add icache req port

* separate ifu req and icache req for timing optimization

* both ifu ftq_req_ready and icache ftq_req_ready depend on each other

* ifu and icache has pc_mem register

[WIP]ICacheMainPipe: add copied registers

[WIP]ftq: read ftq_pc_mem one cycle ahead, reqs to be copied

[WIP] FTQ: delete outside bypass

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<bug-fix>: add s2_valid for pmp access fault

* without s2_valid, invalid pmp_af will cause wait_state turn into
wait_pmp_except and incorrect read data

<bug-fix> fix page fault cause fetch finish bug

<timing>: optimize ICacheMainPipe s2 timing

- Move tag and idx compare to s1 in secondary miss

- Delay 1 cycle when PMP report an access fault and ICache miss

<bug-fix> fix mmio signal mismatch

using RegNext causes a memory fetch req incorrectly perceived as a mmio
req

Revert "<bug-fix> fix mmio signal mismatch"

This reverts commit 99529e4819b711441099f5c91c73a2e37564aae1.

Revert "<timing>: optimize ICacheMainPipe s2 timing"

This reverts commit 33b7428054c70d12ddce94f1da885be439be6639.