timing(ICache): move mshr_resp selector 1 cycle ahead (#4173)

> we can latch mshr.io.resp.bits since they are set on req.fire or
acquire.fire, and keeps unchanged during response
> however, we sho

timing(ICache): move mshr_resp selector 1 cycle ahead (#4173)

> we can latch mshr.io.resp.bits since they are set on req.fire or
acquire.fire, and keeps unchanged during response
> however, we should not latch mshr.io.resp.valid, since io.flush/fencei
may clear it at any time

Old:
```
tilelink.resp.id -> | Reg |
|
v
| MSHR0 | -> | --- |
| MSHR1 | -> | Mux | -> io.resp
| ... | -> | |
| MSHRn | -> | --- |
```

New:
```
tilelink.resp.id
|
v
| MSHR0 | -> | --- |
| MSHR1 | -> | Mux | -> | Reg | -> io.resp
| ... | -> | |
| MSHRn | -> | --- |
```

Timing results are good, related path: slack -44ps -> positive.

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fix(ICacheMissUnit): clear corrupt_r when response is sent to MainPipe (#4112)

feat(ICache): ECC error injection (#4044)

This PR is part of *RAS(Reliability, Accessibility, Serviceability)* error recovery features.

- Add a series of mmio-mapped CSR to control ICache ECC check

feat(ICache): ECC error injection (#4044)

This PR is part of *RAS(Reliability, Accessibility, Serviceability)* error recovery features.

- Add a series of mmio-mapped CSR to control ICache ECC check & ECC inject features
- Implement ICache ECC injection
- M-state software can write `eccctrl` to trigger error injection to meta/dataArray, next read can trigger auto-recovery (implemented in #3899)
- Remove custom CSR `Sfetchctl`

# Details
## CSR
The base address of the added mmio-mapped CSR is `0x38022080` and the registers is defined as below:
```
64 10 7 4 2 1 0
0x00 eccctrl | WARL | ierror | istatus | itarget | inject | enable |

64 PAddrBits-1 0
0x08 ecciaddr | WARL | paddr |
```
| CSR | field | desp |
| --- | --- | --- |
| eccctrl | enable | ECC check enable |
| eccctrl | inject | ECC inject enable (write 1 to trigger injection, read always 0) |
| eccctrl | itarget | ECC inject target<br>0: metaArray<br>1: rsvd<br>2: dataArray<br>3: rsvd |
| eccctrl | istatus | ECC inject status (read-only)<br>0: idle: inject controller idle, goes to working when received a inject request (i.e. write 1 to eccctrl.inject)<br>1: working: inject controller working, goes to injected when finished / error when failed<br>2: injected, goes to idle after read<br>3: rsvd<br>4: rsvd<br>5: rsvd<br>6: rsvd<br>7: error: inject failed (check eccctl.ierror for reason), goes to idle after read |
| eccctrl | ierror | ECC error reason (read-only, valid only if `eccctrl.istatus==error`)<br>0: ECC check is not enabled (i.e. `!eccctrl.enable`)<br>1: inject target invalid (i.e. `eccctrl.itarget==rsvd`)<br>2: inject addr (i.e. `ecciaddr.paddr`) not in ICache<br>3: rsvd<br>4: rsvd<br>5: rsvd<br>6: rsvd<br>7: rsvd |
| ecciaddr | paddr | Physical address of the inject target |

## Inject method
```asm
$INJECT_ADDR:
# maybe do something else
ret

test:
la t0, $BASE_ADDR # load icache control base addr
la t1, $INJECT_ADDR # load inject addr
jalr ra, 0(t1) # jump to injected addr to load it i
sd t1, 8(t0) # set inject addr
la t2, (target << 2 | 1 << 1 | 1 << 0) # load inject target & inject enable & ecc enable
sd t1, 0(t0) # set inject enable & ecc enable
loop:
ld t1, 0(t0) # get ecc control state
andi t1, t1, (0b11 << (4+1)) # get high bits of inject state
beqz t1, loop # if is idle, or working, loop

addi t1, t1, -1 # t1 = inject_state[2:1] - 1
bnez t1, error # if is not injected, error or rsvd

jalr ra, 0(t1) # jump to injected addr to trigger error
j finish

error:
# handle error
finish:
# finish
```
Or, checkout https://github.com/OpenXiangShan/nexus-am/pull/48

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refactor(ICache): refactor code style & eliminate IDE warnings (#3947)

- add type annotation to public members
- add private qualifier to other members
- add `asUInt` to shift results (Bits)
- fi

refactor(ICache): refactor code style & eliminate IDE warnings (#3947)

- add type annotation to public members
- add private qualifier to other members
- add `asUInt` to shift results (Bits)
- fix typo
- remove unused imports
- rename `ICacheMSHR.waymask` to `way` since it is not a mask
- use `idxBits` for `log2Up(nSets)`
- use `wayBits` for `log2Up(nWays)`
- use `foreach` instead of `map` when return value is not needed
- use `{}` instead of `()` for multi-line `foreach` and `map`

The generated verilog is checked and is identical with the original
(except `waymask` -> `way` & order changes).

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style(Frontend): use scalafmt formatting frontend (#3370)

Format frontend according to the scalafmt file drafted in #3061.

timing(ICache): allow send MSHR response to (pre)fetch even when io.flush (#3542)

Cut critical path `io.flush -> mainPipe/prefetchPipe s2_miss -> s2_ready
-> ftq ready` for timing.

Now missUnit

timing(ICache): allow send MSHR response to (pre)fetch even when io.flush (#3542)

Cut critical path `io.flush -> mainPipe/prefetchPipe s2_miss -> s2_ready
-> ftq ready` for timing.

Now missUnit will still send response to mainPipe/prefetchPipe/wayLookup
when `io.flush` or `io.fencei` is `true.B`, but unnecessary response
will be dropped by mainPipe/prefetchPipe/wayLookup since their
`sx_valid` is set to false at the moment, so no functional/performance
change is expected.

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ICacheMissUnit: wait for all beats even corrupt has already occurred

See Tilelink spec section 4.4:
> The ones that are not marked corrupt still contain valid data. Every
TileLink request message

ICacheMissUnit: wait for all beats even corrupt has already occurred

See Tilelink spec section 4.4:
> The ones that are not marked corrupt still contain valid data. Every
TileLink request message requires a mandatory response message of a
mandatory size, and all beats of the message must be sent, even if every
beat is marked as corrupt.

We can't simply reset counter and send response to MainPipe when
corruption happens, but we have to wait until all beats of the message
are sent back from L2 cache even if there's a corrupt.

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MissUnit: update replacer only when acuqire fire (#3245)

Each time `io.victim.vSetIdx.valid === true.B`, replacer will choose the
LRU way as victim and access it to MRU position.

When `acquireArb.i

MissUnit: update replacer only when acuqire fire (#3245)

Each time `io.victim.vSetIdx.valid === true.B`, replacer will choose the
LRU way as victim and access it to MRU position.

When `acquireArb.io.out.valid === true.B && acquireArb.io.out.ready ===
false.B`, replacer will be mistakenly updated, thus violates PLRU
policy.

We want to update replacer only once per acquire request, so
`io.victim.vSetIdx.valid := acquireArb.io.out.fire`.

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ICache: implement new ICache (#3051)

Co-authored-by: xu_zh <[email protected]>

ICache: split cacheline in mainPipe and dataArray (#2609)

icache: reduce 1 cycle in mshr (#2375)

fdip: change instruction prefetch position to L2 (#2320)

* fdip: change prefetchQueue structure from shiftReg to fifo
* icache: add perfAccumulate to statistics the latency distribution of MSHR

Bump rocket-chip (#2353)

chore: remove deprecated brackets, APIs, etc. (#2321)

Bump difftst, huancun, and utility (#2316)

* add `VERILATOR_5` macro to indicate v5.0
* update the clock gating primitive for Verilator v5.0
* remove the clock IOs for DifftestModules
* add dontC

Bump difftst, huancun, and utility (#2316)

* add `VERILATOR_5` macro to indicate v5.0
* update the clock gating primitive for Verilator v5.0
* remove the clock IOs for DifftestModules
* add dontCare for RefillEvent

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Bump difftest for Chisel-generated interfaces (#2284)

We also add support for difftest with RISC-V Vector extension and nFused.

L2 TLB check is disabled unexpectedly and will be fixed soon.

icache: change itlb port to no-blocked and new fdip (#2277)

top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> de

top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> decode -> rename -> dispatch

* top-down: add dummy connections

* top-down: update TopdownCounters

* top-down: imp backend analysis and counter dump

* top-down: add HartId in `addSource`

* top-down: broadcast lqIdx of ROB head

* top-down: frontend signal done

* top-down: add memblock topdown interface

* Bump HuanCun: add TopDownMonitor

* top-down: receive and handle reasons in dispatch

* top-down: remove previous top-down code

* TopDown: add MemReqSource enum

* TopDown: extend mshr_latency range

* TopDown: add basic Req Source

TODO: distinguish prefetch

* dcache: distinguish L1DataPrefetch and CPUData

* top-down: comment out debugging perf counters in ibuffer

* TopDown: add path to pass MemReqSource to HuanCun

* TopDown: use simpler logic to count reqSource and update Probe count

* frontend: update topdown counters

* Update HuanCun Topdown for MemReqSource

* top-down: fix load stalls

* top-down: Change the priority of different stall reasons

* top-down: breakdown OtherCoreStall

* sbuffer: fix eviction

* when valid count reaches StoreBufferSize, do eviction

* sbuffer: fix replaceIdx

* If the way selected by the replacement algorithm cannot be written into dcache, its result is not used.

* dcache, ldu: fix vaddr in missqueue

This commit prevents the high bits of the virtual address from being truncated

* fix-ldst_pri-230506

* mainpipe: fix loadsAreComing

* top-down: disable dedup

* top-down: remove old top-down config

* top-down: split lq addr from ls_debug

* top-down: purge previous top-down code

* top-down: add debug_vaddr in LoadQueueReplay

* add source rob_head_other_repay

* remove load_l1_cache_stall_with/wihtou_bank_conflict

* dcache: split CPUData & refill latency

* split CPUData to CPUStoreData & CPULoadData & CPUAtomicData
* monitor refill latency for all type of req

* dcache: fix perfcounter in mq

* io.req.bits.cancel should be applied when counting req.fire

* TopDown: add TopDown for CPL2 in XiangShan

* top-down: add hartid params to L2Cache

* top-down: fix dispatch queue bound

* top-down: no DqStall when robFull

* topdown: buspmu support latency statistic (#2106)

* perf: add buspmu between L2 and L3, support name argument

* bump difftest

* perf: busmonitor supports latency stat

* config: fix cpl2 compatible problem

* bump utility

* bump coupledL2

* bump huancun

* misc: adapt to utility key&field

* config: fix key&field source, remove deprecated argument

* buspmu: remove debug print

* bump coupledl2&huancun

* top-down: fix sq full condition

* top-down: classify "lq full" load bound

* top-down: bump submodules

* bump coupledL2: fix reqSource in data path

* bump coupledL2

---------

Co-authored-by: tastynoob <[email protected]>
Co-authored-by: Guokai Chen <[email protected]>
Co-authored-by: lixin <[email protected]>
Co-authored-by: XiChen <[email protected]>
Co-authored-by: Zhou Yaoyang <[email protected]>
Co-authored-by: Lyn <[email protected]>
Co-authored-by: wakafa <[email protected]>

show more ...

Merge coupledL2 into master (#2064)

* icache: Acquire -> Get to L2

* gitmodules: add coupledL2 as submodule

* cpl2: merge coupledL2 into master

* Changes includes:
* coupledL2 integratio

Merge coupledL2 into master (#2064)

* icache: Acquire -> Get to L2

* gitmodules: add coupledL2 as submodule

* cpl2: merge coupledL2 into master

* Changes includes:
* coupledL2 integration
* modify user&echo fields in i$/d$/ptw
* set d$ never always-releasedata
* remove hw perfcnt connection for L2

* bump utility

* icache: remove unused releaseUnit

* config: minimalconfig includes l2

* Otherwise, dirty bits maintainence may be broken
* Known issue: L2 should have more than 1 bank to avoid compiling problem

* bump Utility

* bump coupledL2: fix bugs in dual-core

* bump coupledL2

* icache: set icache as non-coherent node

* bump coupledL2: fix dirty problem in L2 ProbeAckData

---------

Co-authored-by: guohongyu <[email protected]>
Co-authored-by: XiChen <[email protected]>

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ICache: remove useless code

ICache : finish fencei support

ICache:add DifftestRefillEvent for fdip debug

ICache:improve prefetch pipe filter logic

ICache:add blockCounter for blocking judgement

ICache: fix port_i_only_hit_in_ipf counter inc logic & add ipf_entry_first_hit_by_port_i perf counter