frontend: use HasCExtension to control whether we support rvc

bpu: add recover logic on replay for ras, prevent update on replay
for bim, btb, tage and ubtb

bpu: change signal names

change signal names related to brInfo

ras: enable debug

ifu, bpu: try to improve ras timing, change ubtb and btb update logic

ras: use bank aligned pc to calculate new return address

ifu: use @chiselName annotation

RAS: fix typo

merge master into tage-sc

Merge branch 'master' into ras-fix-rvc

ras: fix a bug where ras pushes wrong pc into stack on last half rvi-call
now we have reasonable ras performance on rvc coremark

Merge remote-tracking branch 'origin/master' into xs-fpu

Merge remote-tracking branch 'origin/ras-fix-rvc' into tage-sc

fix ras commit addr for rvc

RAS: wrap mems with Module

BPU: ret instruction taken depend on btb hit when spec ras is empty

log clean ups

RAS: use commit RAS to recover

RAS: add pop push logic when recover

RAS: upgrade ret predict accuracy

But not all is right(wrong route instruction may change RAS)

RAS: change push/pop signal

RAS: fix update info bug

RAS: add RVC surport

RAS: add update debug info