Merge branch 'master' into decoupled-frontend

frontend: let br/jmp share the last slot of an ftb entry, ghist update timing optimization

misc: code clean up (#1073)

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

frontend: code clean ups

frontend: remove deprecated code

Merge branch 'master' into merge-master

misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

[WIP]BPU: Decoupled frontend BPU design

Add sbt build support (#857)

Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr.
(2) DPI-C is cross-platform (Verilator, VCS, ...)
(3) difftest APIs are splited from emu.cpp to possibly support more backend platforms
(NEMU, Spike, ...)

The performance at this commit is quite slower than the original emu.
Performance issues will be fixed later.

* [WIP] SimTop: try to use 'XSTop' as soc

* CircularQueuePtr: ues F-bounded polymorphis instead implict helper

* Refactor parameters & Clean up code

* difftest: support basic difftest

* Support diffetst in new sim top

* Difftest; convert recode fmt to ieee754 when comparing fp regs

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Debug: add int/exc inst wb to debug queue

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Difftest: fix naive commit num limit

Co-authored-by: Yinan Xu <[email protected]>
Co-authored-by: William Wang <[email protected]>

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ras: partly handle stack overflow problems (#748)

* ras: partly handle stack overflow problems

* ras: add overflow and underflow statistics

csr,bpu: support enabling and disabling branch predictors via sbpctl (#593)

* csr: add sbpctrl to control branch predictors

* bpu: add dynamic switch to each predictor

* csr: change spfctl and

csr,bpu: support enabling and disabling branch predictors via sbpctl (#593)

* csr: add sbpctrl to control branch predictors

* bpu: add dynamic switch to each predictor

* csr: change spfctl and sbpctl address

* bpu: fix s3 connections

Co-authored-by: Yinan Xu <[email protected]>

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ftq, bpu: add cycle on commit and redirect(for ras and loop

ras: fix bugs

Merge branch 'ftq' of https://github.com/RISCVERS/XiangShan into ftq

ras: fix bugs and remove commit stack

RAS: add EnableCommit option

when enable commit, RAS use commit stack to recover,else we use CFI
update info to recover RAS sp and top register.

ftq and all: now we can compile

ras: move RASEntry to top level

RAS: fix perf bug that pc + 2 but not RVC

RAS: add topRegister

instead of searching by using sp index, use topRegister to store the top
entry of the stack.
sp is now use RASSize to initialize to identify the stack is empty.i.e,
valid sp sta

RAS: add topRegister

instead of searching by using sp index, use topRegister to store the top
entry of the stack.
sp is now use RASSize to initialize to identify the stack is empty.i.e,
valid sp start with 0 for the first entry and RASSize -1 for the last

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ifu, bpu: now we fetch with packet aligned pc

Merge remote-tracking branch 'origin/frontend-no-rvc' into ifu-timing

ras: don't modify commit_stack when replay