History log of /XiangShan/src/main/scala/xiangshan/cache/wpu/VictimList.scala (Results 1 – 3 of 3)
Revision Date Author Comments
# 4a0e27ec 31-Jul-2024 Yanqin Li <[email protected]>

wpu: fix the issue of abnormal power (#2976)

fix points:
1. parameter bug in DCacheWrapper
2. add clock gate to avoid frequent flip in BankedDataArray
3. remove redundant designs in WPU

power

wpu: fix the issue of abnormal power (#2976)

fix points:
1. parameter bug in DCacheWrapper
2. add clock gate to avoid frequent flip in BankedDataArray
3. remove redundant designs in WPU

power comparison:
![image](https://github.com/user-attachments/assets/8605098c-30a9-4b4e-a34b-69fd87a816df)

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# 8891a219 08-Oct-2023 Yinan Xu <[email protected]>

Bump rocket-chip (#2353)


# 04665835 28-Jul-2023 Maxpicca-Li <[email protected]>

DCacheWPU: update the latest version (#2095)

Co-authored-by: bugGenerator <[email protected]>
Co-authored-by: William Wang <[email protected]>
Co-authored-by: Haoyuan Feng <fenghaoyuan19@mails

DCacheWPU: update the latest version (#2095)

Co-authored-by: bugGenerator <[email protected]>
Co-authored-by: William Wang <[email protected]>
Co-authored-by: Haoyuan Feng <[email protected]>

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