timing(Backend): remove useless ldest=/=0.U logic because rfWen will be false

backend: new rob 8 banks read and 8 commit width

Merge upstream/master into tmp-backend-merge-master

backend: parameterized generation debug IO and difftest IO

Bump rocket-chip (#2353)

backend,perf: add more PMC

merge master into new-backend

Todo: fix error

params,backend: refactor RegFile parameters

CtrlBlock: implement rename snapshot (#2191)

* CtrlBlock: new ME method for better timing and area

* ctrlblock: implement snapshot recovery

* rename: enlarge distance between snapshots

* sn

CtrlBlock: implement rename snapshot (#2191)

* CtrlBlock: new ME method for better timing and area

* ctrlblock: implement snapshot recovery

* rename: enlarge distance between snapshots

* snapshot: add rename snapshot switch

* CtrlBlock: add snapshotGen API

* snapshot: optimize timing

* snapshot: put snapshot logic in a module

show more ...

CtrlBlock: new ME method for better timing and area (#2161)

new move elimination method:

1. get old_pdest from arch-rat when commit;
2. get ready-for-free from comparing old-pdest with arch-rat

CtrlBlock: new ME method for better timing and area (#2161)

new move elimination method:

1. get old_pdest from arch-rat when commit;
2. get ready-for-free from comparing old-pdest with arch-rat after commit;

show more ...

backend: refactor vset and add rab support

vset: add vset instr support

Switch to asynchronous reset for all modules (#1867)

This commit changes the reset of all modules to asynchronous style,
including changes on the initialization values of some registers.
For async

Switch to asynchronous reset for all modules (#1867)

This commit changes the reset of all modules to asynchronous style,
including changes on the initialization values of some registers.
For async registers, they must have constant reset values.

show more ...

Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

rename: Re-rename instead of walking back after redirect (#1768)

* freelist & refcounter: implement arch states

* walk: restore and walk again when redirecting

* ROB: optimize invalidation of

rename: Re-rename instead of walking back after redirect (#1768)

* freelist & refcounter: implement arch states

* walk: restore and walk again when redirecting

* ROB: optimize invalidation of `valid`

show more ...

ctrl: optimize freelist timing (#1633)

* rat: map all arch registers to zero when init

* freelist: fix stepBack width

* freelist: fix timing of free offset

freelist: optimize timing of read and writing (#1593)

This commit optimizes the timing of freelist by changing the updating
function of headPtr and tailPtr.

We maintains an one-hot representatio

freelist: optimize timing of read and writing (#1593)

This commit optimizes the timing of freelist by changing the updating
function of headPtr and tailPtr.

We maintains an one-hot representation of headPtr and further uses it to
read the free registers from the list, which should be better than the
previous implementation where headPtr is used to indexed into the queue.

The update of tailPtr and the freelist is delayed by one cycle to
optimize the timing. Because freelist allocates new registers in the
next cycle iff there are more than RenameWidth free registers in this
cycle. The freed registers in this cycle will never be used in the next
cycle. Thus, we can delay the updating of queue data to the next cycle.
We also move the update of tailPtr to the next cycle, since PopCount
takes a long timing and we move the last adder to the next cycle. Now
the adder works parallely with PopCount. That is, the updating of
tailPtr is pipelined.

show more ...

core: refactor hardware performance counters (#1335)

This commit optimizes the coding style and timing for hardware
performance counters.

By default, performance counters are RegNext(RegNext(_)).

add performance counters at core and hauncun (#1156)

* Add perf counters
* add reg from hpm counter source
* add print perfcounter enable

refCounter: delay de-allocation for one more cycle (#1144)

This commit changes how de-allocation is done in RefCounter. One cycle
after we update the reference counters, the free registers are rele

refCounter: delay de-allocation for one more cycle (#1144)

This commit changes how de-allocation is done in RefCounter. One cycle
after we update the reference counters, the free registers are released
to the freelist.

Previous version creates a critical path, starting from deallocate ports
and ending at freelist registers. This commit adds one more cycle in the
allocation --> updating reference counters --> freeing physical
registers --> allocation loop.

show more ...

rename: support full-featured move elimination (#1123)

This commit optimizes the move elimination implementation.

Reference counting for every physical register is recorded. Originally
0-31 regi

rename: support full-featured move elimination (#1123)

This commit optimizes the move elimination implementation.

Reference counting for every physical register is recorded. Originally
0-31 registers have counters of ones. Every time the physical register
is allocated or deallocated, the counter is increased or decreased by
one. When the counter becomes zero from a non-zero value, the register
is freed and released to freelist.

show more ...

core: use redirect ports for flush (#1121)

This commit removes flush IO for every module. Flush now re-uses
redirect ports to flush the instructions.

misc: code clean up (#1073)

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

backend, freelist: shrink verilog size by using scala variable
instead of chisel var in MEFreeList.scala

backend, freelist: simplify walk logic