History log of /XiangShan/src/main/scala/xiangshan/backend/issue/ (Results 726 – 750 of 794)
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a3f0ab0801-Jul-2020 ZhangZifei <[email protected]>

IssueQueue: fix bug that disable validQue when deq


IssueQueue.scala
7cc699dc01-Jul-2020 ZhangZifei <[email protected]>

IssueQueue: fix bug of log cause mix of idQue'idx and IQue's idx


IssueQueue.scala
cfe3d82401-Jul-2020 ZhangZifei <[email protected]>

IssueQueue: fix bug of toIssFire and change some log


IssueQueue.scala
ec9f649c01-Jul-2020 ZhangZifei <[email protected]>

IssueQueue: fix bug of tail change logic


IssueQueue.scala
90db48e001-Jul-2020 ZhangZifei <[email protected]>

IssueQueue: change some log


IssueQueue.scala
526e279a01-Jul-2020 ZhangZifei <[email protected]>

IssueQueue: fix bug of enqBypass logic and comment some log


IssueQueue.scala
1b8013d401-Jul-2020 ZhangZifei <[email protected]>

IssueQueue: fix bug of signal io.enqCtrl.ready


IssueQueue.scala
f4bd523401-Jul-2020 ZhangZifei <[email protected]>

IssueQueue: fix bug of tailKeep/has1Rdy, rename IQ Module


/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
IssueQueue.scala
/XiangShan/src/test/scala/IQtest/IQtest.scala
4c620a3101-Jul-2020 Yinan Xu <[email protected]>

issuequeue: add log


/XiangShan/.gitignore
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala
IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala
f9d0143130-Jun-2020 William Wang <[email protected]>

pipeline: fixing bugs in "dummy" test


/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/Alu.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/Bru.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/Lsu.scala
IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/package.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala
/XiangShan/src/main/scala/xiangshan/frontend/FakeIFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
/XiangShan/src/main/scala/xiangshan/utils/LogUtils.scala
/XiangShan/src/test/csrc/difftest.cpp
/XiangShan/src/test/csrc/emu.h
/XiangShan/src/test/scala/top/XSSim.scala
/XiangShan/stale_outputs_checked
03b441c130-Jun-2020 ZhangZifei <[email protected]>

IssueQueue: fix srcRdyVec's bug and add pc/roqIdx to wu/bp's log


IssueQueue.scala
04b5628330-Jun-2020 ZhangZifei <[email protected]>

IssueQueue: add srcType check to wakeup and bypass


IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/package.scala
40486c9c30-Jun-2020 ZhangZifei <[email protected]>

IssueQueue: fix bug of write back idQue(sel) to IdQue(tail)


IssueQueue.scala
f8930d2230-Jun-2020 ZhangZifei <[email protected]>

IssueQueue: add io.selectUop logic and change issToFire signal


IssueQueue.scala
7b8d1ac830-Jun-2020 ZhangZifei <[email protected]>

IssueQueue: add redirect logic


IssueQueue.scala
9bc5b00d30-Jun-2020 ZhangZifei <[email protected]>

IssueQueue: add log, fix bug of signal idValidQue


IssueQueue.scala
16ab672d30-Jun-2020 ZhangZifei <[email protected]>

IssueQueue: add srcDataWire signal

add srcDataWire to make sure the data sent to issueToFire is new


IssueQueue.scala
e1a7b39f30-Jun-2020 ZhangZifei <[email protected]>

IssueQueue: add some comment to beautify it


IssueQueue.scala
ec4f3be230-Jun-2020 ZhangZifei <[email protected]>

IssueQueue: add deq, wakeup and bypass & add independent rdy/data


/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
IssueQueue.scala
7487794f29-Jun-2020 ZhangZifei <[email protected]>

IssueQueue: init commit of IssueQueueCompact with only enqueue


/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/Alu.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/Bru.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/Lsu.scala
IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/package.scala
/XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala
/XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
/XiangShan/src/main/scala/xiangshan/utils/LogUtils.scala
/XiangShan/src/test/csrc/difftest.cpp
/XiangShan/stale_outputs_checked
0103429028-Jun-2020 jinyue <[email protected]>

IssueQueue: change module CCU into function


IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/utils/LogUtils.scala
/XiangShan/src/test/scala/top/XSSim.scala
0851457f27-Jun-2020 LinJiawei <[email protected]>

Rename: map arch reg to phy reg 0-31 initially


/XiangShan/Makefile
/XiangShan/debug/Makefile
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala
/XiangShan/src/main/scala/xiangshan/utils/LogUtils.scala
/XiangShan/src/test/csrc/common.h
/XiangShan/src/test/csrc/emu.h
/XiangShan/src/test/csrc/log.cpp
/XiangShan/src/test/csrc/main.cpp
/XiangShan/src/test/scala/top/XSSim.scala
c59eb60626-Jun-2020 Yinan Xu <[email protected]>

merge issuequeue


IssueQueue.scala
f232e79226-Jun-2020 Yinan Xu <[email protected]>

Merge remote-tracking branch 'origin/issuequeue' into debug-0626


/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala
IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
571a2e6926-Jun-2020 jinyue <[email protected]>

IssueQueue:add src3 debug info


/XiangShan/Makefile
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala
IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
/XiangShan/src/main/scala/xiangshan/utils/LogUtils.scala
/XiangShan/src/test/csrc/emu.h
/XiangShan/src/test/csrc/main.cpp
/XiangShan/src/test/scala/top/XSSim.scala

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