fix(csr): filter out Read-Only CSR in regOut (#4412)

fix(PFEvent): use `CSRModule` for distribute_csr in PFEvent (#4321)

feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI p

feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI protoco
- Can don't using these modules by setting the option `HasMEMencryption`
& `HasBitmapCheck` to false

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feat(custom, csr): add two custom CSRs mcorepwr and mflushpwr to control power (#4164)

Co-authored-by: Zhu Yu <[email protected]>

fix(dbltrp): fix sdt write and sdt/sie interaction logic

* For the write alias of sstatus, write sdt 0 should also be blocked
by DTE close
* For the write behavior of `mstatus/vsstatus.sdt`,

fix(dbltrp): fix sdt write and sdt/sie interaction logic

* For the write alias of sstatus, write sdt 0 should also be blocked
by DTE close
* For the write behavior of `mstatus/vsstatus.sdt`, since it is
directly written, the `sdt` field in `new_val` can be used to
determine whether to write `sdt` and affect `sie`. For the write
behavior of `sstatus.sdt`, due to changes in the write mask when
`DTEclose` is enabled, the original value of `sstatus.sdt` must be
considered for its impact on `sie` when `new_val.sdt` cannot be written.

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feat(pointer masking): support Ssnpm & Smnpm & Smmpm (#3921)

feat(pointer masking): support Ssnpm & Smnpm & Smmpm

fix(dbltrp): fix sdt/dte interaction logic

* menvcfg.DTE only control Smode dbltrp. Thus mstatus.sdt will not
control by DTE.
* as sstatus is alias of mstatus, when menvcfg.DTE close write

fix(dbltrp): fix sdt/dte interaction logic

* menvcfg.DTE only control Smode dbltrp. Thus mstatus.sdt will not
control by DTE.
* as sstatus is alias of mstatus, when menvcfg.DTE close write
sstatus.sdt cannot lead to shadow write of mstatus.sdt. As a result,
we add wmask of sdt, when write source is from alias write.
While vsstatus is not alias of any other CSR fields, so origin logic
is correct.

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fix(mip): mip.seip is alias of mvip.seip when mvien.seie = 0

fix(mip): add otherwise when wen mip

fix(mhpmevent): add MhpmeventBundle for mhpmevent csr.

feat(Ss/Smdbltrp) : Support RISC-V Ss/Smdbltrp Extension (#3789)

* NEMU commit: 066cb1f1c61feb21153399c26ca393dfb3a560d7
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defco

feat(Ss/Smdbltrp) : Support RISC-V Ss/Smdbltrp Extension (#3789)

* NEMU commit: 066cb1f1c61feb21153399c26ca393dfb3a560d7
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig

Including:
* fix(format): adjust code format and add one config (OpenXiangShan/NEMU#603)
* fix(vfredusum): set xstatus.fs and xstatus.vs dirty (OpenXiangShan/NEMU#605)
* fix(vf): do not set dirtyFs for some instructions (OpenXiangShan/NEMU#606)
* feat(trigger): add trigger support for rva.
* configs(xs): open Sm/sdbltrp extension and add MDT_INIT config (OpenXiangShan/NEMU#604)

---

* spike commit: c0b18d3913d8ceac83743a053a7dbd2fb8716c83
* spike config: CPU=XIANGSHAN

Including:
* fix(rva, trigger): For rva instr, raise BP from trigger prior to misaligned.
* fix(Makefile): Increase maxdepth for finding .h files.
* fix(tdata1): CPU_XIANGSHAN do not implement hit bit in tdata1.
* fix(icount): place the read before the return of the detect_icount_match.

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fix(Smrnmi): expand NMI interrupt to two types and route the nmi signals to XSTOP (#3691)

fix(Trigger): remove tcontrol in trigger module.

* remove tcontrol.
* use xIE to control trigger's breakpoint exception.
* modify medelege: bit(EX_BP) is writable.
* fix emu.yml to make medelege

fix(Trigger): remove tcontrol in trigger module.

* remove tcontrol.
* use xIE to control trigger's breakpoint exception.
* modify medelege: bit(EX_BP) is writable.
* fix emu.yml to make medelege.EX_BP writable in SMP Linux jobs.

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feat(CSR): add No.16,18 and 19 exceptions (#3640)

fix(CSR): remove reg in mhartid (#3665)

* mhartid should be assigned directly to multicycle hartid from top.

refactor(HPM): move HPMs from utils to utility repo (#3631)

Because HPMs will be used in Coupled L2 as well, delete
`PerfCounterUtils.scala` in Xiangshan and create
`HardwarePerfMonitor.scala` in

refactor(HPM): move HPMs from utils to utility repo (#3631)

Because HPMs will be used in Coupled L2 as well, delete
`PerfCounterUtils.scala` in Xiangshan and create
`HardwarePerfMonitor.scala` in Utility.
See also [Pull Request in
CoupledL2](https://github.com/OpenXiangShan/CoupledL2/pull/251#discussion_r1770738535).

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fix(CSR): Add legalization code for mstatus.MPP, mnstatus.MNPP and dcsr.PRV (#3577)

fix(Svpbmt): let PBMTEs in [mh]envcfg be RW and have reset value 0 (#3558)

feat(pbmt): support PBMTE in MMU (#3521)

Co-authored-by: Xuan Hu <[email protected]>

fix(CSR): LCOFIP should not always be updated with lcofiReq from hpmevent.OF

feat(riscv64): support RISC-V Smrnmi extension (#3480)

fix(csr): fix wen perfEvents to wen mhpmevents csr (#3469)

misa: set misa.B to 1.

NewCSR: fix mie.LCOFIE is RW and init value 0

NewCSR: fix wen condition of mip.lcofip