fix(CSR): use GEILEN from IMSICParams (#4520)

fix(aia): add the missing AIA-related permission checks

Along the same lines, when hstatus.VGEIN is not the number of an implemented guest external
interrupt, attempts from M-mode or HS-mode to acce

fix(aia): add the missing AIA-related permission checks

Along the same lines, when hstatus.VGEIN is not the number of an implemented guest external
interrupt, attempts from M-mode or HS-mode to access CSR vstopei raise an illegal instruction
exception, and attempts from VS-mode to access stopei raise a virtual instruction exception.

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feat(CSR): set init 0 for htimedelta csr (#4145)

fix(hideleg): fix the read value of the LCOFI bit of hideleg.

For bits of mideleg that are zero, the corresponding bits in
hideleg, hip, and hie are read-only zeros.

The VSSIP, VSTIP, VSEIP in mide

fix(hideleg): fix the read value of the LCOFI bit of hideleg.

For bits of mideleg that are zero, the corresponding bits in
hideleg, hip, and hie are read-only zeros.

The VSSIP, VSTIP, VSEIP in mideleg are read-only ones
when the H extension is implemented.

When the hypervisor extension is implemented, if a bit is zero in
the same position in both mideleg and mvien, then that bit is
read-only zero in hideleg (in addition to being read-only zero in
sip, sie, hip, and hie). But if a bit for one of interrupts 13-63
is a one in either mideleg or mvien, then the same bit in hideleg
may be writable or may be read-only zero, depending on the
implementation. No bits in hideleg are ever read-only ones. The
RISC-V Privileged Architecture further constrains bits 12:0 of
hideleg.

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feat(pointer masking): support Ssnpm & Smnpm & Smmpm (#3921)

feat(pointer masking): support Ssnpm & Smnpm & Smmpm

fix(aia): fix hviprio bundle

feat(Ss/Smdbltrp) : Support RISC-V Ss/Smdbltrp Extension (#3789)

* NEMU commit: 066cb1f1c61feb21153399c26ca393dfb3a560d7
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defco

feat(Ss/Smdbltrp) : Support RISC-V Ss/Smdbltrp Extension (#3789)

* NEMU commit: 066cb1f1c61feb21153399c26ca393dfb3a560d7
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig

Including:
* fix(format): adjust code format and add one config (OpenXiangShan/NEMU#603)
* fix(vfredusum): set xstatus.fs and xstatus.vs dirty (OpenXiangShan/NEMU#605)
* fix(vf): do not set dirtyFs for some instructions (OpenXiangShan/NEMU#606)
* feat(trigger): add trigger support for rva.
* configs(xs): open Sm/sdbltrp extension and add MDT_INIT config (OpenXiangShan/NEMU#604)

---

* spike commit: c0b18d3913d8ceac83743a053a7dbd2fb8716c83
* spike config: CPU=XIANGSHAN

Including:
* fix(rva, trigger): For rva instr, raise BP from trigger prior to misaligned.
* fix(Makefile): Increase maxdepth for finding .h files.
* fix(tdata1): CPU_XIANGSHAN do not implement hit bit in tdata1.
* fix(icount): place the read before the return of the detect_icount_match.

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feat(CSR): add No.16,18 and 19 exceptions (#3640)

fix(csr): fix trap inst update when CSRR insts raise trap and remove useless io (#3620)

This PR fix trap inst update.
Because of CSRR inst is out of order insts, trap inst should select the
oldest

fix(csr): fix trap inst update when CSRR insts raise trap and remove useless io (#3620)

This PR fix trap inst update.
Because of CSRR inst is out of order insts, trap inst should select the
oldest trap inst when CSRR inst raise trap.

---------

Co-authored-by: Xuan Hu <[email protected]>

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fix(Svpbmt): let PBMTEs in [mh]envcfg be RW and have reset value 0 (#3558)

feat(pbmt): support PBMTE in MMU (#3521)

Co-authored-by: Xuan Hu <[email protected]>

NewCSR: when STCE in menvcfg is zero, STCE in henvcfg is read-only zero

build: purge chisel 3 and add deprecation check (#3250)

NewCSR: set legal init value to WARL Field

NewCSR: set local interrupt is RO while LCOFI is RW and reset 0 in hideleg CSR (#3222)

NewCSR: fix xtopi priority select and iprio bundle

* unused interrupt field is read only 0 in Iprio Bundle

NewCSR,AIA: connect external interrupt pending to xip CSR

* Connect meip produced by imsic to `mip.regOut.MEIP`.
* Connect seip produced by imsic to `mip.rdata.SEIP`.
* Connect vseip produced by ims

NewCSR,AIA: connect external interrupt pending to xip CSR

* Connect meip produced by imsic to `mip.regOut.MEIP`.
* Connect seip produced by imsic to `mip.rdata.SEIP`.
* Connect vseip produced by imsic to `hgeip.regOut[63:1]`

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Support smstateen/ssstateen extension, add stateen0 CSRs

NewCSR: fix atp CSRs PPN mask

* The writable length of satp is `PAddrBits - PageOffsetWidth`.
* The writable length of vsatp varies with hgatp.MODE.
* When hgatp.MODE is `Bare`, it's `PAddrBits -

NewCSR: fix atp CSRs PPN mask

* The writable length of satp is `PAddrBits - PageOffsetWidth`.
* The writable length of vsatp varies with hgatp.MODE.
* When hgatp.MODE is `Bare`, it's `PAddrBits - PageOffsetWidth`.
* When hgatp.MODE is `Sv39x4`, it's `41 - PageOffsetWidth`.
* The writable length of hgatp is `PAddrBits - PageOffsetWidth`. Since the root page table is 16 KiB and must be aligned to a 16-KiB boundary, the lowest two bits of the physical page number (PPN) in hgatp always read as zeros.
* A write to hgatp with an unsupported MODE value is not ignored as it is for satp.
* Instead, the fields of hgatp are WARL in the normal way, when so indicated.

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NewCSR: fix rdata when VS mode access VS CSRs by address of S mode

NewCSR: set accessibility of `htinst` to RW

NewCSR: use rocketchip's CSR addr

NewCSR: use runtime reflect to call CSRFieldXXBits instead of compile reflect

NewCSR: support AIA extension Interrupt Pending and Enable

NewCSR: update henvcfg CSR

* Henvcfg.STCE is read-only zero when menvcfg.STCE=0 && access stimecmp/vstimecmp in Non-M mode