fix(dcsr): debug support critical error state

* support nmip, cetrig, extcause fileds in dcsr.
* critical error state enter dmode when dcsr.cetrig assert.

fix(CSR): Add legalization code for mstatus.MPP, mnstatus.MNPP and dcsr.PRV (#3577)

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump
target address, which made it impossible to raise exceptions in such
cases.

To resolve this problem, we detect the invalid jump target in
jump/branch/CSR and, this information to frontend and store the complete
invalid target in a single register in backend. The frontend will then
raise an exception to backend and backend will also use the invalid
target in the register to write xtval and mepc.

---------

Co-authored-by: Muzi <[email protected]>
Co-authored-by: ngc7331 <[email protected]>

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Trigger: refactor trigger information in pipeline. (#3403)

ROB: clear flushPipe when the enq uop has exception (#3281)

NewCSR: fixed dpc

NewCSR: support vu/vs entry debugMode

NewCSR: Add Trigger CSR tcontrol

* add csr tcontrol.

* medeleg(EX_BP) hard-wired to 0. Parter 5.4 in debug spec. tcontrol is implemented. medeleg(3) is hard-wired to 0.

NewCSR: Refactor CSR about Debug

* add CSR: trigger csr & debug csr

* add CSR event: TrapEntryDEvent & DretEvent

* fixed trigger's comparison func between Consecutive pc and tdada2