| #
4e1a70f6 |
| 28-Jun-2020 |
William Wang <[email protected]> |
Lsu: add sbuffer to naive Lsu
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| #
f56615ce |
| 24-Jun-2020 |
ljw <[email protected]> |
Merge pull request #27 from RISCVERS/dev-xs-execution
difftest: set up nemu difftest framework
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| #
72235fa4 |
| 24-Jun-2020 |
William Wang <[email protected]> |
difftest: set up nemu difftest framework
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| #
b2ff7aaa |
| 24-Jun-2020 |
jinyue <[email protected]> |
Backend:add lsu into wbInstReqs
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| #
63a5f438 |
| 24-Jun-2020 |
jinyue <[email protected]> |
Backend: change dispatch2->dispatch
IssueQueue: delete io.enq.redirect
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| #
dc84e476 |
| 24-Jun-2020 |
jinyue <[email protected]> |
Merge branch 'master' into issuequeue
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| #
99dd9207 |
| 23-Jun-2020 |
LinJiawei <[email protected]> |
add decode buffer
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| #
2ad41afc |
| 23-Jun-2020 |
jinyue <[email protected]> |
Merge branch 'master' into issuequeue
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| #
a9d430a1 |
| 23-Jun-2020 |
ljw <[email protected]> |
Merge pull request #14 from RISCVERS/dispatch-dev
merge branch dispatch-dev to master
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| #
e402d94e |
| 23-Jun-2020 |
William Wang <[email protected]> |
Lsu: insert naive Lsu into pipeline
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| #
0765c64f |
| 23-Jun-2020 |
Yinan Xu <[email protected]> |
backend,dispatch: remove unused code in backend.scala
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| #
ad17ac41 |
| 23-Jun-2020 |
Yinan Xu <[email protected]> |
backend: fix connections between dispatch and rename,regfile
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| #
735ba814 |
| 23-Jun-2020 |
William Wang <[email protected]> |
Roq: fix Backend-Roq interface
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| #
0200b0af |
| 23-Jun-2020 |
Yinan Xu <[email protected]> |
Merge branch 'master' into dispatch-dev
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| #
5e8cfbcd |
| 23-Jun-2020 |
ZhangZifei <[email protected]> |
IssueQueue: change wakeupPorts/Bypass from DecoupleIO to ValidIO
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| #
58fdaf7c |
| 23-Jun-2020 |
Yinan Xu <[email protected]> |
backend,dispatch: finish dispatch except for redirect
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| #
5c9fc6ec |
| 22-Jun-2020 |
ZhangZifei <[email protected]> |
IssueQueue: fix bug that bypass group should be in wakeupPorts
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| #
986a0bb0 |
| 22-Jun-2020 |
ZhangZifei <[email protected]> |
IssueQueue: move bypass's data from wakeupPorts to bypassData
also parameterize bypass logic in Exu and Backend.
add needBypass in Exu.Config to explictly point out bypass or not.
bypass logic: the
IssueQueue: move bypass's data from wakeupPorts to bypassData
also parameterize bypass logic in Exu and Backend.
add needBypass in Exu.Config to explictly point out bypass or not.
bypass logic: the bypass units form a bypass group, they bypass
each other, the data was bypassed by io.bypassUops and bypassData.
other data from non-bypass-group are passed by wakeupPorts.
Units of non-bypass-group are passed normally
show more ...
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| #
88b0b551 |
| 22-Jun-2020 |
LinJiawei <[email protected]> |
Brq: remove BrqReciveSize
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| #
ad55d194 |
| 22-Jun-2020 |
ZhangZifei <[email protected]> |
IssueQueue: remove io.bypassDatas
bypassDatas is confilct with wakeUpPorts(CDB)
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| #
b61413a3 |
| 21-Jun-2020 |
Yinan Xu <[email protected]> |
merge master
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| #
5d47a821 |
| 21-Jun-2020 |
ZhangZifei <[email protected]> |
BRQ: remove Brq.exuRedirect's Arbiter
ALU/BRU's outRedirect.bits is passed Brq directly.
Redirect's valid is ALU/BRU's fire()
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| #
8999dcd9 |
| 21-Jun-2020 |
ZhangZifei <[email protected]> |
Brq/exuRedirect: change from Valid(Redirect) to ValidIO(ExuOutput)
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| #
7bc1a6e4 |
| 21-Jun-2020 |
ZhangZifei <[email protected]> |
Merge branch 'master' into alu
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| #
cc4cad5e |
| 21-Jun-2020 |
ZhangZifei <[email protected]> |
Exu/Alu: add ALU && pass ALU/BRU.bjRes to Brq through exuRedirect
1. add ALU(almost copy from Noop.ALU)
remove jal/jalr/ret/call from ALU
remove predictWrong from ALU(judged by brq now)
rem
Exu/Alu: add ALU && pass ALU/BRU.bjRes to Brq through exuRedirect
1. add ALU(almost copy from Noop.ALU)
remove jal/jalr/ret/call from ALU
remove predictWrong from ALU(judged by brq now)
remove bpuUpdateReq from ALU
2. add Redirect to ExuOutput
it is connected to brq
show more ...
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