Backend,MemBlock: add uopIdx for vector load/store feedback

backend: new rob 8 banks read and 8 commit width

frontend: add a gpaddr write data path

add a data path in Ifu, which write gpaddr to backend at the same time
as write to IBuffer

Merge remote-tracking branch 'upstream/master' into tmp-master

TODO: add gpaddr data path from frontend to backend

RVH: finish the desigh of H extention

Merge remote-tracking branch 'upstream/master' into tmp-master

Trigger: optimize trigger

* delete data trigger in frontend

* optimiza trigger comparison logic
co-author-by: Guokai Chen <[email protected]>

* delete frontendTiming & frontendChain

Trigger: optimize trigger

* delete data trigger in frontend

* optimiza trigger comparison logic
co-author-by: Guokai Chen <[email protected]>

* delete frontendTiming & frontendChain in TriggerCf

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CSR: Correct the behavior of `ebreak` when hart not in debug mode

* `ebreak` instruction will raise breakpoint exception when hart not in debug mode.
* Use the signals renamed with "has*" to specify

CSR: Correct the behavior of `ebreak` when hart not in debug mode

* `ebreak` instruction will raise breakpoint exception when hart not in debug mode.
* Use the signals renamed with "has*" to specify the traps(exceptions/interrupts) are to be handled which were transported from ROB, while the signals renamed with "raise*" are being transported to ROB.

This commit is cherry-pick from nanhu and new-backend.

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Decode,IBuffer: fix circle dependency deadlock

* Add a new field `canAccept` passed from decode to notice `IBuffer` that it can deq new instructions.
* IBuffer.io.out(i).ready depends on IBuffer.io.

Decode,IBuffer: fix circle dependency deadlock

* Add a new field `canAccept` passed from decode to notice `IBuffer` that it can deq new instructions.
* IBuffer.io.out(i).ready depends on IBuffer.io.out(i).ready.
* Since decode promises accepting insts in order, priority encoder is used to simplify the accumulation of `numDeq`.
* `numDeq` records the number of deq insts from ibuffer, not from bypass. And it is used to update deqPtr and corresponding deqBankPtr.
* Guard numFromFetch calculation with io.in.valid to avoid updating enqPtr when input signal is invalid.
* Todo: check ibuffer timing, critical path maybe ibuffer.io.out.valid -> ibuffer.io.out.ready -> ibuffer.validEntries -> nextValidEntries -> allowEnq

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Merge remote-tracking branch 'upstream/master' into tmp-backend-merge-fixtiming

Trigger: delete useless code about trigger

MemResp: fix bug --> hyu still needs fastResp

Backend: refactor LDU resp

Scheduler: implement wakeup from LoadUnit

Rab: shrink rab entry width

Feature keyword priority (#2562)

* "isKeyword" priority & debug( modify load fwd mshr data):

*Bundle: add "isKeyword" in L2ToL1Hint

*XSCore/XSTile/MemBlock: modify l2_hint assignment,(

Feature keyword priority (#2562)

* "isKeyword" priority & debug( modify load fwd mshr data):

*Bundle: add "isKeyword" in L2ToL1Hint

*XSCore/XSTile/MemBlock: modify l2_hint assignment,(add isKeyword)

*DCacheWrapper: add lqidx for compare age, add IsKeywordField

*LoadPipe: add lqIdx for miss_req

*MissQueue: add "isKeyword" logic for miss entries, MissReqPipeReg
transfer "isKeyword" from L1 to L2 by mem_acquire
modify refill_to_ldq 's addr/data logic depending on
"isKeyword"
modify load forward data from mshr logic

*LoadQueueReplay: modify replay order by l2_hint

*LoadUnit: add lqIdx in dcache_req

* modify iskeyword 'user' to 'echo', load forward data from tlbundle D

* L2TOP: modify l2_hint type, add l2_hint_iskeyword

* LRQ: add l2_hint xsperf counter

* modify merge conflict:
loadunit: name changed so_uop --> so_select_src.uop

* DCacheWrapper: modify tl_channel_D 2 beats both can fwd data

* dump coupledL2 : Feature favor l1 d keyword priority (#87)

* Fix fma rm (#2586)

* bump fudian

* fma: fix bug of fadd's rm

* FMA: fix bug of fadd's rm

* dump : coupledL2 branch:feature-favor-L1D-keyword-priority

* dump coupledL2

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Co-authored-by: xiaofeibao-xjtu <[email protected]>

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rv64v: support copy data directly use i2v
* also fix some bugs for vwadd.w and vrgather.vi

Debug Module: cherry-pick debug module from nanhu

remove rawNuke (#2460)

Co-authored-by: Lyn <[email protected]>

LDU: fix rar flush logic (#2445)

* fix rar flush logic

* fix re-fetch and flushPipe logic

* fix rar rollback logic, cancel isFlushPipe

* fix syntax error

* fix selectOldest logic

* fi

LDU: fix rar flush logic (#2445)

* fix rar flush logic

* fix re-fetch and flushPipe logic

* fix rar rollback logic, cancel isFlushPipe

* fix syntax error

* fix selectOldest logic

* fix redirect pc gen loigc

---------

Co-authored-by: Lyn <[email protected]>

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snapshot: flush conditionally when redirect comes

fix merge error

Merge upstream/master into tmp-backend-merge-master

Rob: fix FP CSR issue when rob compressing

Bump rocket-chip (#2353)