| #
4ec80874 |
| 18-Dec-2020 |
zoujr <[email protected]> |
Ibuffer: Optmise Ibuf timing
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| #
44ff7871 |
| 16-Dec-2020 |
Lingrui98 <[email protected]> |
ifu: use parallel priority mux for if1_npc, add a priority mux generator
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| #
1e808fde |
| 14-Dec-2020 |
Yinan Xu <[email protected]> |
Merge pull request #308 from RISCVERS/decode-alt
Decode: refractor Decode Unit
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| #
5d60766c |
| 14-Dec-2020 |
Yinan Xu <[email protected]> |
Merge pull request #317 from RISCVERS/frontend-refactor
Frontend refactor on global history
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| #
580c7a5e |
| 14-Dec-2020 |
Lingrui98 <[email protected]> |
bundle: fix a bug which will not mark sawNTBrs when the whole fetch packet is predicted not taken
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| #
bca39442 |
| 13-Dec-2020 |
YikeZhou <[email protected]> |
Merge branch 'master' into decode-alt
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| #
d5f596d2 |
| 13-Dec-2020 |
Lingrui98 <[email protected]> |
Merge remote-tracking branch 'origin/master' into frontend-refactor
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| #
f634c609 |
| 13-Dec-2020 |
Lingrui98 <[email protected]> |
ifu: refactor global history
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| #
2ea5e87c |
| 13-Dec-2020 |
Yinan Xu <[email protected]> |
Merge remote-tracking branch 'origin/master' into perf-debug
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| #
21e7a6c5 |
| 13-Dec-2020 |
Yinan Xu <[email protected]> |
roq,commits: update commit io
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| #
579b9f28 |
| 12-Dec-2020 |
LinJiawei <[email protected]> |
[WIP] impl fp load/store in recode fmt
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| #
7e6acce3 |
| 12-Dec-2020 |
jinyue110 <[email protected]> |
ICache: add access fault exception
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| #
a7006537 |
| 11-Dec-2020 |
Yinan Xu <[email protected]> |
Merge remote-tracking branch 'origin/master' into perf-debug
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| #
a63ad672 |
| 11-Dec-2020 |
YikeZhou <[email protected]> |
Merge branch 'master' into decode-alt
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| #
1fac3bed |
| 11-Dec-2020 |
Steve Gou <[email protected]> |
Merge pull request #304 from RISCVERS/frontend-refactor
Frontend refactor
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| #
838068f7 |
| 10-Dec-2020 |
Lingrui98 <[email protected]> |
bundle: fix a bug which suppresses last half RVI
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| #
57c3c8de |
| 10-Dec-2020 |
Lingrui98 <[email protected]> |
predecode: fix a bug on last half RVI
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| #
c2a8ae00 |
| 04-Dec-2020 |
YikeZhou <[email protected]> |
DecodeUnit: may have bugs
package.scala: add SelImm object to indicate Imm type
Bundle: add selImm to CtrlSignal
DecodeUnitDiffTest: can select subset of control signals for testing
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| #
04fb04ef |
| 03-Dec-2020 |
Lingrui98 <[email protected]> |
ifu, bpu, predecode: several bugs fixed, now we can run coremark at a low performance
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| #
4d24c305 |
| 03-Dec-2020 |
YikeZhou <[email protected]> |
DecodeUnit: Fill up decode frame.
DecodeUnitDiffTest: Add a diff-test with old Decoder.
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| #
4b17b4ee |
| 03-Dec-2020 |
Lingrui98 <[email protected]> |
ifu, bpu: now can run but got errors
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| #
ceaf5e1f |
| 01-Dec-2020 |
Lingrui98 <[email protected]> |
frontend: half done refactoring
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| #
be25371a |
| 30-Nov-2020 |
YikeZhou <[email protected]> |
DecodeUnit: Add a rocket-like decode frame
Bundle: Add `decode` method to CtrlSignals Bundle
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| #
8b922c39 |
| 29-Nov-2020 |
Yinan Xu <[email protected]> |
ifu: only use redirect.bits for addr
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| #
2d366136 |
| 21-Nov-2020 |
LinJiawei <[email protected]> |
Decode: split 'noSpecExec' and 'blockBackward'
noSpecExec can only enq roq when roq is empty
blockBackward should block roq when the instruction is not commited
|