| #
d42f3562 |
| 29-Jan-2021 |
Lingrui98 <[email protected]> |
ibuffer: remove pnpc
ifu: reconsider prediction of prevHalfInstr
now we do not need to gather meta from the last packet
because we update with packet, thus updating in the
correct slot
|
| #
ac870c74 |
| 28-Jan-2021 |
LinJiawei <[email protected]> |
Merge remote-tracking branch 'origin/master' into ftq
|
| #
e70e66e8 |
| 28-Jan-2021 |
ZhangZifei <[email protected]> |
RS: re-write rs into three block: select ctrl(uop) data(srcdata)
1. divide into three block
2. change io port:
broadcastUop -> fastUopsIn
selectUop -> fastUopOut
extraPorts -> slowPorts
RS: re-write rs into three block: select ctrl(uop) data(srcdata)
1. divide into three block
2. change io port:
broadcastUop -> fastUopsIn
selectUop -> fastUopOut
extraPorts -> slowPorts
etc.
the cross sub block io is not wrapped, to it later
show more ...
|
| #
c32387e4 |
| 28-Jan-2021 |
wangkaifan <[email protected]> |
Merge branch 'dual-stable' into dual-dev
|
| #
37459b99 |
| 28-Jan-2021 |
LinJiawei <[email protected]> |
Merge remote-tracking branch 'origin/opt-exception' into ftq
|
| #
8a5bdd64 |
| 28-Jan-2021 |
wangkaifan <[email protected]> |
difftest: export atomic store info to assist dual-core difftest
|
| #
8f77f081 |
| 28-Jan-2021 |
Yinan Xu <[email protected]> |
Merge remote-tracking branch 'origin/master' into opt-exception
|
| #
b1c52bdf |
| 27-Jan-2021 |
wangkaifan <[email protected]> |
Merge branch 'master' of https://github.com/RISCVERS/XiangShan into dual-stable
|
| #
54bc08ad |
| 27-Jan-2021 |
wangkaifan <[email protected]> |
misc: optimize trap info transition for dual-core
|
| #
f871093b |
| 27-Jan-2021 |
Yinan Xu <[email protected]> |
Merge pull request #486 from RISCVERS/perf-debug
Perf: Add counter for BPU
|
| #
76523708 |
| 27-Jan-2021 |
Yinan Xu <[email protected]> |
Merge pull request #496 from RISCVERS/opt-memblock
Lsq, Roq: ld/st commit logic refactor
|
| #
6886802e |
| 27-Jan-2021 |
LinJiawei <[email protected]> |
Merge remote-tracking branch 'origin/master' into ftq
|
| #
07635e87 |
| 27-Jan-2021 |
wangkaifan <[email protected]> |
difftest: wire out load instr info from core to enhance difftest
|
| #
b3aa0763 |
| 27-Jan-2021 |
William Wang <[email protected]> |
Roq: remove lsqPtr from roq
|
| #
48dc7634 |
| 26-Jan-2021 |
LinJiawei <[email protected]> |
Ftq: add a fsm for each inst
|
| #
8b91a337 |
| 26-Jan-2021 |
William Wang <[email protected]> |
debug: store load paddr in Roq.debug_paddr
|
| #
fe211d16 |
| 26-Jan-2021 |
LinJiawei <[email protected]> |
Update perf counters
|
| #
a165bd69 |
| 25-Jan-2021 |
wangkaifan <[email protected]> |
difftest: support dual-core difftest signal in-core
* should be compatible with single core difftest framework
|
| #
2d7c7105 |
| 25-Jan-2021 |
Yinan Xu <[email protected]> |
redirect: split conditional redirect and unconditional redirect
|
| #
fe1ab9c6 |
| 24-Jan-2021 |
Lingrui98 <[email protected]> |
bundle: add a bit indicating that packet has half RVI from the last packet
|
| #
51f54365 |
| 24-Jan-2021 |
zoujr <[email protected]> |
Merge branch 'master' into perf-debug
|
| #
744c623c |
| 22-Jan-2021 |
Lingrui98 <[email protected]> |
ftq and all: now we can compile
|
| #
fc4776e4 |
| 22-Jan-2021 |
LinJiawei <[email protected]> |
[WIP] connect leftOne and ftq enq ptr
|
| #
148ba860 |
| 22-Jan-2021 |
LinJiawei <[email protected]> |
[WIP] fix cifIndex update logic
|
| #
cde9280d |
| 22-Jan-2021 |
LinJiawei <[email protected]> |
[WIP] update alu/jump unit
|