SoC: remove 4 buffers between L2 and L3 (#2155)

Disable chiselDB by default to minimize the size of DB (#2118)

* config: disable chiseldb by default to minimize db size

* note that tllog is still enabled when alwaysBasicDB is set

* bump hua

Disable chiselDB by default to minimize the size of DB (#2118)

* config: disable chiseldb by default to minimize db size

* note that tllog is still enabled when alwaysBasicDB is set

* bump huancun & utility

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top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> de

top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> decode -> rename -> dispatch

* top-down: add dummy connections

* top-down: update TopdownCounters

* top-down: imp backend analysis and counter dump

* top-down: add HartId in `addSource`

* top-down: broadcast lqIdx of ROB head

* top-down: frontend signal done

* top-down: add memblock topdown interface

* Bump HuanCun: add TopDownMonitor

* top-down: receive and handle reasons in dispatch

* top-down: remove previous top-down code

* TopDown: add MemReqSource enum

* TopDown: extend mshr_latency range

* TopDown: add basic Req Source

TODO: distinguish prefetch

* dcache: distinguish L1DataPrefetch and CPUData

* top-down: comment out debugging perf counters in ibuffer

* TopDown: add path to pass MemReqSource to HuanCun

* TopDown: use simpler logic to count reqSource and update Probe count

* frontend: update topdown counters

* Update HuanCun Topdown for MemReqSource

* top-down: fix load stalls

* top-down: Change the priority of different stall reasons

* top-down: breakdown OtherCoreStall

* sbuffer: fix eviction

* when valid count reaches StoreBufferSize, do eviction

* sbuffer: fix replaceIdx

* If the way selected by the replacement algorithm cannot be written into dcache, its result is not used.

* dcache, ldu: fix vaddr in missqueue

This commit prevents the high bits of the virtual address from being truncated

* fix-ldst_pri-230506

* mainpipe: fix loadsAreComing

* top-down: disable dedup

* top-down: remove old top-down config

* top-down: split lq addr from ls_debug

* top-down: purge previous top-down code

* top-down: add debug_vaddr in LoadQueueReplay

* add source rob_head_other_repay

* remove load_l1_cache_stall_with/wihtou_bank_conflict

* dcache: split CPUData & refill latency

* split CPUData to CPUStoreData & CPULoadData & CPUAtomicData
* monitor refill latency for all type of req

* dcache: fix perfcounter in mq

* io.req.bits.cancel should be applied when counting req.fire

* TopDown: add TopDown for CPL2 in XiangShan

* top-down: add hartid params to L2Cache

* top-down: fix dispatch queue bound

* top-down: no DqStall when robFull

* topdown: buspmu support latency statistic (#2106)

* perf: add buspmu between L2 and L3, support name argument

* bump difftest

* perf: busmonitor supports latency stat

* config: fix cpl2 compatible problem

* bump utility

* bump coupledL2

* bump huancun

* misc: adapt to utility key&field

* config: fix key&field source, remove deprecated argument

* buspmu: remove debug print

* bump coupledl2&huancun

* top-down: fix sq full condition

* top-down: classify "lq full" load bound

* top-down: bump submodules

* bump coupledL2: fix reqSource in data path

* bump coupledL2

---------

Co-authored-by: tastynoob <[email protected]>
Co-authored-by: Guokai Chen <[email protected]>
Co-authored-by: lixin <[email protected]>
Co-authored-by: XiChen <[email protected]>
Co-authored-by: Zhou Yaoyang <[email protected]>
Co-authored-by: Lyn <[email protected]>
Co-authored-by: wakafa <[email protected]>

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Fix constant (#2071)

* constant: fix dead loop

* util: fix constant dynamic switch

* util: fix constant

circt: fix assertion fails in circt simulation (#2023)

Tool: cancel DIP-C write when in FPGA (#2009)

* constant variable: add FPAGPlatform parameter

* scripts: set WITH_CONSTANTIN to 1 by default

* submodules: version to lyq repository for test

Tool: cancel DIP-C write when in FPGA (#2009)

* constant variable: add FPAGPlatform parameter

* scripts: set WITH_CONSTANTIN to 1 by default

* submodules: version to lyq repository for test

* Revert "constant variable: add FPAGPlatform parameter"

This reverts commit fc2f03b768cb2ad63cb543096b00b971c85467d6.

* constant: add FPGA init

* chiseldb: add FPGA init

* difftest: version

* chisledb: add envFPGA situation

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util: change ElaborationArtefacts to FileRegisters (#1973)

* util: change ElaborationArtefacts to FileRegisters

use `filename` instead of `extension` to record file

* huancun: merge master

util: change ElaborationArtefacts to FileRegisters (#1973)

* util: change ElaborationArtefacts to FileRegisters

use `filename` instead of `extension` to record file

* huancun: merge master

* huancun: version change

* util: update to main

* SimTop: delete unused comment

* constantin: fix bug which reduced emputy map

* code opt: add write api in FileRegisters

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Switch to asynchronous reset for all modules (#1867)

This commit changes the reset of all modules to asynchronous style,
including changes on the initialization values of some registers.
For async

Switch to asynchronous reset for all modules (#1867)

This commit changes the reset of all modules to asynchronous style,
including changes on the initialization values of some registers.
For async registers, they must have constant reset values.

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Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

top-down: introduce top-down counters and scripts (#1803)

* top-down: add initial top-down features

* rob600: enlarge queue/buffer size

* :art: After git pull

* :sparkles: Add BranchResteer

top-down: introduce top-down counters and scripts (#1803)

* top-down: add initial top-down features

* rob600: enlarge queue/buffer size

* :art: After git pull

* :sparkles: Add BranchResteers->CtrlBlock

* :sparkles: Cg BranchResteers after pending

* :sparkles: Add robflush_bubble & ldReplay_bubble

* :ambulance: Fix loadReplay->loadReplay.valid

* :art: Dlt printf

* :sparkles: Add stage2_redirect_cycles->CtrlBlock

* :saprkles: CtrlBlock:Add s2Redirect_when_pending

* :sparkles: ID:Add ifu2id_allNO_cycle

* :sparkles: Add ifu2ibuffer_validCnt

* :sparkles: Add ibuffer_IDWidth_hvButNotFull

* :sparkles: Fix ifu2ibuffer_validCnt

* :ambulance: Fix ibuffer_IDWidth_hvButNotFull

* :sparkles: Fix ifu2ibuffer_validCnt->stop

* feat(buggy): parameterize load/store pipeline, etc.

* fix: use LoadPipelineWidth rather than LoadQueueSize

* fix: parameterize `rdataPtrExtNext`

* fix(SBuffer): fix idx update logic

* fix(Sbuffer): use `&&` to generate flushMask instead of `||`

* fix(atomic): parameterize atomic logic in `MemBlock`

* fix(StoreQueue): update allow enque requirement

* chore: update comments, requirements and assertions

* chore: refactor some Mux to meet original logic

* feat: reduce `LsMaxRsDeq` to 2 and delete it

* feat: support one load/store pipeline

* feat: parameterize `EnsbufferWidth`

* chore: resharp codes for better generated name

* top-down: add initial top-down features

* rob600: enlarge queue/buffer size

* top-down: add l1, l2, l3 and ddr loads bound perf counters

* top-down: dig into l1d loads bound

* top-down: move memory related counters to `Scheduler`

* top-down: add 2 Ldus and 2 Stus

* top-down: v1.0

* huancun: bump HuanCun to a version with top-down

* chore: restore parameters and update `build.sc`

* top-down: use ExcitingUtils instead of BoringUtils

* top-down: add switch of top-down counters

* top-down: add top-down scripts

* difftest: enlarge stuck limit cycles again

Co-authored-by: gaozeyu <[email protected]>

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huancun: use huancun of nanhu with Top-Down support (#1811)

top: add real-time clock for CLINT (#1553)

pass reset vector from SimTop (#1545)

core,rob: support the WFI instruction

The RISC-V WFI instruction is previously decoded as NOP. This commit
adds support for the real wait-for-interrupt (WFI).

We add a state_wfi FSM in the ROB. Aft

core,rob: support the WFI instruction

The RISC-V WFI instruction is previously decoded as NOP. This commit
adds support for the real wait-for-interrupt (WFI).

We add a state_wfi FSM in the ROB. After WFI leaves the ROB, the next
instruction will wait in the ROB until an interrupt.

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Misc: add support for compiling with CIRCT

SoC: timing opt (#1431)

* SoC: timing opt

* Added buffers for pma

Co-authored-by: Yinan Xu <[email protected]>

Adjusted reset signals (#1441)

* Adjusted reset signals

* Support reset tree

Connect L2 ecc error to BEU / Connect L3 ecc error to PLIC (#1415)

* l2/l3: Report ecc error to beu or plic

* Bump huancun

* Connect l3 ecc error to plic

Add pma checker for I/O device (#1300)

* SoC: add axi4spliter

* pmp: add apply method to reduce loc

* pma: add PMA used in axi4's spliter

* Fix package import

* pma: re-write tl-pma, put

Add pma checker for I/O device (#1300)

* SoC: add axi4spliter

* pmp: add apply method to reduce loc

* pma: add PMA used in axi4's spliter

* Fix package import

* pma: re-write tl-pma, put tl-pma into AXI4Spliter

* pma: add memory mapped pma

* soc: rm dma port, rm axi4spliter, mv mmpma out of spliter

* Remove unused files

* update dma pma check port at SimTop.scala; update pll lock defalt value to 1

Co-authored-by: ZhangZifei <[email protected]>
Co-authored-by: rvcoresjw <[email protected]>

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update id and dma data width (#1278)

* update id width, set io bits to do not touch
* modify dma data width from 128bits to 256 bits

Change L2 to 4 banks (#1256)

* misc: soc timing optimize

* XSTile: insert buffer between L1Dcache and L2

* Bump huancun

* Change L2 to 4 banks

* Adjust buffers

* Add more buffers for

Change L2 to 4 banks (#1256)

* misc: soc timing optimize

* XSTile: insert buffer between L1Dcache and L2

* Bump huancun

* Change L2 to 4 banks

* Adjust buffers

* Add more buffers for peripheral port

* Fix submodule version

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SoC timing fix (#1253)

* misc: soc timing optimize

* XSTile: insert buffer between L1Dcache and L2

top: add seip and meip bits from plic (#1221)

Refactor config & Add pll (#1181)

* Add cache ctrl node

* L2/L3: Reduce client dir size

* Ctrl: connect soft reset from L3 to core

* Add pll

* Config: seperate SocParams and CoreParams t

Refactor config & Add pll (#1181)

* Add cache ctrl node

* L2/L3: Reduce client dir size

* Ctrl: connect soft reset from L3 to core

* Add pll

* Config: seperate SocParams and CoreParams to get correct number of cores

* Bump huancun

* Add pll output

* Fix inclusive cache config

* Add one more pll ctrl reg

* Bump huancun

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Optimize L2->L3 crossbar (#1177)

* Bump huancun

* Simplify l2 -> l3 cross bar

* HuanCun: remove debug print