| #
83cb791f |
| 02-Apr-2021 |
allen <[email protected]> |
L2/L3: support configurable uncached get and let L3 cache GET (#722)
* Fixed perf counter does not print bug in BlockInclusiveCache.
* BlockInclusiveCache: Dont Probe L1 On Hint Hit.
* L2 use
L2/L3: support configurable uncached get and let L3 cache GET (#722)
* Fixed perf counter does not print bug in BlockInclusiveCache.
* BlockInclusiveCache: Dont Probe L1 On Hint Hit.
* L2 use UncachedGet, L3 cache Get.
* Bump L2
Co-authored-by: LinJiawei <[email protected]>
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| #
94c92d92 |
| 01-Apr-2021 |
Yinan Xu <[email protected]> |
ResetGen: generate reset signals for different modules (#740)
* Add ResetRegGen module to generate reset signals for different modules
To meet physical design requirements, reset signals for diff
ResetGen: generate reset signals for different modules (#740)
* Add ResetRegGen module to generate reset signals for different modules
To meet physical design requirements, reset signals for different modules
need to be generated respectively. This commit adds a ResetRegGen module
to automatically generate reset registers and connects different reset
signals to different modules, including l3cache, l2cache, core.
L1plusCache, MemBlock, IntegerBlock, FloatBlock, CtrlBlock, Frontend are
reset one by one.
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| #
c17003d2 |
| 26-Mar-2021 |
Allen <[email protected]> |
Merge branch 'master' of github.com:RISCVERS/XiangShan
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| #
11b3c588 |
| 26-Mar-2021 |
Allen <[email protected]> |
Pass enablePerf to BlockInclusiveCache.
L2 and L3 Only enablePerf when XSCore enables perf.
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| #
f5089e26 |
| 26-Mar-2021 |
Wonicon <[email protected]> |
l2,timing: bump l2/l3 cache (#652)
* l2,timing: bump l2/l3 cache
This will necessarily add several cycles to L2/L3 cache responsing time.
* l2,l3: bump timing tweaks
Resolved timeout in deb
l2,timing: bump l2/l3 cache (#652)
* l2,timing: bump l2/l3 cache
This will necessarily add several cycles to L2/L3 cache responsing time.
* l2,l3: bump timing tweaks
Resolved timeout in debian boot.
Remove repeat feature to avoid directory disturbing
(repeat allows to use previous tag and victim info which is dangerous).
TODO:
- [ ] Another directory atomicity weakness that heavy l1 release can
overwrite l3tol2 probe directory update, for example:
l1.rel.TtoB write dirty -> l1.rel.BtoN readout dirty then writeback
l2.probeAck.BtoB write non-dirty (not saved)
l3 think l2 is branch, but l2 is still trunk.
But forbid nestB and nestC can cause deadlock...
- [ ] Delay bankedStore one more cycle for L3 large sram timing.
* l2,l3: change mshr amount to 15
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| #
4e3ce935 |
| 22-Mar-2021 |
ljw <[email protected]> |
Beu: separate l1plus and icache (#705)
|
| #
329e267d |
| 21-Mar-2021 |
Yinan Xu <[email protected]> |
top: add TLXbar below L3
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| #
2e3a956e |
| 19-Mar-2021 |
LinJiawei <[email protected]> |
Top: add beu
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| #
6c4d7a40 |
| 19-Mar-2021 |
Yinan Xu <[email protected]> |
Add XSCoreWithL2 to wrap XSCore,L2 into a module (#696)
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| #
9d4d50e0 |
| 10-Mar-2021 |
Yinan Xu <[email protected]> |
Top: remove extra axi ID bits (#671)
* Top: remove extra axi ID bits
* Re-add AXI4UserYanker
Co-authored-by: LinJiawei <[email protected]>
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| #
8b037849 |
| 07-Mar-2021 |
Yinan Xu <[email protected]> |
Update SoC and verilog generation for FPGA/ASIC platform (#653)
* MySoc: verilog top
* MySoc: connect mmio
* MySoc: fix some bugs
* wip
* TopMain: remove to top
* WIP: add dma port
Update SoC and verilog generation for FPGA/ASIC platform (#653)
* MySoc: verilog top
* MySoc: connect mmio
* MySoc: fix some bugs
* wip
* TopMain: remove to top
* WIP: add dma port
* Update XSTop for FPGA/ASIC platform
* Top: add rocket-chip source
* Append SRAM to generated verilog
Co-authored-by: LinJiawei <[email protected]>
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