1/dts-v1/; 2 3/ { 4 #address-cells = <0x1>; 5 #size-cells = <0x1>; 6 compatible = "xlnx,zynq-7000"; 7 interrupt-parent = <0x1>; 8 model = "Xilinx Zynq ZED"; 9 10 cpus { 11 #address-cells = <0x1>; 12 #size-cells = <0x0>; 13 14 cpu@0 { 15 compatible = "arm,cortex-a9"; 16 device_type = "cpu"; 17 reg = <0x0>; 18 clocks = <0x2 0x3>; 19 clock-latency = <0x3e8>; 20 cpu0-supply = <0x3>; 21 operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>; 22 }; 23 24 cpu@1 { 25 compatible = "arm,cortex-a9"; 26 device_type = "cpu"; 27 reg = <0x1>; 28 clocks = <0x2 0x3>; 29 }; 30 }; 31 32 fpga-full { 33 compatible = "fpga-region"; 34 fpga-mgr = <0x4>; 35 #address-cells = <0x1>; 36 #size-cells = <0x1>; 37 ranges; 38 }; 39 40 pmu@f8891000 { 41 compatible = "arm,cortex-a9-pmu"; 42 interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>; 43 interrupt-parent = <0x1>; 44 reg = <0xf8891000 0x1000 0xf8893000 0x1000>; 45 }; 46 47 fixedregulator { 48 compatible = "regulator-fixed"; 49 regulator-name = "VCCPINT"; 50 regulator-min-microvolt = <0xf4240>; 51 regulator-max-microvolt = <0xf4240>; 52 regulator-boot-on; 53 regulator-always-on; 54 linux,phandle = <0x3>; 55 phandle = <0x3>; 56 }; 57 58 amba { 59 u-boot,dm-pre-reloc; 60 compatible = "simple-bus"; 61 #address-cells = <0x1>; 62 #size-cells = <0x1>; 63 interrupt-parent = <0x1>; 64 ranges; 65 66 adc@f8007100 { 67 compatible = "xlnx,zynq-xadc-1.00.a"; 68 reg = <0xf8007100 0x20>; 69 interrupts = <0x0 0x7 0x4>; 70 interrupt-parent = <0x1>; 71 clocks = <0x2 0xc>; 72 }; 73 74 can@e0008000 { 75 compatible = "xlnx,zynq-can-1.0"; 76 status = "disabled"; 77 clocks = <0x2 0x13 0x2 0x24>; 78 clock-names = "can_clk", "pclk"; 79 reg = <0xe0008000 0x1000>; 80 interrupts = <0x0 0x1c 0x4>; 81 interrupt-parent = <0x1>; 82 tx-fifo-depth = <0x40>; 83 rx-fifo-depth = <0x40>; 84 }; 85 86 can@e0009000 { 87 compatible = "xlnx,zynq-can-1.0"; 88 status = "disabled"; 89 clocks = <0x2 0x14 0x2 0x25>; 90 clock-names = "can_clk", "pclk"; 91 reg = <0xe0009000 0x1000>; 92 interrupts = <0x0 0x33 0x4>; 93 interrupt-parent = <0x1>; 94 tx-fifo-depth = <0x40>; 95 rx-fifo-depth = <0x40>; 96 }; 97 98 gpio@e000a000 { 99 compatible = "xlnx,zynq-gpio-1.0"; 100 #gpio-cells = <0x2>; 101 clocks = <0x2 0x2a>; 102 gpio-controller; 103 interrupt-controller; 104 #interrupt-cells = <0x2>; 105 interrupt-parent = <0x1>; 106 interrupts = <0x0 0x14 0x4>; 107 reg = <0xe000a000 0x1000>; 108 linux,phandle = <0x6>; 109 phandle = <0x6>; 110 }; 111 112 i2c@e0004000 { 113 compatible = "cdns,i2c-r1p10"; 114 status = "disabled"; 115 clocks = <0x2 0x26>; 116 interrupt-parent = <0x1>; 117 interrupts = <0x0 0x19 0x4>; 118 reg = <0xe0004000 0x1000>; 119 #address-cells = <0x1>; 120 #size-cells = <0x0>; 121 }; 122 123 i2c@e0005000 { 124 compatible = "cdns,i2c-r1p10"; 125 status = "disabled"; 126 clocks = <0x2 0x27>; 127 interrupt-parent = <0x1>; 128 interrupts = <0x0 0x30 0x4>; 129 reg = <0xe0005000 0x1000>; 130 #address-cells = <0x1>; 131 #size-cells = <0x0>; 132 }; 133 134 interrupt-controller@f8f01000 { 135 compatible = "arm,cortex-a9-gic"; 136 #interrupt-cells = <0x3>; 137 interrupt-controller; 138 reg = <0xf8f01000 0x1000 0xf8f00100 0x100>; 139 linux,phandle = <0x1>; 140 phandle = <0x1>; 141 }; 142 143 cache-controller@f8f02000 { 144 compatible = "arm,pl310-cache"; 145 reg = <0xf8f02000 0x1000>; 146 interrupts = <0x0 0x2 0x4>; 147 arm,data-latency = <0x3 0x2 0x2>; 148 arm,tag-latency = <0x2 0x2 0x2>; 149 cache-unified; 150 cache-level = <0x2>; 151 }; 152 153 memory-controller@f8006000 { 154 compatible = "xlnx,zynq-ddrc-a05"; 155 reg = <0xf8006000 0x1000>; 156 }; 157 158 ocmc@f800c000 { 159 compatible = "xlnx,zynq-ocmc-1.0"; 160 interrupt-parent = <0x1>; 161 interrupts = <0x0 0x3 0x4>; 162 reg = <0xf800c000 0x1000>; 163 }; 164 165 serial@e0000000 { 166 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 167 status = "disabled"; 168 clocks = <0x2 0x17 0x2 0x28>; 169 clock-names = "uart_clk", "pclk"; 170 reg = <0xe0000000 0x1000>; 171 interrupts = <0x0 0x1b 0x4>; 172 }; 173 174 serial@e0001000 { 175 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 176 status = "okay"; 177 clocks = <0x2 0x18 0x2 0x29>; 178 clock-names = "uart_clk", "pclk"; 179 reg = <0xe0001000 0x1000>; 180 interrupts = <0x0 0x32 0x4>; 181 }; 182 183 spi@e0006000 { 184 compatible = "xlnx,zynq-spi-r1p6"; 185 reg = <0xe0006000 0x1000>; 186 status = "okay"; 187 interrupt-parent = <0x1>; 188 interrupts = <0x0 0x1a 0x4>; 189 clocks = <0x2 0x19 0x2 0x22>; 190 clock-names = "ref_clk", "pclk"; 191 #address-cells = <0x1>; 192 #size-cells = <0x0>; 193 194 ad9361-phy@0 { 195 #address-cells = <0x1>; 196 #size-cells = <0x0>; 197 #clock-cells = <0x1>; 198 compatible = "adi,ad9361"; 199 reg = <0x0>; 200 spi-cpha; 201 spi-max-frequency = <0x989680>; 202 clocks = <0x5 0x0>; 203 clock-names = "ad9361_ext_refclk"; 204 clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; 205 adi,digital-interface-tune-skip-mode = <0x0>; 206 adi,pp-tx-swap-enable; 207 adi,pp-rx-swap-enable; 208 adi,rx-frame-pulse-mode-enable; 209 adi,lvds-mode-enable; 210 adi,lvds-bias-mV = <0x96>; 211 adi,lvds-rx-onchip-termination-enable; 212 adi,rx-data-delay = <0x4>; 213 adi,tx-fb-clock-delay = <0x7>; 214 adi,dcxo-coarse-and-fine-tune = <0x8 0x1720>; 215 adi,2rx-2tx-mode-enable; 216 adi,frequency-division-duplex-mode-enable; 217 adi,rx-rf-port-input-select = <0x0>; 218 adi,tx-rf-port-input-select = <0x0>; 219 adi,tx-attenuation-mdB = <0x2710>; 220 adi,rf-rx-bandwidth-hz = <0x112a880>; 221 adi,rf-tx-bandwidth-hz = <0x112a880>; 222 adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>; 223 adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>; 224 adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 225 adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 226 adi,gc-rx1-mode = <0x2>; 227 adi,gc-rx2-mode = <0x2>; 228 adi,gc-adc-ovr-sample-size = <0x4>; 229 adi,gc-adc-small-overload-thresh = <0x2f>; 230 adi,gc-adc-large-overload-thresh = <0x3a>; 231 adi,gc-lmt-overload-high-thresh = <0x320>; 232 adi,gc-lmt-overload-low-thresh = <0x2c0>; 233 adi,gc-dec-pow-measurement-duration = <0x2000>; 234 adi,gc-low-power-thresh = <0x18>; 235 adi,mgc-inc-gain-step = <0x2>; 236 adi,mgc-dec-gain-step = <0x2>; 237 adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>; 238 adi,agc-attack-delay-extra-margin-us = <0x1>; 239 adi,agc-outer-thresh-high = <0x5>; 240 adi,agc-outer-thresh-high-dec-steps = <0x2>; 241 adi,agc-inner-thresh-high = <0xa>; 242 adi,agc-inner-thresh-high-dec-steps = <0x1>; 243 adi,agc-inner-thresh-low = <0xc>; 244 adi,agc-inner-thresh-low-inc-steps = <0x1>; 245 adi,agc-outer-thresh-low = <0x12>; 246 adi,agc-outer-thresh-low-inc-steps = <0x2>; 247 adi,agc-adc-small-overload-exceed-counter = <0xa>; 248 adi,agc-adc-large-overload-exceed-counter = <0xa>; 249 adi,agc-adc-large-overload-inc-steps = <0x2>; 250 adi,agc-lmt-overload-large-exceed-counter = <0xa>; 251 adi,agc-lmt-overload-small-exceed-counter = <0xa>; 252 adi,agc-lmt-overload-large-inc-steps = <0x2>; 253 adi,agc-gain-update-interval-us = <0x3e8>; 254 adi,fagc-dec-pow-measurement-duration = <0x40>; 255 adi,fagc-lp-thresh-increment-steps = <0x1>; 256 adi,fagc-lp-thresh-increment-time = <0x5>; 257 adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>; 258 adi,fagc-final-overrange-count = <0x3>; 259 adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>; 260 adi,fagc-lmt-final-settling-steps = <0x1>; 261 adi,fagc-lock-level = <0xa>; 262 adi,fagc-lock-level-gain-increase-upper-limit = <0x5>; 263 adi,fagc-lock-level-lmt-gain-increase-enable; 264 adi,fagc-lpf-final-settling-steps = <0x1>; 265 adi,fagc-optimized-gain-offset = <0x5>; 266 adi,fagc-power-measurement-duration-in-state5 = <0x40>; 267 adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable; 268 adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>; 269 adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable; 270 adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>; 271 adi,fagc-rst-gla-large-adc-overload-enable; 272 adi,fagc-rst-gla-large-lmt-overload-enable; 273 adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>; 274 adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable; 275 adi,fagc-state-wait-time-ns = <0x104>; 276 adi,fagc-use-last-lock-level-for-set-gain-enable; 277 adi,rssi-restart-mode = <0x3>; 278 adi,rssi-delay = <0x1>; 279 adi,rssi-wait = <0x1>; 280 adi,rssi-duration = <0x3e8>; 281 adi,ctrl-outs-index = <0x0>; 282 adi,ctrl-outs-enable-mask = <0xff>; 283 adi,temp-sense-measurement-interval-ms = <0x3e8>; 284 adi,temp-sense-offset-signed = <0xce>; 285 adi,temp-sense-periodic-measurement-enable; 286 adi,aux-dac-manual-mode-enable; 287 adi,aux-dac1-default-value-mV = <0x0>; 288 adi,aux-dac1-rx-delay-us = <0x0>; 289 adi,aux-dac1-tx-delay-us = <0x0>; 290 adi,aux-dac2-default-value-mV = <0x0>; 291 adi,aux-dac2-rx-delay-us = <0x0>; 292 adi,aux-dac2-tx-delay-us = <0x0>; 293 en_agc-gpios = <0x6 0x62 0x0>; 294 sync-gpios = <0x6 0x63 0x0>; 295 reset-gpios = <0x6 0x64 0x0>; 296 enable-gpios = <0x6 0x65 0x0>; 297 txnrx-gpios = <0x6 0x66 0x0>; 298 linux,phandle = <0x11>; 299 phandle = <0x11>; 300 }; 301 }; 302 303 spi@e0007000 { 304 compatible = "xlnx,zynq-spi-r1p6"; 305 reg = <0xe0007000 0x1000>; 306 status = "okay"; 307 interrupt-parent = <0x1>; 308 interrupts = <0x0 0x31 0x4>; 309 clocks = <0x2 0x1a 0x2 0x23>; 310 clock-names = "ref_clk", "pclk"; 311 #address-cells = <0x1>; 312 #size-cells = <0x0>; 313 314 adf4351-udc-tx-pmod@0 { 315 #address-cells = <0x1>; 316 #size-cells = <0x0>; 317 compatible = "adi,adf4351"; 318 reg = <0x0>; 319 spi-max-frequency = <0x989680>; 320 clocks = <0x7>; 321 clock-names = "clkin"; 322 adi,channel-spacing = <0xf4240>; 323 adi,power-up-frequency = <0x160dc080>; 324 adi,phase-detector-polarity-positive-enable; 325 adi,charge-pump-current = <0x9c4>; 326 adi,output-power = <0x3>; 327 adi,mute-till-lock-enable; 328 adi,muxout-select = <0x6>; 329 gpios = <0x6 0x68 0x0>; 330 }; 331 332 adf4351-udc-rx-pmod@1 { 333 #address-cells = <0x1>; 334 #size-cells = <0x0>; 335 compatible = "adi,adf4351"; 336 reg = <0x1>; 337 spi-max-frequency = <0x989680>; 338 clocks = <0x7>; 339 clock-names = "clkin"; 340 adi,channel-spacing = <0xf4240>; 341 adi,power-up-frequency = <0x1443fd00>; 342 adi,phase-detector-polarity-positive-enable; 343 adi,charge-pump-current = <0x9c4>; 344 adi,output-power = <0x3>; 345 adi,mute-till-lock-enable; 346 adi,muxout-select = <0x6>; 347 gpios = <0x6 0x67 0x0>; 348 }; 349 }; 350 351 spi@e000d000 { 352 clock-names = "ref_clk", "pclk"; 353 clocks = <0x2 0xa 0x2 0x2b>; 354 compatible = "xlnx,zynq-qspi-1.0"; 355 status = "okay"; 356 interrupt-parent = <0x1>; 357 interrupts = <0x0 0x13 0x4>; 358 reg = <0xe000d000 0x1000>; 359 #address-cells = <0x1>; 360 #size-cells = <0x0>; 361 is-dual = <0x0>; 362 num-cs = <0x1>; 363 364 ps7-qspi@0 { 365 #address-cells = <0x1>; 366 #size-cells = <0x1>; 367 compatible = "n25q128a11"; 368 reg = <0x0>; 369 spi-max-frequency = <0x2faf080>; 370 371 partition@0 { 372 label = "boot"; 373 reg = <0x0 0x500000>; 374 }; 375 376 partition@500000 { 377 label = "bootenv"; 378 reg = <0x500000 0x20000>; 379 }; 380 381 partition@520000 { 382 label = "config"; 383 reg = <0x520000 0x20000>; 384 }; 385 386 partition@540000 { 387 label = "image"; 388 reg = <0x540000 0xa80000>; 389 }; 390 391 partition@fc0000 { 392 label = "spare"; 393 reg = <0xfc0000 0x0>; 394 }; 395 }; 396 }; 397 398 memory-controller@e000e000 { 399 #address-cells = <0x1>; 400 #size-cells = <0x1>; 401 status = "disabled"; 402 clock-names = "memclk", "aclk"; 403 clocks = <0x2 0xb 0x2 0x2c>; 404 compatible = "arm,pl353-smc-r2p1"; 405 interrupt-parent = <0x1>; 406 interrupts = <0x0 0x12 0x4>; 407 ranges; 408 reg = <0xe000e000 0x1000>; 409 410 flash@e1000000 { 411 status = "disabled"; 412 compatible = "arm,pl353-nand-r2p1"; 413 reg = <0xe1000000 0x1000000>; 414 #address-cells = <0x1>; 415 #size-cells = <0x1>; 416 }; 417 418 flash@e2000000 { 419 status = "disabled"; 420 compatible = "cfi-flash"; 421 reg = <0xe2000000 0x2000000>; 422 #address-cells = <0x1>; 423 #size-cells = <0x1>; 424 }; 425 }; 426 427 ethernet@e000b000 { 428 compatible = "cdns,zynq-gem", "cdns,gem"; 429 reg = <0xe000b000 0x1000>; 430 status = "okay"; 431 interrupts = <0x0 0x16 0x4>; 432 clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>; 433 clock-names = "pclk", "hclk", "tx_clk"; 434 #address-cells = <0x1>; 435 #size-cells = <0x0>; 436 phy-handle = <0x8>; 437 phy-mode = "rgmii-id"; 438 439 phy@0 { 440 device_type = "ethernet-phy"; 441 reg = <0x0>; 442 marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0xa>; 443 linux,phandle = <0x8>; 444 phandle = <0x8>; 445 }; 446 }; 447 448 ethernet@e000c000 { 449 compatible = "cdns,zynq-gem", "cdns,gem"; 450 reg = <0xe000c000 0x1000>; 451 status = "disabled"; 452 interrupts = <0x0 0x2d 0x4>; 453 clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>; 454 clock-names = "pclk", "hclk", "tx_clk"; 455 #address-cells = <0x1>; 456 #size-cells = <0x0>; 457 }; 458 459 sdhci@e0100000 { 460 compatible = "arasan,sdhci-8.9a"; 461 status = "okay"; 462 clock-names = "clk_xin", "clk_ahb"; 463 clocks = <0x2 0x15 0x2 0x20>; 464 interrupt-parent = <0x1>; 465 interrupts = <0x0 0x18 0x4>; 466 reg = <0xe0100000 0x1000>; 467 broken-adma2; 468 }; 469 470 sdhci@e0101000 { 471 compatible = "arasan,sdhci-8.9a"; 472 status = "disabled"; 473 clock-names = "clk_xin", "clk_ahb"; 474 clocks = <0x2 0x16 0x2 0x21>; 475 interrupt-parent = <0x1>; 476 interrupts = <0x0 0x2f 0x4>; 477 reg = <0xe0101000 0x1000>; 478 broken-adma2; 479 }; 480 481 slcr@f8000000 { 482 #address-cells = <0x1>; 483 #size-cells = <0x1>; 484 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; 485 reg = <0xf8000000 0x1000>; 486 ranges; 487 linux,phandle = <0x9>; 488 phandle = <0x9>; 489 490 clkc@100 { 491 #clock-cells = <0x1>; 492 compatible = "xlnx,ps7-clkc"; 493 fclk-enable = <0xf>; 494 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; 495 reg = <0x100 0x100>; 496 ps-clk-frequency = <0x1fca055>; 497 linux,phandle = <0x2>; 498 phandle = <0x2>; 499 }; 500 501 rstc@200 { 502 compatible = "xlnx,zynq-reset"; 503 reg = <0x200 0x48>; 504 #reset-cells = <0x1>; 505 syscon = <0x9>; 506 }; 507 508 pinctrl@700 { 509 compatible = "xlnx,pinctrl-zynq"; 510 reg = <0x700 0x200>; 511 syscon = <0x9>; 512 }; 513 }; 514 515 dmac@f8003000 { 516 compatible = "arm,pl330", "arm,primecell"; 517 reg = <0xf8003000 0x1000>; 518 interrupt-parent = <0x1>; 519 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; 520 interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>; 521 #dma-cells = <0x1>; 522 #dma-channels = <0x8>; 523 #dma-requests = <0x4>; 524 clocks = <0x2 0x1b>; 525 clock-names = "apb_pclk"; 526 linux,phandle = <0xf>; 527 phandle = <0xf>; 528 }; 529 530 devcfg@f8007000 { 531 compatible = "xlnx,zynq-devcfg-1.0"; 532 interrupt-parent = <0x1>; 533 interrupts = <0x0 0x8 0x4>; 534 reg = <0xf8007000 0x100>; 535 clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>; 536 clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; 537 syscon = <0x9>; 538 linux,phandle = <0x4>; 539 phandle = <0x4>; 540 }; 541 542 efuse@f800d000 { 543 compatible = "xlnx,zynq-efuse"; 544 reg = <0xf800d000 0x20>; 545 }; 546 547 timer@f8f00200 { 548 compatible = "arm,cortex-a9-global-timer"; 549 reg = <0xf8f00200 0x20>; 550 interrupts = <0x1 0xb 0x301>; 551 interrupt-parent = <0x1>; 552 clocks = <0x2 0x4>; 553 }; 554 555 timer@f8001000 { 556 interrupt-parent = <0x1>; 557 interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>; 558 compatible = "cdns,ttc"; 559 clocks = <0x2 0x6>; 560 reg = <0xf8001000 0x1000>; 561 }; 562 563 timer@f8002000 { 564 interrupt-parent = <0x1>; 565 interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>; 566 compatible = "cdns,ttc"; 567 clocks = <0x2 0x6>; 568 reg = <0xf8002000 0x1000>; 569 }; 570 571 timer@f8f00600 { 572 interrupt-parent = <0x1>; 573 interrupts = <0x1 0xd 0x301>; 574 compatible = "arm,cortex-a9-twd-timer"; 575 reg = <0xf8f00600 0x20>; 576 clocks = <0x2 0x4>; 577 }; 578 579 usb@e0002000 { 580 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 581 status = "okay"; 582 clocks = <0x2 0x1c>; 583 interrupt-parent = <0x1>; 584 interrupts = <0x0 0x15 0x4>; 585 reg = <0xe0002000 0x1000>; 586 phy_type = "ulpi"; 587 dr_mode = "host"; 588 xlnx,phy-reset-gpio = <0x6 0x55 0x0>; 589 }; 590 591 usb@e0003000 { 592 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 593 status = "disabled"; 594 clocks = <0x2 0x1d>; 595 interrupt-parent = <0x1>; 596 interrupts = <0x0 0x2c 0x4>; 597 reg = <0xe0003000 0x1000>; 598 phy_type = "ulpi"; 599 }; 600 601 watchdog@f8005000 { 602 clocks = <0x2 0x2d>; 603 compatible = "cdns,wdt-r1p2"; 604 interrupt-parent = <0x1>; 605 interrupts = <0x0 0x9 0x1>; 606 reg = <0xf8005000 0x1000>; 607 timeout-sec = <0xa>; 608 }; 609 }; 610 611 aliases { 612 ethernet0 = "/amba/ethernet@e000b000"; 613 serial0 = "/amba/serial@e0001000"; 614 }; 615 616 memory { 617 device_type = "memory"; 618 reg = <0x0 0x20000000>; 619 }; 620 621 chosen { 622 bootargs = "console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait"; 623 linux,stdout-path = "/amba@0/uart@E0001000"; 624 }; 625 626 fpga-axi@0 { 627 compatible = "simple-bus"; 628 #address-cells = <0x1>; 629 #size-cells = <0x1>; 630 ranges; 631 632 i2c@41600000 { 633 compatible = "xlnx,axi-iic-1.01.b", "xlnx,xps-iic-2.00.a"; 634 reg = <0x41600000 0x10000>; 635 interrupt-parent = <0x1>; 636 interrupts = <0x0 0x3a 0x4>; 637 clocks = <0x2 0xf>; 638 clock-names = "pclk"; 639 #size-cells = <0x0>; 640 #address-cells = <0x1>; 641 642 adv7511@39 { 643 compatible = "adi,adv7511"; 644 reg = <0x39 0x3f>; 645 reg-names = "primary", "edid"; 646 adi,input-depth = <0x8>; 647 adi,input-colorspace = "yuv422"; 648 adi,input-clock = "1x"; 649 adi,input-style = <0x1>; 650 adi,input-justification = "right"; 651 adi,clock-delay = <0x0>; 652 #sound-dai-cells = <0x0>; 653 linux,phandle = <0x14>; 654 phandle = <0x14>; 655 656 ports { 657 #address-cells = <0x1>; 658 #size-cells = <0x0>; 659 660 port@0 { 661 reg = <0x0>; 662 663 endpoint { 664 remote-endpoint = <0xa>; 665 linux,phandle = <0xe>; 666 phandle = <0xe>; 667 }; 668 }; 669 670 port@1 { 671 reg = <0x1>; 672 }; 673 }; 674 }; 675 676 adau1761@3b { 677 compatible = "adi,adau1761"; 678 reg = <0x3b>; 679 clocks = <0xb>; 680 clock-names = "mclk"; 681 #sound-dai-cells = <0x0>; 682 linux,phandle = <0x16>; 683 phandle = <0x16>; 684 }; 685 }; 686 687/* 688 axivdma@43000000 { 689 compatible = "xlnx,axi-vdma-1.00.a"; 690 #address-cells = <0x1>; 691 #size-cells = <0x1>; 692 #dma-cells = <0x1>; 693 #dma-channels = <0x1>; 694 reg = <0x43000000 0x1000>; 695 xlnx,num-fstores = <0x3>; 696 linux,phandle = <0xc>; 697 phandle = <0xc>; 698 699 dma-channel@43000000 { 700 compatible = "xlnx,axi-vdma-mm2s-channel"; 701 interrupts = <0x0 0x3b 0x4>; 702 xlnx,datawidth = <0x40>; 703 xlnx,genlock-mode = <0x0>; 704 xlnx,include-dre = <0x0>; 705 }; 706 }; 707 708 axi-clkgen@79000000 { 709 compatible = "adi,axi-clkgen-2.00.a"; 710 reg = <0x79000000 0x10000>; 711 #clock-cells = <0x0>; 712 clocks = <0x2 0x10>; 713 linux,phandle = <0xd>; 714 phandle = <0xd>; 715 }; 716 717 axi_hdmi@70e00000 { 718 compatible = "adi,axi-hdmi-tx-1.00.a"; 719 reg = <0x70e00000 0x10000>; 720 dmas = <0xc 0x0>; 721 dma-names = "video"; 722 clocks = <0xd>; 723 724 port { 725 726 endpoint { 727 remote-endpoint = <0xe>; 728 linux,phandle = <0xa>; 729 phandle = <0xa>; 730 }; 731 }; 732 }; 733 734 axi-spdif-tx@75c00000 { 735 compatible = "adi,axi-spdif-tx-1.00.a"; 736 reg = <0x75c00000 0x1000>; 737 dmas = <0xf 0x0>; 738 dma-names = "tx"; 739 clocks = <0x2 0xf 0xb>; 740 clock-names = "axi", "ref"; 741 #sound-dai-cells = <0x0>; 742 linux,phandle = <0x13>; 743 phandle = <0x13>; 744 }; 745*/ 746 747 axi-i2s@77600000 { 748 compatible = "adi,axi-i2s-1.00.a"; 749 reg = <0x77600000 0x1000>; 750 dmas = <0xf 0x1 0xf 0x2>; 751 dma-names = "tx", "rx"; 752 clocks = <0x2 0xf 0xb>; 753 clock-names = "axi", "ref"; 754 #sound-dai-cells = <0x0>; 755 linux,phandle = <0x15>; 756 phandle = <0x15>; 757 }; 758 759 i2c@41620000 { 760 compatible = "xlnx,axi-iic-1.01.b", "xlnx,xps-iic-2.00.a"; 761 reg = <0x41620000 0x10000>; 762 interrupt-parent = <0x1>; 763 interrupts = <0x0 0x37 0x4>; 764 clocks = <0x2 0xf>; 765 clock-names = "pclk"; 766 #size-cells = <0x0>; 767 #address-cells = <0x1>; 768 769 ad7291@2f { 770 compatible = "adi,ad7291"; 771 reg = <0x2f>; 772 }; 773 774 eeprom@50 { 775 compatible = "at24,24c02"; 776 reg = <0x50>; 777 }; 778 }; 779 780 dma@7c400000 { 781 compatible = "adi,axi-dmac-1.00.a"; 782 reg = <0x7c400000 0x10000>; 783 #dma-cells = <0x1>; 784 interrupts = <0x0 0x39 0x0>; 785 clocks = <0x2 0x10>; 786 linux,phandle = <0x10>; 787 phandle = <0x10>; 788 789 adi,channels { 790 #size-cells = <0x0>; 791 #address-cells = <0x1>; 792 793 dma-channel@0 { 794 reg = <0x0>; 795 adi,source-bus-width = <0x40>; 796 adi,source-bus-type = <0x2>; 797 adi,destination-bus-width = <0x40>; 798 adi,destination-bus-type = <0x0>; 799 adi,length-width = <0x18>; 800 }; 801 }; 802 }; 803 804 dma@7c420000 { 805 compatible = "adi,axi-dmac-1.00.a"; 806 reg = <0x7c420000 0x10000>; 807 #dma-cells = <0x1>; 808 interrupts = <0x0 0x38 0x0>; 809 clocks = <0x2 0x10>; 810 linux,phandle = <0x12>; 811 phandle = <0x12>; 812 813 adi,channels { 814 #size-cells = <0x0>; 815 #address-cells = <0x1>; 816 817 dma-channel@0 { 818 reg = <0x0>; 819 adi,source-bus-width = <0x40>; 820 adi,source-bus-type = <0x0>; 821 adi,destination-bus-width = <0x40>; 822 adi,destination-bus-type = <0x2>; 823 adi,length-width = <0x18>; 824 adi,cyclic; 825 }; 826 }; 827 }; 828 829 sdr: sdr { 830 compatible ="sdr,sdr"; 831 dmas = <&rx_dma 0 832 &rx_dma 1 833 &tx_dma 0 834 &tx_dma 1>; 835 dma-names = "rx_dma_mm2s", "rx_dma_s2mm", "tx_dma_mm2s", "tx_dma_s2mm"; 836 interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt0", "tx_itrpt1"; 837 interrupt-parent = <1>; 838 interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>; 839 } ; 840 841 axidmatest_1: axidmatest@1 { 842 compatible ="xlnx,axi-dma-test-1.00.a"; 843 dmas = <&rx_dma 0 844 &rx_dma 1>; 845 dma-names = "axidma0", "axidma1"; 846 } ; 847 848 tx_dma: dma@80400000 { 849 #dma-cells = <1>; 850 clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; 851 clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 852 compatible = "xlnx,axi-dma-1.00.a"; 853 interrupt-names = "mm2s_introut", "s2mm_introut"; 854 interrupt-parent = <1>; 855 interrupts = <0 35 4 0 36 4>; 856 reg = <0x80400000 0x10000>; 857 xlnx,addrwidth = <0x20>; 858 xlnx,include-sg ; 859 xlnx,sg-length-width = <0xe>; 860 dma-channel@80400000 { 861 compatible = "xlnx,axi-dma-mm2s-channel"; 862 dma-channels = <0x1>; 863 interrupts = <0 35 4>; 864 xlnx,datawidth = <0x40>; 865 xlnx,device-id = <0x0>; 866 }; 867 dma-channel@80400030 { 868 compatible = "xlnx,axi-dma-s2mm-channel"; 869 dma-channels = <0x1>; 870 interrupts = <0 36 4>; 871 xlnx,datawidth = <0x40>; 872 xlnx,device-id = <0x0>; 873 }; 874 }; 875 876 rx_dma: dma@80410000 { 877 #dma-cells = <1>; 878 clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; 879 clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 880 compatible = "xlnx,axi-dma-1.00.a"; 881 //dma-coherent ; 882 interrupt-names = "mm2s_introut", "s2mm_introut"; 883 interrupt-parent = <1>; 884 interrupts = <0 31 4 0 32 4>; 885 reg = <0x80410000 0x10000>; 886 xlnx,addrwidth = <0x20>; 887 xlnx,include-sg ; 888 xlnx,sg-length-width = <0xe>; 889 dma-channel@80410000 { 890 compatible = "xlnx,axi-dma-mm2s-channel"; 891 dma-channels = <0x1>; 892 interrupts = <0 31 4>; 893 xlnx,datawidth = <0x40>; 894 xlnx,device-id = <0x1>; 895 }; 896 dma-channel@80410030 { 897 compatible = "xlnx,axi-dma-s2mm-channel"; 898 dma-channels = <0x1>; 899 interrupts = <0 32 4>; 900 xlnx,datawidth = <0x40>; 901 xlnx,device-id = <0x1>; 902 }; 903 }; 904 905 tx_intf_0: tx_intf@83c00000 { 906 clock-names = "s00_axi_aclk", "s00_axis_aclk", "s01_axis_aclk", "m00_axis_aclk"; 907 clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 908 compatible = "sdr,tx_intf"; 909 interrupt-names = "tx_itrpt0", "tx_itrpt1"; 910 interrupt-parent = <1>; 911 interrupts = <0 33 1 0 34 1>; 912 reg = <0x83c00000 0x10000>; 913 xlnx,s00-axi-addr-width = <0x7>; 914 xlnx,s00-axi-data-width = <0x20>; 915 }; 916 917 rx_intf_0: rx_intf@83c20000 { 918 clock-names = "s00_axi_aclk", "s00_axis_aclk", "m00_axis_aclk"; 919 clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 920 compatible = "sdr,rx_intf"; 921 interrupt-names = "not_valid_anymore", "rx_pkt_intr"; 922 interrupt-parent = <1>; 923 interrupts = <0 29 1 0 30 1>; 924 reg = <0x83c20000 0x10000>; 925 xlnx,s00-axi-addr-width = <0x7>; 926 xlnx,s00-axi-data-width = <0x20>; 927 }; 928 929 openofdm_tx_0: openofdm_tx@83c10000 { 930 clock-names = "clk"; 931 clocks = <0x2 0x11>; 932 compatible = "sdr,openofdm_tx"; 933 reg = <0x83c10000 0x10000>; 934 }; 935 936 openofdm_rx_0: openofdm_rx@83c30000 { 937 clock-names = "clk"; 938 clocks = <0x2 0x11>; 939 compatible = "sdr,openofdm_rx"; 940 reg = <0x83c30000 0x10000>; 941 }; 942 943 xpu_0: xpu@83c40000 { 944 clock-names = "s00_axi_aclk"; 945 clocks = <0x2 0x11>; 946 compatible = "sdr,xpu"; 947 reg = <0x83c40000 0x10000>; 948 }; 949 950 cf-ad9361-lpc@79020000 { 951 compatible = "adi,axi-ad9361-6.00.a"; 952 reg = <0x79020000 0x6000>; 953 dmas = <0x10 0x0>; 954 dma-names = "rx"; 955 spibus-connected = <0x11>; 956 }; 957 958 cf-ad9361-dds-core-lpc@79024000 { 959 compatible = "adi,axi-ad9361-dds-6.00.a"; 960 reg = <0x79024000 0x1000>; 961 clocks = <0x11 0xd>; 962 clock-names = "sampl_clk"; 963 dmas = <0x12 0x0>; 964 dma-names = "tx"; 965 }; 966 }; 967 968/* 969 audio_clock { 970 compatible = "fixed-clock"; 971 #clock-cells = <0x0>; 972 clock-frequency = <0xbb8000>; 973 linux,phandle = <0xb>; 974 phandle = <0xb>; 975 }; 976 977 adv7511_hdmi_snd { 978 compatible = "simple-audio-card"; 979 simple-audio-card,name = "HDMI monitor"; 980 simple-audio-card,widgets = "Speaker", "Speaker"; 981 simple-audio-card,routing = "Speaker", "TX"; 982 983 simple-audio-card,dai-link@0 { 984 format = "spdif"; 985 986 cpu { 987 sound-dai = <0x13>; 988 frame-master; 989 bitclock-master; 990 }; 991 992 codec { 993 sound-dai = <0x14>; 994 }; 995 }; 996 }; 997 998 zed_sound { 999 compatible = "simple-audio-card"; 1000 simple-audio-card,name = "ZED ADAU1761"; 1001 simple-audio-card,widgets = "Microphone", "Mic In", "Headphone", "Headphone Out", "Line", "Line In", "Line", "Line Out"; 1002 simple-audio-card,routing = "Line Out", "LOUT", "Line Out", "ROUT", "Headphone Out", "LHP", "Headphone Out", "RHP", "Mic In", "MICBIAS", "LINN", "Mic In", "RINN", "Mic In", "LAUX", "Line In", "RAUX", "Line In"; 1003 1004 simple-audio-card,dai-link@0 { 1005 format = "i2s"; 1006 1007 cpu { 1008 sound-dai = <0x15>; 1009 frame-master; 1010 bitclock-master; 1011 }; 1012 1013 codec { 1014 sound-dai = <0x16>; 1015 }; 1016 }; 1017 }; 1018*/ 1019 1020 leds { 1021 compatible = "gpio-leds"; 1022 1023 ld0 { 1024 label = "ld0:red"; 1025 gpios = <0x6 0x49 0x0>; 1026 }; 1027 1028 ld1 { 1029 label = "ld1:red"; 1030 gpios = <0x6 0x4a 0x0>; 1031 }; 1032 1033 ld2 { 1034 label = "ld2:red"; 1035 gpios = <0x6 0x4b 0x0>; 1036 }; 1037 1038 ld3 { 1039 label = "ld3:red"; 1040 gpios = <0x6 0x4c 0x0>; 1041 }; 1042 1043 ld4 { 1044 label = "ld4:red"; 1045 gpios = <0x6 0x4d 0x0>; 1046 }; 1047 1048 ld5 { 1049 label = "ld5:red"; 1050 gpios = <0x6 0x4e 0x0>; 1051 }; 1052 1053 ld6 { 1054 label = "ld6:red"; 1055 gpios = <0x6 0x4f 0x0>; 1056 }; 1057 1058 ld7 { 1059 label = "ld7:red"; 1060 gpios = <0x6 0x50 0x0>; 1061 }; 1062 }; 1063 1064 clocks { 1065 1066 clock@0 { 1067 #clock-cells = <0x0>; 1068 compatible = "fixed-clock"; 1069 clock-frequency = <0x2625a00>; 1070 clock-output-names = "ad9361_ext_refclk"; 1071 linux,phandle = <0x5>; 1072 phandle = <0x5>; 1073 }; 1074 1075 clock@1 { 1076 #clock-cells = <0x0>; 1077 compatible = "fixed-clock"; 1078 clock-frequency = <0x17d7840>; 1079 clock-output-names = "refclk"; 1080 linux,phandle = <0x7>; 1081 phandle = <0x7>; 1082 }; 1083 }; 1084}; 1085