1/dts-v1/; 2 3/ { 4 #address-cells = <0x01>; 5 #size-cells = <0x01>; 6 compatible = "xlnx,zynq-7000"; 7 interrupt-parent = <0x01>; 8 model = "Analog Devices ADRV9364-Z7020 (Z7020/AD9364)"; 9 10 cpus { 11 #address-cells = <0x01>; 12 #size-cells = <0x00>; 13 14 cpu@0 { 15 compatible = "arm,cortex-a9"; 16 device_type = "cpu"; 17 reg = <0x00>; 18 clocks = <0x02 0x03>; 19 clock-latency = <0x3e8>; 20 cpu0-supply = <0x03>; 21 operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>; 22 phandle = <0x11>; 23 }; 24 25 cpu@1 { 26 compatible = "arm,cortex-a9"; 27 device_type = "cpu"; 28 reg = <0x01>; 29 clocks = <0x02 0x03>; 30 phandle = <0x13>; 31 }; 32 }; 33 34 fpga-full { 35 compatible = "fpga-region"; 36 fpga-mgr = <0x04>; 37 #address-cells = <0x01>; 38 #size-cells = <0x01>; 39 ranges; 40 phandle = <0x19>; 41 }; 42 43 pmu@f8891000 { 44 compatible = "arm,cortex-a9-pmu"; 45 interrupts = <0x00 0x05 0x04 0x00 0x06 0x04>; 46 interrupt-parent = <0x01>; 47 reg = <0xf8891000 0x1000 0xf8893000 0x1000>; 48 }; 49 50 fixedregulator { 51 compatible = "regulator-fixed"; 52 regulator-name = "VCCPINT"; 53 regulator-min-microvolt = <0xf4240>; 54 regulator-max-microvolt = <0xf4240>; 55 regulator-boot-on; 56 regulator-always-on; 57 phandle = <0x03>; 58 }; 59 60 replicator { 61 compatible = "arm,coresight-static-replicator"; 62 clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; 63 clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; 64 65 out-ports { 66 #address-cells = <0x01>; 67 #size-cells = <0x00>; 68 69 port@0 { 70 reg = <0x00>; 71 72 endpoint { 73 remote-endpoint = <0x05>; 74 phandle = <0x0d>; 75 }; 76 }; 77 78 port@1 { 79 reg = <0x01>; 80 81 endpoint { 82 remote-endpoint = <0x06>; 83 phandle = <0x0c>; 84 }; 85 }; 86 }; 87 88 in-ports { 89 90 port { 91 92 endpoint { 93 remote-endpoint = <0x07>; 94 phandle = <0x0e>; 95 }; 96 }; 97 }; 98 }; 99 100 axi { 101 u-boot,dm-pre-reloc; 102 compatible = "simple-bus"; 103 #address-cells = <0x01>; 104 #size-cells = <0x01>; 105 interrupt-parent = <0x01>; 106 ranges; 107 phandle = <0x1a>; 108 109 adc@f8007100 { 110 compatible = "xlnx,zynq-xadc-1.00.a"; 111 reg = <0xf8007100 0x20>; 112 interrupts = <0x00 0x07 0x04>; 113 interrupt-parent = <0x01>; 114 clocks = <0x02 0x0c>; 115 phandle = <0x1b>; 116 }; 117 118 can@e0008000 { 119 compatible = "xlnx,zynq-can-1.0"; 120 status = "disabled"; 121 clocks = <0x02 0x13 0x02 0x24>; 122 clock-names = "can_clk\0pclk"; 123 reg = <0xe0008000 0x1000>; 124 interrupts = <0x00 0x1c 0x04>; 125 interrupt-parent = <0x01>; 126 tx-fifo-depth = <0x40>; 127 rx-fifo-depth = <0x40>; 128 phandle = <0x1c>; 129 }; 130 131 can@e0009000 { 132 compatible = "xlnx,zynq-can-1.0"; 133 status = "disabled"; 134 clocks = <0x02 0x14 0x02 0x25>; 135 clock-names = "can_clk\0pclk"; 136 reg = <0xe0009000 0x1000>; 137 interrupts = <0x00 0x33 0x04>; 138 interrupt-parent = <0x01>; 139 tx-fifo-depth = <0x40>; 140 rx-fifo-depth = <0x40>; 141 phandle = <0x1d>; 142 }; 143 144 gpio@e000a000 { 145 compatible = "xlnx,zynq-gpio-1.0"; 146 #gpio-cells = <0x02>; 147 clocks = <0x02 0x2a>; 148 gpio-controller; 149 interrupt-controller; 150 #interrupt-cells = <0x02>; 151 interrupt-parent = <0x01>; 152 interrupts = <0x00 0x14 0x04>; 153 reg = <0xe000a000 0x1000>; 154 phandle = <0x09>; 155 }; 156 157 i2c@e0004000 { 158 compatible = "cdns,i2c-r1p10"; 159 status = "disabled"; 160 clocks = <0x02 0x26>; 161 interrupt-parent = <0x01>; 162 interrupts = <0x00 0x19 0x04>; 163 reg = <0xe0004000 0x1000>; 164 #address-cells = <0x01>; 165 #size-cells = <0x00>; 166 phandle = <0x1e>; 167 }; 168 169 i2c@e0005000 { 170 compatible = "cdns,i2c-r1p10"; 171 status = "disabled"; 172 clocks = <0x02 0x27>; 173 interrupt-parent = <0x01>; 174 interrupts = <0x00 0x30 0x04>; 175 reg = <0xe0005000 0x1000>; 176 #address-cells = <0x01>; 177 #size-cells = <0x00>; 178 phandle = <0x1f>; 179 }; 180 181 interrupt-controller@f8f01000 { 182 compatible = "arm,cortex-a9-gic"; 183 #interrupt-cells = <0x03>; 184 interrupt-controller; 185 reg = <0xf8f01000 0x1000 0xf8f00100 0x100>; 186 phandle = <0x01>; 187 }; 188 189 cache-controller@f8f02000 { 190 compatible = "arm,pl310-cache"; 191 reg = <0xf8f02000 0x1000>; 192 interrupts = <0x00 0x02 0x04>; 193 arm,data-latency = <0x03 0x02 0x02>; 194 arm,tag-latency = <0x02 0x02 0x02>; 195 cache-unified; 196 cache-level = <0x02>; 197 phandle = <0x20>; 198 }; 199 200 memory-controller@f8006000 { 201 compatible = "xlnx,zynq-ddrc-a05"; 202 reg = <0xf8006000 0x1000>; 203 phandle = <0x21>; 204 }; 205 206 ocmc@f800c000 { 207 compatible = "xlnx,zynq-ocmc-1.0"; 208 interrupt-parent = <0x01>; 209 interrupts = <0x00 0x03 0x04>; 210 reg = <0xf800c000 0x1000>; 211 phandle = <0x22>; 212 }; 213 214 serial@e0000000 { 215 compatible = "xlnx,xuartps\0cdns,uart-r1p8"; 216 status = "disabled"; 217 clocks = <0x02 0x17 0x02 0x28>; 218 clock-names = "uart_clk\0pclk"; 219 reg = <0xe0000000 0x1000>; 220 interrupts = <0x00 0x1b 0x04>; 221 phandle = <0x23>; 222 }; 223 224 serial@e0001000 { 225 compatible = "xlnx,xuartps\0cdns,uart-r1p8"; 226 status = "okay"; 227 clocks = <0x02 0x18 0x02 0x29>; 228 clock-names = "uart_clk\0pclk"; 229 reg = <0xe0001000 0x1000>; 230 interrupts = <0x00 0x32 0x04>; 231 phandle = <0x24>; 232 }; 233 234 spi@e0006000 { 235 compatible = "xlnx,zynq-spi-r1p6"; 236 reg = <0xe0006000 0x1000>; 237 status = "okay"; 238 interrupt-parent = <0x01>; 239 interrupts = <0x00 0x1a 0x04>; 240 clocks = <0x02 0x19 0x02 0x22>; 241 clock-names = "ref_clk\0pclk"; 242 #address-cells = <0x01>; 243 #size-cells = <0x00>; 244 phandle = <0x25>; 245 246 ad9361-phy@0 { 247 #address-cells = <0x1>; 248 #size-cells = <0x0>; 249 #clock-cells = <0x1>; 250 compatible = "adi,ad9361"; 251 reg = <0x0>; 252 spi-cpha; 253 spi-max-frequency = <0x989680>; 254 clocks = <0x08 0x00>; 255 clock-names = "ad9361_ext_refclk"; 256 clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; 257 adi,digital-interface-tune-skip-mode = <0x0>; 258 adi,pp-tx-swap-enable; 259 adi,pp-rx-swap-enable; 260 adi,rx-frame-pulse-mode-enable; 261 adi,lvds-mode-enable; 262 adi,lvds-bias-mV = <0x96>; 263 adi,lvds-rx-onchip-termination-enable; 264 adi,rx-data-delay = <0x4>; 265 adi,tx-fb-clock-delay = <0x7>; 266 adi,xo-disable-use-ext-refclk-enable; 267 adi,2rx-2tx-mode-enable; 268 adi,frequency-division-duplex-mode-enable; 269 adi,rx-rf-port-input-select = <0x0>; 270 adi,tx-rf-port-input-select = <0x0>; 271 adi,tx-attenuation-mdB = <0x2710>; 272 adi,tx-lo-powerdown-managed-enable; 273 adi,rf-rx-bandwidth-hz = <0x112a880>; 274 adi,rf-tx-bandwidth-hz = <0x112a880>; 275 adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>; 276 adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>; 277 adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 278 adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 279 adi,gc-rx1-mode = <0x2>; 280 adi,gc-rx2-mode = <0x2>; 281 adi,gc-adc-ovr-sample-size = <0x4>; 282 adi,gc-adc-small-overload-thresh = <0x2f>; 283 adi,gc-adc-large-overload-thresh = <0x3a>; 284 adi,gc-lmt-overload-high-thresh = <0x320>; 285 adi,gc-lmt-overload-low-thresh = <0x2c0>; 286 adi,gc-dec-pow-measurement-duration = <0x2000>; 287 adi,gc-low-power-thresh = <0x18>; 288 adi,mgc-inc-gain-step = <0x2>; 289 adi,mgc-dec-gain-step = <0x2>; 290 adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>; 291 adi,agc-attack-delay-extra-margin-us = <0x1>; 292 adi,agc-outer-thresh-high = <0x5>; 293 adi,agc-outer-thresh-high-dec-steps = <0x2>; 294 adi,agc-inner-thresh-high = <0xa>; 295 adi,agc-inner-thresh-high-dec-steps = <0x1>; 296 adi,agc-inner-thresh-low = <0xc>; 297 adi,agc-inner-thresh-low-inc-steps = <0x1>; 298 adi,agc-outer-thresh-low = <0x12>; 299 adi,agc-outer-thresh-low-inc-steps = <0x2>; 300 adi,agc-adc-small-overload-exceed-counter = <0xa>; 301 adi,agc-adc-large-overload-exceed-counter = <0xa>; 302 adi,agc-adc-large-overload-inc-steps = <0x2>; 303 adi,agc-lmt-overload-large-exceed-counter = <0xa>; 304 adi,agc-lmt-overload-small-exceed-counter = <0xa>; 305 adi,agc-lmt-overload-large-inc-steps = <0x2>; 306 adi,agc-gain-update-interval-us = <0x3e8>; 307 adi,fagc-dec-pow-measurement-duration = <0x40>; 308 adi,fagc-lp-thresh-increment-steps = <0x1>; 309 adi,fagc-lp-thresh-increment-time = <0x5>; 310 adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>; 311 adi,fagc-final-overrange-count = <0x3>; 312 adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>; 313 adi,fagc-lmt-final-settling-steps = <0x1>; 314 adi,fagc-lock-level = <0xa>; 315 adi,fagc-lock-level-gain-increase-upper-limit = <0x5>; 316 adi,fagc-lock-level-lmt-gain-increase-enable; 317 adi,fagc-lpf-final-settling-steps = <0x1>; 318 adi,fagc-optimized-gain-offset = <0x5>; 319 adi,fagc-power-measurement-duration-in-state5 = <0x40>; 320 adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable; 321 adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>; 322 adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable; 323 adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>; 324 adi,fagc-rst-gla-large-adc-overload-enable; 325 adi,fagc-rst-gla-large-lmt-overload-enable; 326 adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>; 327 adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable; 328 adi,fagc-state-wait-time-ns = <0x104>; 329 adi,fagc-use-last-lock-level-for-set-gain-enable; 330 adi,rssi-restart-mode = <0x3>; 331 adi,rssi-delay = <0x1>; 332 adi,rssi-wait = <0x1>; 333 adi,rssi-duration = <0x3e8>; 334 adi,ctrl-outs-index = <0x0>; 335 adi,ctrl-outs-enable-mask = <0xff>; 336 adi,temp-sense-measurement-interval-ms = <0x3e8>; 337 adi,temp-sense-offset-signed = <0xce>; 338 adi,temp-sense-periodic-measurement-enable; 339 adi,aux-dac-manual-mode-enable; 340 adi,aux-dac1-default-value-mV = <0x0>; 341 adi,aux-dac1-rx-delay-us = <0x0>; 342 adi,aux-dac1-tx-delay-us = <0x0>; 343 adi,aux-dac2-default-value-mV = <0x0>; 344 adi,aux-dac2-rx-delay-us = <0x0>; 345 adi,aux-dac2-tx-delay-us = <0x0>; 346 en_agc-gpios = <0x09 0x62 0x0>; 347 sync-gpios = <0x09 0x63 0x0>; 348 reset-gpios = <0x09 0x64 0x0>; 349 enable-gpios = <0x09 0x65 0x0>; 350 txnrx-gpios = <0x09 0x66 0x0>; 351 phandle = <0x17>; 352 }; 353 }; 354 355 spi@e0007000 { 356 compatible = "xlnx,zynq-spi-r1p6"; 357 reg = <0xe0007000 0x1000>; 358 status = "disabled"; 359 interrupt-parent = <0x01>; 360 interrupts = <0x00 0x31 0x04>; 361 clocks = <0x02 0x1a 0x02 0x23>; 362 clock-names = "ref_clk\0pclk"; 363 #address-cells = <0x01>; 364 #size-cells = <0x00>; 365 phandle = <0x26>; 366 }; 367 368 spi@e000d000 { 369 clock-names = "ref_clk\0pclk"; 370 clocks = <0x02 0x0a 0x02 0x2b>; 371 compatible = "xlnx,zynq-qspi-1.0"; 372 status = "okay"; 373 interrupt-parent = <0x01>; 374 interrupts = <0x00 0x13 0x04>; 375 reg = <0xe000d000 0x1000>; 376 #address-cells = <0x01>; 377 #size-cells = <0x00>; 378 is-dual = <0x00>; 379 num-cs = <0x01>; 380 phandle = <0x27>; 381 382 ps7-qspi@0 { 383 #address-cells = <0x01>; 384 #size-cells = <0x01>; 385 spi-tx-bus-width = <0x01>; 386 spi-rx-bus-width = <0x04>; 387 compatible = "n25q256a\0jedec,spi-nor"; 388 reg = <0x00>; 389 spi-max-frequency = <0x2faf080>; 390 phandle = <0x28>; 391 392 partition@qspi-fsbl-uboot { 393 label = "qspi-fsbl-uboot"; 394 reg = <0x00 0xe0000>; 395 }; 396 397 partition@qspi-uboot-env { 398 label = "qspi-uboot-env"; 399 reg = <0xe0000 0x20000>; 400 }; 401 402 partition@qspi-linux { 403 label = "qspi-linux"; 404 reg = <0x100000 0x500000>; 405 }; 406 407 partition@qspi-device-tree { 408 label = "qspi-device-tree"; 409 reg = <0x600000 0x20000>; 410 }; 411 412 partition@qspi-rootfs { 413 label = "qspi-rootfs"; 414 reg = <0x620000 0xce0000>; 415 }; 416 417 partition@qspi-bitstream { 418 label = "qspi-bitstream"; 419 reg = <0x1300000 0xd00000>; 420 }; 421 }; 422 }; 423 424 memory-controller@e000e000 { 425 #address-cells = <0x01>; 426 #size-cells = <0x01>; 427 status = "disabled"; 428 clock-names = "memclk\0apb_pclk"; 429 clocks = <0x02 0x0b 0x02 0x2c>; 430 compatible = "arm,pl353-smc-r2p1\0arm,primecell"; 431 interrupt-parent = <0x01>; 432 interrupts = <0x00 0x12 0x04>; 433 ranges; 434 reg = <0xe000e000 0x1000>; 435 phandle = <0x29>; 436 437 flash@e1000000 { 438 status = "disabled"; 439 compatible = "arm,pl353-nand-r2p1"; 440 reg = <0xe1000000 0x1000000>; 441 #address-cells = <0x01>; 442 #size-cells = <0x01>; 443 phandle = <0x2a>; 444 }; 445 446 flash@e2000000 { 447 status = "disabled"; 448 compatible = "cfi-flash"; 449 reg = <0xe2000000 0x2000000>; 450 #address-cells = <0x01>; 451 #size-cells = <0x01>; 452 phandle = <0x2b>; 453 }; 454 }; 455 456 ethernet@e000b000 { 457 compatible = "cdns,zynq-gem\0cdns,gem"; 458 reg = <0xe000b000 0x1000>; 459 status = "okay"; 460 interrupts = <0x00 0x16 0x04>; 461 clocks = <0x02 0x1e 0x02 0x1e 0x02 0x0d>; 462 clock-names = "pclk\0hclk\0tx_clk"; 463 #address-cells = <0x01>; 464 #size-cells = <0x00>; 465 phy-handle = <0x0a>; 466 phy-mode = "rgmii-id"; 467 phandle = <0x2c>; 468 469 phy@0 { 470 device_type = "ethernet-phy"; 471 reg = <0x00>; 472 marvell,reg-init = <0x03 0x10 0xff00 0x1e 0x03 0x11 0xfff0 0x00>; 473 phandle = <0x0a>; 474 }; 475 }; 476 477 ethernet@e000c000 { 478 compatible = "cdns,zynq-gem\0cdns,gem"; 479 reg = <0xe000c000 0x1000>; 480 status = "disabled"; 481 interrupts = <0x00 0x2d 0x04>; 482 clocks = <0x02 0x1f 0x02 0x1f 0x02 0x0e>; 483 clock-names = "pclk\0hclk\0tx_clk"; 484 #address-cells = <0x01>; 485 #size-cells = <0x00>; 486 phandle = <0x2d>; 487 }; 488 489 mmc@e0100000 { 490 compatible = "arasan,sdhci-8.9a"; 491 status = "okay"; 492 clock-names = "clk_xin\0clk_ahb"; 493 clocks = <0x02 0x15 0x02 0x20>; 494 interrupt-parent = <0x01>; 495 interrupts = <0x00 0x18 0x04>; 496 reg = <0xe0100000 0x1000>; 497 disable-wp; 498 phandle = <0x2e>; 499 }; 500 501 mmc@e0101000 { 502 compatible = "arasan,sdhci-8.9a"; 503 status = "disabled"; 504 clock-names = "clk_xin\0clk_ahb"; 505 clocks = <0x02 0x16 0x02 0x21>; 506 interrupt-parent = <0x01>; 507 interrupts = <0x00 0x2f 0x04>; 508 reg = <0xe0101000 0x1000>; 509 phandle = <0x2f>; 510 }; 511 512 slcr@f8000000 { 513 u-boot,dm-pre-reloc; 514 #address-cells = <0x01>; 515 #size-cells = <0x01>; 516 compatible = "xlnx,zynq-slcr\0syscon\0simple-mfd"; 517 reg = <0xf8000000 0x1000>; 518 ranges; 519 phandle = <0x0b>; 520 521 clkc@100 { 522 u-boot,dm-pre-reloc; 523 #clock-cells = <0x01>; 524 compatible = "xlnx,ps7-clkc"; 525 fclk-enable = <0x0f>; 526 clock-output-names = "armpll\0ddrpll\0iopll\0cpu_6or4x\0cpu_3or2x\0cpu_2x\0cpu_1x\0ddr2x\0ddr3x\0dci\0lqspi\0smc\0pcap\0gem0\0gem1\0fclk0\0fclk1\0fclk2\0fclk3\0can0\0can1\0sdio0\0sdio1\0uart0\0uart1\0spi0\0spi1\0dma\0usb0_aper\0usb1_aper\0gem0_aper\0gem1_aper\0sdio0_aper\0sdio1_aper\0spi0_aper\0spi1_aper\0can0_aper\0can1_aper\0i2c0_aper\0i2c1_aper\0uart0_aper\0uart1_aper\0gpio_aper\0lqspi_aper\0smc_aper\0swdt\0dbg_trc\0dbg_apb"; 527 reg = <0x100 0x100>; 528 ps-clk-frequency = <0x1fca055>; 529 phandle = <0x02>; 530 }; 531 532 rstc@200 { 533 compatible = "xlnx,zynq-reset"; 534 reg = <0x200 0x48>; 535 #reset-cells = <0x01>; 536 syscon = <0x0b>; 537 phandle = <0x30>; 538 }; 539 540 pinctrl@700 { 541 compatible = "xlnx,pinctrl-zynq"; 542 reg = <0x700 0x200>; 543 syscon = <0x0b>; 544 phandle = <0x31>; 545 }; 546 }; 547 548 dmac@f8003000 { 549 compatible = "arm,pl330\0arm,primecell"; 550 reg = <0xf8003000 0x1000>; 551 interrupt-parent = <0x01>; 552 interrupt-names = "abort\0dma0\0dma1\0dma2\0dma3\0dma4\0dma5\0dma6\0dma7"; 553 interrupts = <0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04>; 554 #dma-cells = <0x01>; 555 #dma-channels = <0x08>; 556 #dma-requests = <0x04>; 557 clocks = <0x02 0x1b>; 558 clock-names = "apb_pclk"; 559 phandle = <0x32>; 560 }; 561 562 devcfg@f8007000 { 563 compatible = "xlnx,zynq-devcfg-1.0"; 564 interrupt-parent = <0x01>; 565 interrupts = <0x00 0x08 0x04>; 566 reg = <0xf8007000 0x100>; 567 clocks = <0x02 0x0c 0x02 0x0f 0x02 0x10 0x02 0x11 0x02 0x12>; 568 clock-names = "ref_clk\0fclk0\0fclk1\0fclk2\0fclk3"; 569 syscon = <0x0b>; 570 phandle = <0x04>; 571 }; 572 573 efuse@f800d000 { 574 compatible = "xlnx,zynq-efuse"; 575 reg = <0xf800d000 0x20>; 576 phandle = <0x33>; 577 }; 578 579 timer@f8f00200 { 580 compatible = "arm,cortex-a9-global-timer"; 581 reg = <0xf8f00200 0x20>; 582 interrupts = <0x01 0x0b 0x301>; 583 interrupt-parent = <0x01>; 584 clocks = <0x02 0x04>; 585 phandle = <0x34>; 586 }; 587 588 timer@f8001000 { 589 interrupt-parent = <0x01>; 590 interrupts = <0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04>; 591 compatible = "cdns,ttc"; 592 clocks = <0x02 0x06>; 593 reg = <0xf8001000 0x1000>; 594 phandle = <0x35>; 595 }; 596 597 timer@f8002000 { 598 interrupt-parent = <0x01>; 599 interrupts = <0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04>; 600 compatible = "cdns,ttc"; 601 clocks = <0x02 0x06>; 602 reg = <0xf8002000 0x1000>; 603 phandle = <0x36>; 604 }; 605 606 timer@f8f00600 { 607 interrupt-parent = <0x01>; 608 interrupts = <0x01 0x0d 0x301>; 609 compatible = "arm,cortex-a9-twd-timer"; 610 reg = <0xf8f00600 0x20>; 611 clocks = <0x02 0x04>; 612 phandle = <0x37>; 613 }; 614 615 usb@e0002000 { 616 compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2"; 617 status = "okay"; 618 clocks = <0x02 0x1c>; 619 interrupt-parent = <0x01>; 620 interrupts = <0x00 0x15 0x04>; 621 reg = <0xe0002000 0x1000>; 622 phy_type = "ulpi"; 623 dr_mode = "host"; 624 xlnx,phy-reset-gpio = <0x09 0x07 0x00>; 625 phandle = <0x38>; 626 }; 627 628 usb@e0003000 { 629 compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2"; 630 status = "disabled"; 631 clocks = <0x02 0x1d>; 632 interrupt-parent = <0x01>; 633 interrupts = <0x00 0x2c 0x04>; 634 reg = <0xe0003000 0x1000>; 635 phy_type = "ulpi"; 636 phandle = <0x39>; 637 }; 638 639 watchdog@f8005000 { 640 clocks = <0x02 0x2d>; 641 compatible = "cdns,wdt-r1p2"; 642 interrupt-parent = <0x01>; 643 interrupts = <0x00 0x09 0x01>; 644 reg = <0xf8005000 0x1000>; 645 timeout-sec = <0x0a>; 646 phandle = <0x3a>; 647 }; 648 649 etb@f8801000 { 650 compatible = "arm,coresight-etb10\0arm,primecell"; 651 reg = <0xf8801000 0x1000>; 652 clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; 653 clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; 654 655 in-ports { 656 657 port { 658 659 endpoint { 660 remote-endpoint = <0x0c>; 661 phandle = <0x06>; 662 }; 663 }; 664 }; 665 }; 666 667 tpiu@f8803000 { 668 compatible = "arm,coresight-tpiu\0arm,primecell"; 669 reg = <0xf8803000 0x1000>; 670 clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; 671 clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; 672 673 in-ports { 674 675 port { 676 677 endpoint { 678 remote-endpoint = <0x0d>; 679 phandle = <0x05>; 680 }; 681 }; 682 }; 683 }; 684 685 funnel@f8804000 { 686 compatible = "arm,coresight-static-funnel\0arm,primecell"; 687 reg = <0xf8804000 0x1000>; 688 clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; 689 clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; 690 691 out-ports { 692 693 port { 694 695 endpoint { 696 remote-endpoint = <0x0e>; 697 phandle = <0x07>; 698 }; 699 }; 700 }; 701 702 in-ports { 703 #address-cells = <0x01>; 704 #size-cells = <0x00>; 705 706 port@0 { 707 reg = <0x00>; 708 709 endpoint { 710 remote-endpoint = <0x0f>; 711 phandle = <0x12>; 712 }; 713 }; 714 715 port@1 { 716 reg = <0x01>; 717 718 endpoint { 719 remote-endpoint = <0x10>; 720 phandle = <0x14>; 721 }; 722 }; 723 724 port@2 { 725 reg = <0x02>; 726 727 endpoint { 728 phandle = <0x3b>; 729 }; 730 }; 731 }; 732 }; 733 734 ptm@f889c000 { 735 compatible = "arm,coresight-etm3x\0arm,primecell"; 736 reg = <0xf889c000 0x1000>; 737 clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; 738 clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; 739 cpu = <0x11>; 740 741 out-ports { 742 743 port { 744 745 endpoint { 746 remote-endpoint = <0x12>; 747 phandle = <0x0f>; 748 }; 749 }; 750 }; 751 }; 752 753 ptm@f889d000 { 754 compatible = "arm,coresight-etm3x\0arm,primecell"; 755 reg = <0xf889d000 0x1000>; 756 clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; 757 clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; 758 cpu = <0x13>; 759 760 out-ports { 761 762 port { 763 764 endpoint { 765 remote-endpoint = <0x14>; 766 phandle = <0x10>; 767 }; 768 }; 769 }; 770 }; 771 }; 772 773 aliases { 774 ethernet0 = "/axi/ethernet@e000b000"; 775 serial0 = "/axi/serial@e0001000"; 776 phandle = <0x3c>; 777 }; 778 779 memory { 780 device_type = "memory"; 781 reg = <0x00 0x20000000>; 782 }; 783 784 chosen { 785 stdout-path = "/amba@0/uart@E0001000"; 786 }; 787 788 clocks { 789 790 clock@0 { 791 #clock-cells = <0x00>; 792 compatible = "adjustable-clock"; 793 clock-frequency = <0x2625a00>; 794 clock-accuracy = <0x30d40>; 795 clock-output-names = "ad9364_ext_refclk"; 796 phandle = <0x08>; 797 }; 798 799 clock@1 { 800 #clock-cells = <0x00>; 801 compatible = "fixed-clock"; 802 clock-frequency = <0x16e3600>; 803 clock-output-names = "24MHz"; 804 phandle = <0x15>; 805 }; 806 }; 807 808 usb-ulpi-gpio-gate@0 { 809 compatible = "gpio-gate-clock"; 810 clocks = <0x15>; 811 #clock-cells = <0x00>; 812 enable-gpios = <0x09 0x09 0x01>; 813 phandle = <0x3d>; 814 }; 815 816 fpga-axi@0 { 817 compatible = "simple-bus"; 818 #address-cells = <0x01>; 819 #size-cells = <0x01>; 820 ranges; 821 phandle = <0x3e>; 822 823 i2c@41600000 { 824 compatible = "xlnx,axi-iic-1.02.a\0xlnx,xps-iic-2.00.a"; 825 reg = <0x41600000 0x10000>; 826 interrupt-parent = <0x01>; 827 interrupts = <0x00 0x3a 0x04>; 828 clocks = <0x02 0x0f>; 829 clock-names = "pclk"; 830 #address-cells = <0x01>; 831 #size-cells = <0x00>; 832 phandle = <0x3f>; 833 834 ad7291@20 { 835 compatible = "adi,ad7291"; 836 reg = <0x20>; 837 }; 838 839 ad7291-bob@2C { 840 compatible = "adi,ad7291"; 841 reg = <0x2c>; 842 }; 843 844 eeprom@50 { 845 compatible = "at24,24c32"; 846 reg = <0x50>; 847 }; 848 }; 849 850 // dma@7c400000 { 851 // compatible = "adi,axi-dmac-1.00.a"; 852 // reg = <0x7c400000 0x10000>; 853 // #dma-cells = <0x01>; 854 // interrupts = <0x00 0x39 0x04>; 855 // clocks = <0x02 0x10>; 856 // phandle = <0x16>; 857 858 // adi,channels { 859 // #size-cells = <0x00>; 860 // #address-cells = <0x01>; 861 862 // dma-channel@0 { 863 // reg = <0x00>; 864 // adi,source-bus-width = <0x40>; 865 // adi,source-bus-type = <0x02>; 866 // adi,destination-bus-width = <0x40>; 867 // adi,destination-bus-type = <0x00>; 868 // }; 869 // }; 870 // }; 871 872 // dma@7c420000 { 873 // compatible = "adi,axi-dmac-1.00.a"; 874 // reg = <0x7c420000 0x10000>; 875 // #dma-cells = <0x01>; 876 // interrupts = <0x00 0x38 0x04>; 877 // clocks = <0x02 0x10>; 878 // phandle = <0x18>; 879 880 // adi,channels { 881 // #size-cells = <0x00>; 882 // #address-cells = <0x01>; 883 884 // dma-channel@0 { 885 // reg = <0x00>; 886 // adi,source-bus-width = <0x40>; 887 // adi,source-bus-type = <0x00>; 888 // adi,destination-bus-width = <0x40>; 889 // adi,destination-bus-type = <0x02>; 890 // }; 891 // }; 892 // }; 893 894 sdr: sdr { 895 compatible ="sdr,sdr"; 896 dmas = <&rx_dma 1 897 &tx_dma 0>; 898 dma-names = "rx_dma_s2mm", "tx_dma_mm2s"; 899 interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt"; 900 interrupt-parent = <1>; 901 interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>; 902 } ; 903 904 // axidmatest_1: axidmatest@1 { 905 // compatible ="xlnx,axi-dma-test-1.00.a"; 906 // dmas = <&rx_dma 0 907 // &rx_dma 1>; 908 // dma-names = "axidma0", "axidma1"; 909 // } ; 910 911 tx_dma: dma@80400000 { 912 #dma-cells = <1>; 913 clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; 914 clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 915 compatible = "xlnx,axi-dma-1.00.a"; 916 interrupt-names = "mm2s_introut", "s2mm_introut"; 917 interrupt-parent = <1>; 918 interrupts = <0 35 4 0 36 4>; 919 reg = <0x80400000 0x10000>; 920 xlnx,addrwidth = <0x20>; 921 xlnx,include-sg ; 922 xlnx,sg-length-width = <0xe>; 923 dma-channel@80400000 { 924 compatible = "xlnx,axi-dma-mm2s-channel"; 925 dma-channels = <0x1>; 926 interrupts = <0 35 4>; 927 xlnx,datawidth = <0x40>; 928 xlnx,device-id = <0x0>; 929 }; 930 dma-channel@80400030 { 931 compatible = "xlnx,axi-dma-s2mm-channel"; 932 dma-channels = <0x1>; 933 interrupts = <0 36 4>; 934 xlnx,datawidth = <0x40>; 935 xlnx,device-id = <0x0>; 936 }; 937 }; 938 939 rx_dma: dma@80410000 { 940 #dma-cells = <1>; 941 clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; 942 clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 943 compatible = "xlnx,axi-dma-1.00.a"; 944 //dma-coherent ; 945 interrupt-names = "mm2s_introut", "s2mm_introut"; 946 interrupt-parent = <1>; 947 interrupts = <0 31 4 0 32 4>; 948 reg = <0x80410000 0x10000>; 949 xlnx,addrwidth = <0x20>; 950 xlnx,include-sg ; 951 xlnx,sg-length-width = <0xe>; 952 dma-channel@80410000 { 953 compatible = "xlnx,axi-dma-mm2s-channel"; 954 dma-channels = <0x1>; 955 interrupts = <0 31 4>; 956 xlnx,datawidth = <0x40>; 957 xlnx,device-id = <0x1>; 958 }; 959 dma-channel@80410030 { 960 compatible = "xlnx,axi-dma-s2mm-channel"; 961 dma-channels = <0x1>; 962 interrupts = <0 32 4>; 963 xlnx,datawidth = <0x40>; 964 xlnx,device-id = <0x1>; 965 }; 966 }; 967 968 tx_intf_0: tx_intf@83c00000 { 969 clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk"; 970 clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>; 971 compatible = "sdr,tx_intf"; 972 interrupt-names = "tx_itrpt"; 973 interrupt-parent = <1>; 974 interrupts = <0 34 1>; 975 reg = <0x83c00000 0x10000>; 976 xlnx,s00-axi-addr-width = <0x7>; 977 xlnx,s00-axi-data-width = <0x20>; 978 }; 979 980 rx_intf_0: rx_intf@83c20000 { 981 clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk"; 982 clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>; 983 compatible = "sdr,rx_intf"; 984 interrupt-names = "not_valid_anymore", "rx_pkt_intr"; 985 interrupt-parent = <1>; 986 interrupts = <0 29 1 0 30 1>; 987 reg = <0x83c20000 0x10000>; 988 xlnx,s00-axi-addr-width = <0x7>; 989 xlnx,s00-axi-data-width = <0x20>; 990 }; 991 992 openofdm_tx_0: openofdm_tx@83c10000 { 993 clock-names = "clk"; 994 clocks = <0x2 0x11>; 995 compatible = "sdr,openofdm_tx"; 996 reg = <0x83c10000 0x10000>; 997 }; 998 999 openofdm_rx_0: openofdm_rx@83c30000 { 1000 clock-names = "clk"; 1001 clocks = <0x2 0x11>; 1002 compatible = "sdr,openofdm_rx"; 1003 reg = <0x83c30000 0x10000>; 1004 }; 1005 1006 xpu_0: xpu@83c40000 { 1007 clock-names = "s00_axi_aclk"; 1008 clocks = <0x2 0x11>; 1009 compatible = "sdr,xpu"; 1010 reg = <0x83c40000 0x10000>; 1011 }; 1012 1013 side_ch_0: side_ch@83c50000 { 1014 clock-names = "s00_axi_aclk"; 1015 clocks = <0x2 0x11>; 1016 compatible = "sdr,side_ch"; 1017 reg = <0x83c50000 0x10000>; 1018 dmas = <&rx_dma 0 1019 &tx_dma 1>; 1020 dma-names = "rx_dma_mm2s", "tx_dma_s2mm"; 1021 }; 1022 1023 cf-ad9361-lpc@79020000 { 1024 compatible = "adi,axi-ad9361-6.00.a"; 1025 reg = <0x79020000 0x6000>; 1026 // dmas = <0x16 0x00>; 1027 // dma-names = "rx"; 1028 spibus-connected = <0x17>; 1029 phandle = <0x40>; 1030 }; 1031 1032 cf-ad9361-dds-core-lpc@79024000 { 1033 compatible = "adi,axi-ad9361-dds-6.00.a"; 1034 reg = <0x79024000 0x1000>; 1035 clocks = <0x17 0x0d>; 1036 clock-names = "sampl_clk"; 1037 // dmas = <0x18 0x00>; 1038 // dma-names = "tx"; 1039 phandle = <0x41>; 1040 }; 1041 1042 mwipcore@43c00000 { 1043 compatible = "mathworks,mwipcore-axi4lite-v1.00"; 1044 reg = <0x43c00000 0xffff>; 1045 }; 1046 1047 // axi-sysid-0@45000000 { 1048 // compatible = "adi,axi-sysid-1.00.a"; 1049 // reg = <0x45000000 0x10000>; 1050 // phandle = <0x42>; 1051 // }; 1052 }; 1053 1054 leds { 1055 compatible = "gpio-leds"; 1056 1057 led0 { 1058 label = "led0:green"; 1059 gpios = <0x09 0x3a 0x00>; 1060 }; 1061 1062 led1 { 1063 label = "led1:green"; 1064 gpios = <0x09 0x3b 0x00>; 1065 }; 1066 1067 led2 { 1068 label = "led2:green"; 1069 gpios = <0x09 0x3c 0x00>; 1070 }; 1071 1072 led3 { 1073 label = "led3:green"; 1074 gpios = <0x09 0x3d 0x00>; 1075 }; 1076 }; 1077 1078 gpio_keys { 1079 compatible = "gpio-keys"; 1080 #address-cells = <0x01>; 1081 #size-cells = <0x00>; 1082 autorepeat; 1083 1084 pb0 { 1085 label = "Left"; 1086 linux,code = <0x69>; 1087 gpios = <0x09 0x36 0x00>; 1088 }; 1089 1090 pb1 { 1091 label = "Right"; 1092 linux,code = <0x6a>; 1093 gpios = <0x09 0x37 0x00>; 1094 }; 1095 1096 pb2 { 1097 label = "Up"; 1098 linux,code = <0x67>; 1099 gpios = <0x09 0x38 0x00>; 1100 }; 1101 1102 pb3 { 1103 label = "Down"; 1104 linux,code = <0x6c>; 1105 gpios = <0x09 0x39 0x00>; 1106 }; 1107 1108 sw0 { 1109 label = "SW0"; 1110 linux,input-type = <0x05>; 1111 linux,code = <0x0d>; 1112 gpios = <0x09 0x3e 0x00>; 1113 }; 1114 1115 sw1 { 1116 label = "SW1"; 1117 linux,input-type = <0x05>; 1118 linux,code = <0x01>; 1119 gpios = <0x09 0x3f 0x00>; 1120 }; 1121 1122 sw2 { 1123 label = "SW2"; 1124 linux,input-type = <0x05>; 1125 linux,code = <0x02>; 1126 gpios = <0x09 0x40 0x00>; 1127 }; 1128 1129 sw3 { 1130 label = "SW3"; 1131 linux,input-type = <0x05>; 1132 linux,code = <0x03>; 1133 gpios = <0x09 0x41 0x00>; 1134 }; 1135 }; 1136}; 1137