1*0410b1afSXianjun Jiao/dts-v1/; 2*0410b1afSXianjun Jiao 3*0410b1afSXianjun Jiao/ { 4*0410b1afSXianjun Jiao #address-cells = <0x01>; 5*0410b1afSXianjun Jiao #size-cells = <0x01>; 6*0410b1afSXianjun Jiao compatible = "xlnx,zynq-7000"; 7*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 8*0410b1afSXianjun Jiao model = "Analog Devices ADRV9364-Z7020 (Z7020/AD9364)"; 9*0410b1afSXianjun Jiao 10*0410b1afSXianjun Jiao cpus { 11*0410b1afSXianjun Jiao #address-cells = <0x01>; 12*0410b1afSXianjun Jiao #size-cells = <0x00>; 13*0410b1afSXianjun Jiao 14*0410b1afSXianjun Jiao cpu@0 { 15*0410b1afSXianjun Jiao compatible = "arm,cortex-a9"; 16*0410b1afSXianjun Jiao device_type = "cpu"; 17*0410b1afSXianjun Jiao reg = <0x00>; 18*0410b1afSXianjun Jiao clocks = <0x02 0x03>; 19*0410b1afSXianjun Jiao clock-latency = <0x3e8>; 20*0410b1afSXianjun Jiao cpu0-supply = <0x03>; 21*0410b1afSXianjun Jiao operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>; 22*0410b1afSXianjun Jiao }; 23*0410b1afSXianjun Jiao 24*0410b1afSXianjun Jiao cpu@1 { 25*0410b1afSXianjun Jiao compatible = "arm,cortex-a9"; 26*0410b1afSXianjun Jiao device_type = "cpu"; 27*0410b1afSXianjun Jiao reg = <0x01>; 28*0410b1afSXianjun Jiao clocks = <0x02 0x03>; 29*0410b1afSXianjun Jiao }; 30*0410b1afSXianjun Jiao }; 31*0410b1afSXianjun Jiao 32*0410b1afSXianjun Jiao fpga-full { 33*0410b1afSXianjun Jiao compatible = "fpga-region"; 34*0410b1afSXianjun Jiao fpga-mgr = <0x04>; 35*0410b1afSXianjun Jiao #address-cells = <0x01>; 36*0410b1afSXianjun Jiao #size-cells = <0x01>; 37*0410b1afSXianjun Jiao ranges; 38*0410b1afSXianjun Jiao }; 39*0410b1afSXianjun Jiao 40*0410b1afSXianjun Jiao pmu@f8891000 { 41*0410b1afSXianjun Jiao compatible = "arm,cortex-a9-pmu"; 42*0410b1afSXianjun Jiao interrupts = <0x00 0x05 0x04 0x00 0x06 0x04>; 43*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 44*0410b1afSXianjun Jiao reg = <0xf8891000 0x1000 0xf8893000 0x1000>; 45*0410b1afSXianjun Jiao }; 46*0410b1afSXianjun Jiao 47*0410b1afSXianjun Jiao fixedregulator { 48*0410b1afSXianjun Jiao compatible = "regulator-fixed"; 49*0410b1afSXianjun Jiao regulator-name = "VCCPINT"; 50*0410b1afSXianjun Jiao regulator-min-microvolt = <0xf4240>; 51*0410b1afSXianjun Jiao regulator-max-microvolt = <0xf4240>; 52*0410b1afSXianjun Jiao regulator-boot-on; 53*0410b1afSXianjun Jiao regulator-always-on; 54*0410b1afSXianjun Jiao linux,phandle = <0x03>; 55*0410b1afSXianjun Jiao phandle = <0x03>; 56*0410b1afSXianjun Jiao }; 57*0410b1afSXianjun Jiao 58*0410b1afSXianjun Jiao amba { 59*0410b1afSXianjun Jiao u-boot,dm-pre-reloc; 60*0410b1afSXianjun Jiao compatible = "simple-bus"; 61*0410b1afSXianjun Jiao #address-cells = <0x01>; 62*0410b1afSXianjun Jiao #size-cells = <0x01>; 63*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 64*0410b1afSXianjun Jiao ranges; 65*0410b1afSXianjun Jiao 66*0410b1afSXianjun Jiao adc@f8007100 { 67*0410b1afSXianjun Jiao compatible = "xlnx,zynq-xadc-1.00.a"; 68*0410b1afSXianjun Jiao reg = <0xf8007100 0x20>; 69*0410b1afSXianjun Jiao interrupts = <0x00 0x07 0x04>; 70*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 71*0410b1afSXianjun Jiao clocks = <0x02 0x0c>; 72*0410b1afSXianjun Jiao }; 73*0410b1afSXianjun Jiao 74*0410b1afSXianjun Jiao can@e0008000 { 75*0410b1afSXianjun Jiao compatible = "xlnx,zynq-can-1.0"; 76*0410b1afSXianjun Jiao status = "disabled"; 77*0410b1afSXianjun Jiao clocks = <0x02 0x13 0x02 0x24>; 78*0410b1afSXianjun Jiao clock-names = "can_clk\0pclk"; 79*0410b1afSXianjun Jiao reg = <0xe0008000 0x1000>; 80*0410b1afSXianjun Jiao interrupts = <0x00 0x1c 0x04>; 81*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 82*0410b1afSXianjun Jiao tx-fifo-depth = <0x40>; 83*0410b1afSXianjun Jiao rx-fifo-depth = <0x40>; 84*0410b1afSXianjun Jiao }; 85*0410b1afSXianjun Jiao 86*0410b1afSXianjun Jiao can@e0009000 { 87*0410b1afSXianjun Jiao compatible = "xlnx,zynq-can-1.0"; 88*0410b1afSXianjun Jiao status = "disabled"; 89*0410b1afSXianjun Jiao clocks = <0x02 0x14 0x02 0x25>; 90*0410b1afSXianjun Jiao clock-names = "can_clk\0pclk"; 91*0410b1afSXianjun Jiao reg = <0xe0009000 0x1000>; 92*0410b1afSXianjun Jiao interrupts = <0x00 0x33 0x04>; 93*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 94*0410b1afSXianjun Jiao tx-fifo-depth = <0x40>; 95*0410b1afSXianjun Jiao rx-fifo-depth = <0x40>; 96*0410b1afSXianjun Jiao }; 97*0410b1afSXianjun Jiao 98*0410b1afSXianjun Jiao gpio@e000a000 { 99*0410b1afSXianjun Jiao compatible = "xlnx,zynq-gpio-1.0"; 100*0410b1afSXianjun Jiao #gpio-cells = <0x02>; 101*0410b1afSXianjun Jiao clocks = <0x02 0x2a>; 102*0410b1afSXianjun Jiao gpio-controller; 103*0410b1afSXianjun Jiao interrupt-controller; 104*0410b1afSXianjun Jiao #interrupt-cells = <0x02>; 105*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 106*0410b1afSXianjun Jiao interrupts = <0x00 0x14 0x04>; 107*0410b1afSXianjun Jiao reg = <0xe000a000 0x1000>; 108*0410b1afSXianjun Jiao linux,phandle = <0x06>; 109*0410b1afSXianjun Jiao phandle = <0x06>; 110*0410b1afSXianjun Jiao }; 111*0410b1afSXianjun Jiao 112*0410b1afSXianjun Jiao i2c@e0004000 { 113*0410b1afSXianjun Jiao compatible = "cdns,i2c-r1p10"; 114*0410b1afSXianjun Jiao status = "disabled"; 115*0410b1afSXianjun Jiao clocks = <0x02 0x26>; 116*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 117*0410b1afSXianjun Jiao interrupts = <0x00 0x19 0x04>; 118*0410b1afSXianjun Jiao reg = <0xe0004000 0x1000>; 119*0410b1afSXianjun Jiao #address-cells = <0x01>; 120*0410b1afSXianjun Jiao #size-cells = <0x00>; 121*0410b1afSXianjun Jiao }; 122*0410b1afSXianjun Jiao 123*0410b1afSXianjun Jiao i2c@e0005000 { 124*0410b1afSXianjun Jiao compatible = "cdns,i2c-r1p10"; 125*0410b1afSXianjun Jiao status = "disabled"; 126*0410b1afSXianjun Jiao clocks = <0x02 0x27>; 127*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 128*0410b1afSXianjun Jiao interrupts = <0x00 0x30 0x04>; 129*0410b1afSXianjun Jiao reg = <0xe0005000 0x1000>; 130*0410b1afSXianjun Jiao #address-cells = <0x01>; 131*0410b1afSXianjun Jiao #size-cells = <0x00>; 132*0410b1afSXianjun Jiao }; 133*0410b1afSXianjun Jiao 134*0410b1afSXianjun Jiao interrupt-controller@f8f01000 { 135*0410b1afSXianjun Jiao compatible = "arm,cortex-a9-gic"; 136*0410b1afSXianjun Jiao #interrupt-cells = <0x03>; 137*0410b1afSXianjun Jiao interrupt-controller; 138*0410b1afSXianjun Jiao reg = <0xf8f01000 0x1000 0xf8f00100 0x100>; 139*0410b1afSXianjun Jiao linux,phandle = <0x01>; 140*0410b1afSXianjun Jiao phandle = <0x01>; 141*0410b1afSXianjun Jiao }; 142*0410b1afSXianjun Jiao 143*0410b1afSXianjun Jiao cache-controller@f8f02000 { 144*0410b1afSXianjun Jiao compatible = "arm,pl310-cache"; 145*0410b1afSXianjun Jiao reg = <0xf8f02000 0x1000>; 146*0410b1afSXianjun Jiao interrupts = <0x00 0x02 0x04>; 147*0410b1afSXianjun Jiao arm,data-latency = <0x03 0x02 0x02>; 148*0410b1afSXianjun Jiao arm,tag-latency = <0x02 0x02 0x02>; 149*0410b1afSXianjun Jiao cache-unified; 150*0410b1afSXianjun Jiao cache-level = <0x02>; 151*0410b1afSXianjun Jiao }; 152*0410b1afSXianjun Jiao 153*0410b1afSXianjun Jiao memory-controller@f8006000 { 154*0410b1afSXianjun Jiao compatible = "xlnx,zynq-ddrc-a05"; 155*0410b1afSXianjun Jiao reg = <0xf8006000 0x1000>; 156*0410b1afSXianjun Jiao }; 157*0410b1afSXianjun Jiao 158*0410b1afSXianjun Jiao ocmc@f800c000 { 159*0410b1afSXianjun Jiao compatible = "xlnx,zynq-ocmc-1.0"; 160*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 161*0410b1afSXianjun Jiao interrupts = <0x00 0x03 0x04>; 162*0410b1afSXianjun Jiao reg = <0xf800c000 0x1000>; 163*0410b1afSXianjun Jiao }; 164*0410b1afSXianjun Jiao 165*0410b1afSXianjun Jiao serial@e0000000 { 166*0410b1afSXianjun Jiao compatible = "xlnx,xuartps\0cdns,uart-r1p8"; 167*0410b1afSXianjun Jiao status = "disabled"; 168*0410b1afSXianjun Jiao clocks = <0x02 0x17 0x02 0x28>; 169*0410b1afSXianjun Jiao clock-names = "uart_clk\0pclk"; 170*0410b1afSXianjun Jiao reg = <0xe0000000 0x1000>; 171*0410b1afSXianjun Jiao interrupts = <0x00 0x1b 0x04>; 172*0410b1afSXianjun Jiao }; 173*0410b1afSXianjun Jiao 174*0410b1afSXianjun Jiao serial@e0001000 { 175*0410b1afSXianjun Jiao compatible = "xlnx,xuartps\0cdns,uart-r1p8"; 176*0410b1afSXianjun Jiao status = "okay"; 177*0410b1afSXianjun Jiao clocks = <0x02 0x18 0x02 0x29>; 178*0410b1afSXianjun Jiao clock-names = "uart_clk\0pclk"; 179*0410b1afSXianjun Jiao reg = <0xe0001000 0x1000>; 180*0410b1afSXianjun Jiao interrupts = <0x00 0x32 0x04>; 181*0410b1afSXianjun Jiao }; 182*0410b1afSXianjun Jiao 183*0410b1afSXianjun Jiao spi@e0006000 { 184*0410b1afSXianjun Jiao compatible = "xlnx,zynq-spi-r1p6"; 185*0410b1afSXianjun Jiao reg = <0xe0006000 0x1000>; 186*0410b1afSXianjun Jiao status = "okay"; 187*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 188*0410b1afSXianjun Jiao interrupts = <0x00 0x1a 0x04>; 189*0410b1afSXianjun Jiao clocks = <0x02 0x19 0x02 0x22>; 190*0410b1afSXianjun Jiao clock-names = "ref_clk\0pclk"; 191*0410b1afSXianjun Jiao #address-cells = <0x01>; 192*0410b1afSXianjun Jiao #size-cells = <0x00>; 193*0410b1afSXianjun Jiao 194*0410b1afSXianjun Jiao ad9361-phy@0 { 195*0410b1afSXianjun Jiao #address-cells = <0x01>; 196*0410b1afSXianjun Jiao #size-cells = <0x00>; 197*0410b1afSXianjun Jiao #clock-cells = <0x01>; 198*0410b1afSXianjun Jiao compatible = "adi,ad9361"; 199*0410b1afSXianjun Jiao reg = <0x00>; 200*0410b1afSXianjun Jiao spi-cpha; 201*0410b1afSXianjun Jiao spi-max-frequency = <0x989680>; 202*0410b1afSXianjun Jiao clocks = <0x05 0x00>; 203*0410b1afSXianjun Jiao clock-names = "ad9364_ext_refclk"; 204*0410b1afSXianjun Jiao clock-output-names = "rx_sampl_clk\0tx_sampl_clk"; 205*0410b1afSXianjun Jiao adi,digital-interface-tune-skip-mode = <0x00>; 206*0410b1afSXianjun Jiao adi,pp-tx-swap-enable; 207*0410b1afSXianjun Jiao adi,pp-rx-swap-enable; 208*0410b1afSXianjun Jiao adi,rx-frame-pulse-mode-enable; 209*0410b1afSXianjun Jiao adi,lvds-mode-enable; 210*0410b1afSXianjun Jiao adi,lvds-bias-mV = <0x96>; 211*0410b1afSXianjun Jiao adi,lvds-rx-onchip-termination-enable; 212*0410b1afSXianjun Jiao adi,rx-data-delay = <0x04>; 213*0410b1afSXianjun Jiao adi,tx-fb-clock-delay = <0x07>; 214*0410b1afSXianjun Jiao adi,xo-disable-use-ext-refclk-enable; 215*0410b1afSXianjun Jiao adi,2rx-2tx-mode-enable; 216*0410b1afSXianjun Jiao adi,frequency-division-duplex-mode-enable; 217*0410b1afSXianjun Jiao adi,rx-rf-port-input-select = <0x00>; 218*0410b1afSXianjun Jiao adi,tx-rf-port-input-select = <0x00>; 219*0410b1afSXianjun Jiao adi,tx-attenuation-mdB = <0x2710>; 220*0410b1afSXianjun Jiao adi,tx-lo-powerdown-managed-enable; 221*0410b1afSXianjun Jiao adi,rf-rx-bandwidth-hz = <0x112a880>; 222*0410b1afSXianjun Jiao adi,rf-tx-bandwidth-hz = <0x112a880>; 223*0410b1afSXianjun Jiao adi,rx-synthesizer-frequency-hz = <0x00 0x8f0d1800>; 224*0410b1afSXianjun Jiao adi,tx-synthesizer-frequency-hz = <0x00 0x92080880>; 225*0410b1afSXianjun Jiao adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 226*0410b1afSXianjun Jiao adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 227*0410b1afSXianjun Jiao adi,gc-rx1-mode = <0x02>; 228*0410b1afSXianjun Jiao adi,gc-rx2-mode = <0x02>; 229*0410b1afSXianjun Jiao adi,gc-adc-ovr-sample-size = <0x04>; 230*0410b1afSXianjun Jiao adi,gc-adc-small-overload-thresh = <0x2f>; 231*0410b1afSXianjun Jiao adi,gc-adc-large-overload-thresh = <0x3a>; 232*0410b1afSXianjun Jiao adi,gc-lmt-overload-high-thresh = <0x320>; 233*0410b1afSXianjun Jiao adi,gc-lmt-overload-low-thresh = <0x2c0>; 234*0410b1afSXianjun Jiao adi,gc-dec-pow-measurement-duration = <0x2000>; 235*0410b1afSXianjun Jiao adi,gc-low-power-thresh = <0x18>; 236*0410b1afSXianjun Jiao adi,mgc-inc-gain-step = <0x02>; 237*0410b1afSXianjun Jiao adi,mgc-dec-gain-step = <0x02>; 238*0410b1afSXianjun Jiao adi,mgc-split-table-ctrl-inp-gain-mode = <0x00>; 239*0410b1afSXianjun Jiao adi,agc-attack-delay-extra-margin-us = <0x01>; 240*0410b1afSXianjun Jiao adi,agc-outer-thresh-high = <0x05>; 241*0410b1afSXianjun Jiao adi,agc-outer-thresh-high-dec-steps = <0x02>; 242*0410b1afSXianjun Jiao adi,agc-inner-thresh-high = <0x0a>; 243*0410b1afSXianjun Jiao adi,agc-inner-thresh-high-dec-steps = <0x01>; 244*0410b1afSXianjun Jiao adi,agc-inner-thresh-low = <0x0c>; 245*0410b1afSXianjun Jiao adi,agc-inner-thresh-low-inc-steps = <0x01>; 246*0410b1afSXianjun Jiao adi,agc-outer-thresh-low = <0x12>; 247*0410b1afSXianjun Jiao adi,agc-outer-thresh-low-inc-steps = <0x02>; 248*0410b1afSXianjun Jiao adi,agc-adc-small-overload-exceed-counter = <0x0a>; 249*0410b1afSXianjun Jiao adi,agc-adc-large-overload-exceed-counter = <0x0a>; 250*0410b1afSXianjun Jiao adi,agc-adc-large-overload-inc-steps = <0x02>; 251*0410b1afSXianjun Jiao adi,agc-lmt-overload-large-exceed-counter = <0x0a>; 252*0410b1afSXianjun Jiao adi,agc-lmt-overload-small-exceed-counter = <0x0a>; 253*0410b1afSXianjun Jiao adi,agc-lmt-overload-large-inc-steps = <0x02>; 254*0410b1afSXianjun Jiao adi,agc-gain-update-interval-us = <0x3e8>; 255*0410b1afSXianjun Jiao adi,fagc-dec-pow-measurement-duration = <0x40>; 256*0410b1afSXianjun Jiao adi,fagc-lp-thresh-increment-steps = <0x01>; 257*0410b1afSXianjun Jiao adi,fagc-lp-thresh-increment-time = <0x05>; 258*0410b1afSXianjun Jiao adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x08>; 259*0410b1afSXianjun Jiao adi,fagc-final-overrange-count = <0x03>; 260*0410b1afSXianjun Jiao adi,fagc-gain-index-type-after-exit-rx-mode = <0x00>; 261*0410b1afSXianjun Jiao adi,fagc-lmt-final-settling-steps = <0x01>; 262*0410b1afSXianjun Jiao adi,fagc-lock-level = <0x0a>; 263*0410b1afSXianjun Jiao adi,fagc-lock-level-gain-increase-upper-limit = <0x05>; 264*0410b1afSXianjun Jiao adi,fagc-lock-level-lmt-gain-increase-enable; 265*0410b1afSXianjun Jiao adi,fagc-lpf-final-settling-steps = <0x01>; 266*0410b1afSXianjun Jiao adi,fagc-optimized-gain-offset = <0x05>; 267*0410b1afSXianjun Jiao adi,fagc-power-measurement-duration-in-state5 = <0x40>; 268*0410b1afSXianjun Jiao adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable; 269*0410b1afSXianjun Jiao adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0x0a>; 270*0410b1afSXianjun Jiao adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable; 271*0410b1afSXianjun Jiao adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x00>; 272*0410b1afSXianjun Jiao adi,fagc-rst-gla-large-adc-overload-enable; 273*0410b1afSXianjun Jiao adi,fagc-rst-gla-large-lmt-overload-enable; 274*0410b1afSXianjun Jiao adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0x0a>; 275*0410b1afSXianjun Jiao adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable; 276*0410b1afSXianjun Jiao adi,fagc-state-wait-time-ns = <0x104>; 277*0410b1afSXianjun Jiao adi,fagc-use-last-lock-level-for-set-gain-enable; 278*0410b1afSXianjun Jiao adi,rssi-restart-mode = <0x03>; 279*0410b1afSXianjun Jiao adi,rssi-delay = <0x01>; 280*0410b1afSXianjun Jiao adi,rssi-wait = <0x01>; 281*0410b1afSXianjun Jiao adi,rssi-duration = <0x3e8>; 282*0410b1afSXianjun Jiao adi,ctrl-outs-index = <0x00>; 283*0410b1afSXianjun Jiao adi,ctrl-outs-enable-mask = <0xff>; 284*0410b1afSXianjun Jiao adi,temp-sense-measurement-interval-ms = <0x3e8>; 285*0410b1afSXianjun Jiao adi,temp-sense-offset-signed = <0xce>; 286*0410b1afSXianjun Jiao adi,temp-sense-periodic-measurement-enable; 287*0410b1afSXianjun Jiao adi,aux-dac-manual-mode-enable; 288*0410b1afSXianjun Jiao adi,aux-dac1-default-value-mV = <0x00>; 289*0410b1afSXianjun Jiao adi,aux-dac1-rx-delay-us = <0x00>; 290*0410b1afSXianjun Jiao adi,aux-dac1-tx-delay-us = <0x00>; 291*0410b1afSXianjun Jiao adi,aux-dac2-default-value-mV = <0x00>; 292*0410b1afSXianjun Jiao adi,aux-dac2-rx-delay-us = <0x00>; 293*0410b1afSXianjun Jiao adi,aux-dac2-tx-delay-us = <0x00>; 294*0410b1afSXianjun Jiao en_agc-gpios = <0x06 0x62 0x00>; 295*0410b1afSXianjun Jiao sync-gpios = <0x06 0x63 0x00>; 296*0410b1afSXianjun Jiao reset-gpios = <0x06 0x64 0x00>; 297*0410b1afSXianjun Jiao enable-gpios = <0x06 0x65 0x00>; 298*0410b1afSXianjun Jiao txnrx-gpios = <0x06 0x66 0x00>; 299*0410b1afSXianjun Jiao linux,phandle = <0x0b>; 300*0410b1afSXianjun Jiao phandle = <0x0b>; 301*0410b1afSXianjun Jiao }; 302*0410b1afSXianjun Jiao }; 303*0410b1afSXianjun Jiao 304*0410b1afSXianjun Jiao spi@e0007000 { 305*0410b1afSXianjun Jiao compatible = "xlnx,zynq-spi-r1p6"; 306*0410b1afSXianjun Jiao reg = <0xe0007000 0x1000>; 307*0410b1afSXianjun Jiao status = "disabled"; 308*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 309*0410b1afSXianjun Jiao interrupts = <0x00 0x31 0x04>; 310*0410b1afSXianjun Jiao clocks = <0x02 0x1a 0x02 0x23>; 311*0410b1afSXianjun Jiao clock-names = "ref_clk\0pclk"; 312*0410b1afSXianjun Jiao #address-cells = <0x01>; 313*0410b1afSXianjun Jiao #size-cells = <0x00>; 314*0410b1afSXianjun Jiao }; 315*0410b1afSXianjun Jiao 316*0410b1afSXianjun Jiao spi@e000d000 { 317*0410b1afSXianjun Jiao clock-names = "ref_clk\0pclk"; 318*0410b1afSXianjun Jiao clocks = <0x02 0x0a 0x02 0x2b>; 319*0410b1afSXianjun Jiao compatible = "xlnx,zynq-qspi-1.0"; 320*0410b1afSXianjun Jiao status = "okay"; 321*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 322*0410b1afSXianjun Jiao interrupts = <0x00 0x13 0x04>; 323*0410b1afSXianjun Jiao reg = <0xe000d000 0x1000>; 324*0410b1afSXianjun Jiao #address-cells = <0x01>; 325*0410b1afSXianjun Jiao #size-cells = <0x00>; 326*0410b1afSXianjun Jiao is-dual = <0x00>; 327*0410b1afSXianjun Jiao num-cs = <0x01>; 328*0410b1afSXianjun Jiao 329*0410b1afSXianjun Jiao ps7-qspi@0 { 330*0410b1afSXianjun Jiao #address-cells = <0x01>; 331*0410b1afSXianjun Jiao #size-cells = <0x01>; 332*0410b1afSXianjun Jiao spi-tx-bus-width = <0x01>; 333*0410b1afSXianjun Jiao spi-rx-bus-width = <0x04>; 334*0410b1afSXianjun Jiao compatible = "n25q256a\0jedec,spi-nor"; 335*0410b1afSXianjun Jiao reg = <0x00>; 336*0410b1afSXianjun Jiao spi-max-frequency = <0x2faf080>; 337*0410b1afSXianjun Jiao 338*0410b1afSXianjun Jiao partition@qspi-fsbl-uboot { 339*0410b1afSXianjun Jiao label = "qspi-fsbl-uboot"; 340*0410b1afSXianjun Jiao reg = <0x00 0xe0000>; 341*0410b1afSXianjun Jiao }; 342*0410b1afSXianjun Jiao 343*0410b1afSXianjun Jiao partition@qspi-uboot-env { 344*0410b1afSXianjun Jiao label = "qspi-uboot-env"; 345*0410b1afSXianjun Jiao reg = <0xe0000 0x20000>; 346*0410b1afSXianjun Jiao }; 347*0410b1afSXianjun Jiao 348*0410b1afSXianjun Jiao partition@qspi-linux { 349*0410b1afSXianjun Jiao label = "qspi-linux"; 350*0410b1afSXianjun Jiao reg = <0x100000 0x500000>; 351*0410b1afSXianjun Jiao }; 352*0410b1afSXianjun Jiao 353*0410b1afSXianjun Jiao partition@qspi-device-tree { 354*0410b1afSXianjun Jiao label = "qspi-device-tree"; 355*0410b1afSXianjun Jiao reg = <0x600000 0x20000>; 356*0410b1afSXianjun Jiao }; 357*0410b1afSXianjun Jiao 358*0410b1afSXianjun Jiao partition@qspi-rootfs { 359*0410b1afSXianjun Jiao label = "qspi-rootfs"; 360*0410b1afSXianjun Jiao reg = <0x620000 0xce0000>; 361*0410b1afSXianjun Jiao }; 362*0410b1afSXianjun Jiao 363*0410b1afSXianjun Jiao partition@qspi-bitstream { 364*0410b1afSXianjun Jiao label = "qspi-bitstream"; 365*0410b1afSXianjun Jiao reg = <0x1300000 0xd00000>; 366*0410b1afSXianjun Jiao }; 367*0410b1afSXianjun Jiao }; 368*0410b1afSXianjun Jiao }; 369*0410b1afSXianjun Jiao 370*0410b1afSXianjun Jiao memory-controller@e000e000 { 371*0410b1afSXianjun Jiao #address-cells = <0x01>; 372*0410b1afSXianjun Jiao #size-cells = <0x01>; 373*0410b1afSXianjun Jiao status = "disabled"; 374*0410b1afSXianjun Jiao clock-names = "memclk\0aclk"; 375*0410b1afSXianjun Jiao clocks = <0x02 0x0b 0x02 0x2c>; 376*0410b1afSXianjun Jiao compatible = "arm,pl353-smc-r2p1"; 377*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 378*0410b1afSXianjun Jiao interrupts = <0x00 0x12 0x04>; 379*0410b1afSXianjun Jiao ranges; 380*0410b1afSXianjun Jiao reg = <0xe000e000 0x1000>; 381*0410b1afSXianjun Jiao 382*0410b1afSXianjun Jiao flash@e1000000 { 383*0410b1afSXianjun Jiao status = "disabled"; 384*0410b1afSXianjun Jiao compatible = "arm,pl353-nand-r2p1"; 385*0410b1afSXianjun Jiao reg = <0xe1000000 0x1000000>; 386*0410b1afSXianjun Jiao #address-cells = <0x01>; 387*0410b1afSXianjun Jiao #size-cells = <0x01>; 388*0410b1afSXianjun Jiao }; 389*0410b1afSXianjun Jiao 390*0410b1afSXianjun Jiao flash@e2000000 { 391*0410b1afSXianjun Jiao status = "disabled"; 392*0410b1afSXianjun Jiao compatible = "cfi-flash"; 393*0410b1afSXianjun Jiao reg = <0xe2000000 0x2000000>; 394*0410b1afSXianjun Jiao #address-cells = <0x01>; 395*0410b1afSXianjun Jiao #size-cells = <0x01>; 396*0410b1afSXianjun Jiao }; 397*0410b1afSXianjun Jiao }; 398*0410b1afSXianjun Jiao 399*0410b1afSXianjun Jiao ethernet@e000b000 { 400*0410b1afSXianjun Jiao compatible = "cdns,zynq-gem\0cdns,gem"; 401*0410b1afSXianjun Jiao reg = <0xe000b000 0x1000>; 402*0410b1afSXianjun Jiao status = "okay"; 403*0410b1afSXianjun Jiao interrupts = <0x00 0x16 0x04>; 404*0410b1afSXianjun Jiao clocks = <0x02 0x1e 0x02 0x1e 0x02 0x0d>; 405*0410b1afSXianjun Jiao clock-names = "pclk\0hclk\0tx_clk"; 406*0410b1afSXianjun Jiao #address-cells = <0x01>; 407*0410b1afSXianjun Jiao #size-cells = <0x00>; 408*0410b1afSXianjun Jiao phy-handle = <0x07>; 409*0410b1afSXianjun Jiao phy-mode = "rgmii-id"; 410*0410b1afSXianjun Jiao 411*0410b1afSXianjun Jiao phy@0 { 412*0410b1afSXianjun Jiao device_type = "ethernet-phy"; 413*0410b1afSXianjun Jiao reg = <0x00>; 414*0410b1afSXianjun Jiao marvell,reg-init = <0x03 0x10 0xff00 0x1e 0x03 0x11 0xfff0 0x00>; 415*0410b1afSXianjun Jiao linux,phandle = <0x07>; 416*0410b1afSXianjun Jiao phandle = <0x07>; 417*0410b1afSXianjun Jiao }; 418*0410b1afSXianjun Jiao }; 419*0410b1afSXianjun Jiao 420*0410b1afSXianjun Jiao ethernet@e000c000 { 421*0410b1afSXianjun Jiao compatible = "cdns,zynq-gem\0cdns,gem"; 422*0410b1afSXianjun Jiao reg = <0xe000c000 0x1000>; 423*0410b1afSXianjun Jiao status = "disabled"; 424*0410b1afSXianjun Jiao interrupts = <0x00 0x2d 0x04>; 425*0410b1afSXianjun Jiao clocks = <0x02 0x1f 0x02 0x1f 0x02 0x0e>; 426*0410b1afSXianjun Jiao clock-names = "pclk\0hclk\0tx_clk"; 427*0410b1afSXianjun Jiao #address-cells = <0x01>; 428*0410b1afSXianjun Jiao #size-cells = <0x00>; 429*0410b1afSXianjun Jiao }; 430*0410b1afSXianjun Jiao 431*0410b1afSXianjun Jiao mmc@e0100000 { 432*0410b1afSXianjun Jiao compatible = "arasan,sdhci-8.9a"; 433*0410b1afSXianjun Jiao status = "okay"; 434*0410b1afSXianjun Jiao clock-names = "clk_xin\0clk_ahb"; 435*0410b1afSXianjun Jiao clocks = <0x02 0x15 0x02 0x20>; 436*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 437*0410b1afSXianjun Jiao interrupts = <0x00 0x18 0x04>; 438*0410b1afSXianjun Jiao reg = <0xe0100000 0x1000>; 439*0410b1afSXianjun Jiao disable-wp; 440*0410b1afSXianjun Jiao }; 441*0410b1afSXianjun Jiao 442*0410b1afSXianjun Jiao mmc@e0101000 { 443*0410b1afSXianjun Jiao compatible = "arasan,sdhci-8.9a"; 444*0410b1afSXianjun Jiao status = "disabled"; 445*0410b1afSXianjun Jiao clock-names = "clk_xin\0clk_ahb"; 446*0410b1afSXianjun Jiao clocks = <0x02 0x16 0x02 0x21>; 447*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 448*0410b1afSXianjun Jiao interrupts = <0x00 0x2f 0x04>; 449*0410b1afSXianjun Jiao reg = <0xe0101000 0x1000>; 450*0410b1afSXianjun Jiao }; 451*0410b1afSXianjun Jiao 452*0410b1afSXianjun Jiao slcr@f8000000 { 453*0410b1afSXianjun Jiao u-boot,dm-pre-reloc; 454*0410b1afSXianjun Jiao #address-cells = <0x01>; 455*0410b1afSXianjun Jiao #size-cells = <0x01>; 456*0410b1afSXianjun Jiao compatible = "xlnx,zynq-slcr\0syscon\0simple-mfd"; 457*0410b1afSXianjun Jiao reg = <0xf8000000 0x1000>; 458*0410b1afSXianjun Jiao ranges; 459*0410b1afSXianjun Jiao linux,phandle = <0x08>; 460*0410b1afSXianjun Jiao phandle = <0x08>; 461*0410b1afSXianjun Jiao 462*0410b1afSXianjun Jiao clkc@100 { 463*0410b1afSXianjun Jiao u-boot,dm-pre-reloc; 464*0410b1afSXianjun Jiao #clock-cells = <0x01>; 465*0410b1afSXianjun Jiao compatible = "xlnx,ps7-clkc"; 466*0410b1afSXianjun Jiao fclk-enable = <0x0f>; 467*0410b1afSXianjun Jiao clock-output-names = "armpll\0ddrpll\0iopll\0cpu_6or4x\0cpu_3or2x\0cpu_2x\0cpu_1x\0ddr2x\0ddr3x\0dci\0lqspi\0smc\0pcap\0gem0\0gem1\0fclk0\0fclk1\0fclk2\0fclk3\0can0\0can1\0sdio0\0sdio1\0uart0\0uart1\0spi0\0spi1\0dma\0usb0_aper\0usb1_aper\0gem0_aper\0gem1_aper\0sdio0_aper\0sdio1_aper\0spi0_aper\0spi1_aper\0can0_aper\0can1_aper\0i2c0_aper\0i2c1_aper\0uart0_aper\0uart1_aper\0gpio_aper\0lqspi_aper\0smc_aper\0swdt\0dbg_trc\0dbg_apb"; 468*0410b1afSXianjun Jiao reg = <0x100 0x100>; 469*0410b1afSXianjun Jiao ps-clk-frequency = <0x1fca055>; 470*0410b1afSXianjun Jiao linux,phandle = <0x02>; 471*0410b1afSXianjun Jiao phandle = <0x02>; 472*0410b1afSXianjun Jiao }; 473*0410b1afSXianjun Jiao 474*0410b1afSXianjun Jiao rstc@200 { 475*0410b1afSXianjun Jiao compatible = "xlnx,zynq-reset"; 476*0410b1afSXianjun Jiao reg = <0x200 0x48>; 477*0410b1afSXianjun Jiao #reset-cells = <0x01>; 478*0410b1afSXianjun Jiao syscon = <0x08>; 479*0410b1afSXianjun Jiao }; 480*0410b1afSXianjun Jiao 481*0410b1afSXianjun Jiao pinctrl@700 { 482*0410b1afSXianjun Jiao compatible = "xlnx,pinctrl-zynq"; 483*0410b1afSXianjun Jiao reg = <0x700 0x200>; 484*0410b1afSXianjun Jiao syscon = <0x08>; 485*0410b1afSXianjun Jiao }; 486*0410b1afSXianjun Jiao }; 487*0410b1afSXianjun Jiao 488*0410b1afSXianjun Jiao dmac@f8003000 { 489*0410b1afSXianjun Jiao compatible = "arm,pl330\0arm,primecell"; 490*0410b1afSXianjun Jiao reg = <0xf8003000 0x1000>; 491*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 492*0410b1afSXianjun Jiao interrupt-names = "abort\0dma0\0dma1\0dma2\0dma3\0dma4\0dma5\0dma6\0dma7"; 493*0410b1afSXianjun Jiao interrupts = <0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04>; 494*0410b1afSXianjun Jiao #dma-cells = <0x01>; 495*0410b1afSXianjun Jiao #dma-channels = <0x08>; 496*0410b1afSXianjun Jiao #dma-requests = <0x04>; 497*0410b1afSXianjun Jiao clocks = <0x02 0x1b>; 498*0410b1afSXianjun Jiao clock-names = "apb_pclk"; 499*0410b1afSXianjun Jiao }; 500*0410b1afSXianjun Jiao 501*0410b1afSXianjun Jiao devcfg@f8007000 { 502*0410b1afSXianjun Jiao compatible = "xlnx,zynq-devcfg-1.0"; 503*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 504*0410b1afSXianjun Jiao interrupts = <0x00 0x08 0x04>; 505*0410b1afSXianjun Jiao reg = <0xf8007000 0x100>; 506*0410b1afSXianjun Jiao clocks = <0x02 0x0c 0x02 0x0f 0x02 0x10 0x02 0x11 0x02 0x12>; 507*0410b1afSXianjun Jiao clock-names = "ref_clk\0fclk0\0fclk1\0fclk2\0fclk3"; 508*0410b1afSXianjun Jiao syscon = <0x08>; 509*0410b1afSXianjun Jiao linux,phandle = <0x04>; 510*0410b1afSXianjun Jiao phandle = <0x04>; 511*0410b1afSXianjun Jiao }; 512*0410b1afSXianjun Jiao 513*0410b1afSXianjun Jiao efuse@f800d000 { 514*0410b1afSXianjun Jiao compatible = "xlnx,zynq-efuse"; 515*0410b1afSXianjun Jiao reg = <0xf800d000 0x20>; 516*0410b1afSXianjun Jiao }; 517*0410b1afSXianjun Jiao 518*0410b1afSXianjun Jiao timer@f8f00200 { 519*0410b1afSXianjun Jiao compatible = "arm,cortex-a9-global-timer"; 520*0410b1afSXianjun Jiao reg = <0xf8f00200 0x20>; 521*0410b1afSXianjun Jiao interrupts = <0x01 0x0b 0x301>; 522*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 523*0410b1afSXianjun Jiao clocks = <0x02 0x04>; 524*0410b1afSXianjun Jiao }; 525*0410b1afSXianjun Jiao 526*0410b1afSXianjun Jiao timer@f8001000 { 527*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 528*0410b1afSXianjun Jiao interrupts = <0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04>; 529*0410b1afSXianjun Jiao compatible = "cdns,ttc"; 530*0410b1afSXianjun Jiao clocks = <0x02 0x06>; 531*0410b1afSXianjun Jiao reg = <0xf8001000 0x1000>; 532*0410b1afSXianjun Jiao }; 533*0410b1afSXianjun Jiao 534*0410b1afSXianjun Jiao timer@f8002000 { 535*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 536*0410b1afSXianjun Jiao interrupts = <0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04>; 537*0410b1afSXianjun Jiao compatible = "cdns,ttc"; 538*0410b1afSXianjun Jiao clocks = <0x02 0x06>; 539*0410b1afSXianjun Jiao reg = <0xf8002000 0x1000>; 540*0410b1afSXianjun Jiao }; 541*0410b1afSXianjun Jiao 542*0410b1afSXianjun Jiao timer@f8f00600 { 543*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 544*0410b1afSXianjun Jiao interrupts = <0x01 0x0d 0x301>; 545*0410b1afSXianjun Jiao compatible = "arm,cortex-a9-twd-timer"; 546*0410b1afSXianjun Jiao reg = <0xf8f00600 0x20>; 547*0410b1afSXianjun Jiao clocks = <0x02 0x04>; 548*0410b1afSXianjun Jiao }; 549*0410b1afSXianjun Jiao 550*0410b1afSXianjun Jiao usb@e0002000 { 551*0410b1afSXianjun Jiao compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2"; 552*0410b1afSXianjun Jiao status = "okay"; 553*0410b1afSXianjun Jiao clocks = <0x02 0x1c>; 554*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 555*0410b1afSXianjun Jiao interrupts = <0x00 0x15 0x04>; 556*0410b1afSXianjun Jiao reg = <0xe0002000 0x1000>; 557*0410b1afSXianjun Jiao phy_type = "ulpi"; 558*0410b1afSXianjun Jiao dr_mode = "host"; 559*0410b1afSXianjun Jiao xlnx,phy-reset-gpio = <0x06 0x07 0x00>; 560*0410b1afSXianjun Jiao }; 561*0410b1afSXianjun Jiao 562*0410b1afSXianjun Jiao usb@e0003000 { 563*0410b1afSXianjun Jiao compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2"; 564*0410b1afSXianjun Jiao status = "disabled"; 565*0410b1afSXianjun Jiao clocks = <0x02 0x1d>; 566*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 567*0410b1afSXianjun Jiao interrupts = <0x00 0x2c 0x04>; 568*0410b1afSXianjun Jiao reg = <0xe0003000 0x1000>; 569*0410b1afSXianjun Jiao phy_type = "ulpi"; 570*0410b1afSXianjun Jiao }; 571*0410b1afSXianjun Jiao 572*0410b1afSXianjun Jiao watchdog@f8005000 { 573*0410b1afSXianjun Jiao clocks = <0x02 0x2d>; 574*0410b1afSXianjun Jiao compatible = "cdns,wdt-r1p2"; 575*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 576*0410b1afSXianjun Jiao interrupts = <0x00 0x09 0x01>; 577*0410b1afSXianjun Jiao reg = <0xf8005000 0x1000>; 578*0410b1afSXianjun Jiao timeout-sec = <0x0a>; 579*0410b1afSXianjun Jiao }; 580*0410b1afSXianjun Jiao }; 581*0410b1afSXianjun Jiao 582*0410b1afSXianjun Jiao aliases { 583*0410b1afSXianjun Jiao ethernet0 = "/amba/ethernet@e000b000"; 584*0410b1afSXianjun Jiao serial0 = "/amba/serial@e0001000"; 585*0410b1afSXianjun Jiao }; 586*0410b1afSXianjun Jiao 587*0410b1afSXianjun Jiao memory { 588*0410b1afSXianjun Jiao device_type = "memory"; 589*0410b1afSXianjun Jiao reg = <0x00 0x40000000>; 590*0410b1afSXianjun Jiao }; 591*0410b1afSXianjun Jiao 592*0410b1afSXianjun Jiao chosen { 593*0410b1afSXianjun Jiao linux,stdout-path = "/amba@0/uart@E0001000"; 594*0410b1afSXianjun Jiao }; 595*0410b1afSXianjun Jiao 596*0410b1afSXianjun Jiao clocks { 597*0410b1afSXianjun Jiao 598*0410b1afSXianjun Jiao clock@0 { 599*0410b1afSXianjun Jiao #clock-cells = <0x00>; 600*0410b1afSXianjun Jiao compatible = "adjustable-clock"; 601*0410b1afSXianjun Jiao clock-frequency = <0x2625a00>; 602*0410b1afSXianjun Jiao clock-accuracy = <0x30d40>; 603*0410b1afSXianjun Jiao clock-output-names = "ad9364_ext_refclk"; 604*0410b1afSXianjun Jiao linux,phandle = <0x05>; 605*0410b1afSXianjun Jiao phandle = <0x05>; 606*0410b1afSXianjun Jiao }; 607*0410b1afSXianjun Jiao 608*0410b1afSXianjun Jiao clock@1 { 609*0410b1afSXianjun Jiao #clock-cells = <0x00>; 610*0410b1afSXianjun Jiao compatible = "fixed-clock"; 611*0410b1afSXianjun Jiao clock-frequency = <0x16e3600>; 612*0410b1afSXianjun Jiao clock-output-names = "24MHz"; 613*0410b1afSXianjun Jiao linux,phandle = <0x09>; 614*0410b1afSXianjun Jiao phandle = <0x09>; 615*0410b1afSXianjun Jiao }; 616*0410b1afSXianjun Jiao }; 617*0410b1afSXianjun Jiao 618*0410b1afSXianjun Jiao usb-ulpi-gpio-gate@0 { 619*0410b1afSXianjun Jiao compatible = "gpio-gate-clock"; 620*0410b1afSXianjun Jiao clocks = <0x09>; 621*0410b1afSXianjun Jiao #clock-cells = <0x00>; 622*0410b1afSXianjun Jiao enable-gpios = <0x06 0x09 0x01>; 623*0410b1afSXianjun Jiao }; 624*0410b1afSXianjun Jiao 625*0410b1afSXianjun Jiao fpga-axi@0 { 626*0410b1afSXianjun Jiao compatible = "simple-bus"; 627*0410b1afSXianjun Jiao #address-cells = <0x01>; 628*0410b1afSXianjun Jiao #size-cells = <0x01>; 629*0410b1afSXianjun Jiao ranges; 630*0410b1afSXianjun Jiao 631*0410b1afSXianjun Jiao i2c@41600000 { 632*0410b1afSXianjun Jiao compatible = "xlnx,axi-iic-1.02.a\0xlnx,xps-iic-2.00.a"; 633*0410b1afSXianjun Jiao reg = <0x41600000 0x10000>; 634*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 635*0410b1afSXianjun Jiao interrupts = <0x00 0x3a 0x04>; 636*0410b1afSXianjun Jiao clocks = <0x02 0x0f>; 637*0410b1afSXianjun Jiao clock-names = "pclk"; 638*0410b1afSXianjun Jiao #address-cells = <0x01>; 639*0410b1afSXianjun Jiao #size-cells = <0x00>; 640*0410b1afSXianjun Jiao 641*0410b1afSXianjun Jiao ad7291@20 { 642*0410b1afSXianjun Jiao compatible = "adi,ad7291"; 643*0410b1afSXianjun Jiao reg = <0x20>; 644*0410b1afSXianjun Jiao }; 645*0410b1afSXianjun Jiao 646*0410b1afSXianjun Jiao ad7291-bob@2C { 647*0410b1afSXianjun Jiao compatible = "adi,ad7291"; 648*0410b1afSXianjun Jiao reg = <0x2c>; 649*0410b1afSXianjun Jiao }; 650*0410b1afSXianjun Jiao 651*0410b1afSXianjun Jiao eeprom@50 { 652*0410b1afSXianjun Jiao compatible = "at24,24c32"; 653*0410b1afSXianjun Jiao reg = <0x50>; 654*0410b1afSXianjun Jiao }; 655*0410b1afSXianjun Jiao }; 656*0410b1afSXianjun Jiao 657*0410b1afSXianjun Jiao sdr { 658*0410b1afSXianjun Jiao compatible = "sdr,sdr"; 659*0410b1afSXianjun Jiao dmas = <0x0a 0x01 0x0c 0x00>; 660*0410b1afSXianjun Jiao dma-names = "rx_dma_s2mm\0tx_dma_mm2s"; 661*0410b1afSXianjun Jiao interrupt-names = "not_valid_anymore\0rx_pkt_intr\0tx_itrpt"; 662*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 663*0410b1afSXianjun Jiao interrupts = <0x00 0x1d 0x01 0x00 0x1e 0x01 0x00 0x21 0x01 0x00 0x22 0x01>; 664*0410b1afSXianjun Jiao }; 665*0410b1afSXianjun Jiao 666*0410b1afSXianjun Jiao axidmatest@1 { 667*0410b1afSXianjun Jiao compatible = "xlnx,axi-dma-test-1.00.a"; 668*0410b1afSXianjun Jiao dmas = <0x0a 0x00 0x0a 0x01>; 669*0410b1afSXianjun Jiao dma-names = "axidma0\0axidma1"; 670*0410b1afSXianjun Jiao }; 671*0410b1afSXianjun Jiao 672*0410b1afSXianjun Jiao dma@80400000 { 673*0410b1afSXianjun Jiao #dma-cells = <0x01>; 674*0410b1afSXianjun Jiao clock-names = "s_axi_lite_aclk\0m_axi_sg_aclk\0m_axi_mm2s_aclk\0m_axi_s2mm_aclk"; 675*0410b1afSXianjun Jiao clocks = <0x02 0x11 0x02 0x11 0x02 0x11 0x02 0x11>; 676*0410b1afSXianjun Jiao compatible = "xlnx,axi-dma-1.00.a"; 677*0410b1afSXianjun Jiao interrupt-names = "mm2s_introut\0s2mm_introut"; 678*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 679*0410b1afSXianjun Jiao interrupts = <0x00 0x23 0x04 0x00 0x24 0x04>; 680*0410b1afSXianjun Jiao reg = <0x80400000 0x10000>; 681*0410b1afSXianjun Jiao xlnx,addrwidth = <0x20>; 682*0410b1afSXianjun Jiao xlnx,include-sg; 683*0410b1afSXianjun Jiao xlnx,sg-length-width = <0x0e>; 684*0410b1afSXianjun Jiao phandle = <0x0c>; 685*0410b1afSXianjun Jiao 686*0410b1afSXianjun Jiao dma-channel@80400000 { 687*0410b1afSXianjun Jiao compatible = "xlnx,axi-dma-mm2s-channel"; 688*0410b1afSXianjun Jiao dma-channels = <0x01>; 689*0410b1afSXianjun Jiao interrupts = <0x00 0x23 0x04>; 690*0410b1afSXianjun Jiao xlnx,datawidth = <0x40>; 691*0410b1afSXianjun Jiao xlnx,device-id = <0x00>; 692*0410b1afSXianjun Jiao }; 693*0410b1afSXianjun Jiao 694*0410b1afSXianjun Jiao dma-channel@80400030 { 695*0410b1afSXianjun Jiao compatible = "xlnx,axi-dma-s2mm-channel"; 696*0410b1afSXianjun Jiao dma-channels = <0x01>; 697*0410b1afSXianjun Jiao interrupts = <0x00 0x24 0x04>; 698*0410b1afSXianjun Jiao xlnx,datawidth = <0x40>; 699*0410b1afSXianjun Jiao xlnx,device-id = <0x00>; 700*0410b1afSXianjun Jiao }; 701*0410b1afSXianjun Jiao }; 702*0410b1afSXianjun Jiao 703*0410b1afSXianjun Jiao dma@80410000 { 704*0410b1afSXianjun Jiao #dma-cells = <0x01>; 705*0410b1afSXianjun Jiao clock-names = "s_axi_lite_aclk\0m_axi_sg_aclk\0m_axi_mm2s_aclk\0m_axi_s2mm_aclk"; 706*0410b1afSXianjun Jiao clocks = <0x02 0x11 0x02 0x11 0x02 0x11 0x02 0x11>; 707*0410b1afSXianjun Jiao compatible = "xlnx,axi-dma-1.00.a"; 708*0410b1afSXianjun Jiao interrupt-names = "mm2s_introut\0s2mm_introut"; 709*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 710*0410b1afSXianjun Jiao interrupts = <0x00 0x1f 0x04 0x00 0x20 0x04>; 711*0410b1afSXianjun Jiao reg = <0x80410000 0x10000>; 712*0410b1afSXianjun Jiao xlnx,addrwidth = <0x20>; 713*0410b1afSXianjun Jiao xlnx,include-sg; 714*0410b1afSXianjun Jiao xlnx,sg-length-width = <0x0e>; 715*0410b1afSXianjun Jiao phandle = <0x0a>; 716*0410b1afSXianjun Jiao 717*0410b1afSXianjun Jiao dma-channel@80410000 { 718*0410b1afSXianjun Jiao compatible = "xlnx,axi-dma-mm2s-channel"; 719*0410b1afSXianjun Jiao dma-channels = <0x01>; 720*0410b1afSXianjun Jiao interrupts = <0x00 0x1f 0x04>; 721*0410b1afSXianjun Jiao xlnx,datawidth = <0x40>; 722*0410b1afSXianjun Jiao xlnx,device-id = <0x01>; 723*0410b1afSXianjun Jiao }; 724*0410b1afSXianjun Jiao 725*0410b1afSXianjun Jiao dma-channel@80410030 { 726*0410b1afSXianjun Jiao compatible = "xlnx,axi-dma-s2mm-channel"; 727*0410b1afSXianjun Jiao dma-channels = <0x01>; 728*0410b1afSXianjun Jiao interrupts = <0x00 0x20 0x04>; 729*0410b1afSXianjun Jiao xlnx,datawidth = <0x40>; 730*0410b1afSXianjun Jiao xlnx,device-id = <0x01>; 731*0410b1afSXianjun Jiao }; 732*0410b1afSXianjun Jiao }; 733*0410b1afSXianjun Jiao 734*0410b1afSXianjun Jiao tx_intf@83c00000 { 735*0410b1afSXianjun Jiao clock-names = "s00_axi_aclk\0s00_axis_aclk"; 736*0410b1afSXianjun Jiao clocks = <0x02 0x11 0x02 0x11>; 737*0410b1afSXianjun Jiao compatible = "sdr,tx_intf"; 738*0410b1afSXianjun Jiao interrupt-names = "tx_itrpt"; 739*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 740*0410b1afSXianjun Jiao interrupts = <0x00 0x22 0x01>; 741*0410b1afSXianjun Jiao reg = <0x83c00000 0x10000>; 742*0410b1afSXianjun Jiao xlnx,s00-axi-addr-width = <0x07>; 743*0410b1afSXianjun Jiao xlnx,s00-axi-data-width = <0x20>; 744*0410b1afSXianjun Jiao }; 745*0410b1afSXianjun Jiao 746*0410b1afSXianjun Jiao rx_intf@83c20000 { 747*0410b1afSXianjun Jiao clock-names = "s00_axi_aclk\0m00_axis_aclk"; 748*0410b1afSXianjun Jiao clocks = <0x02 0x11 0x02 0x11>; 749*0410b1afSXianjun Jiao compatible = "sdr,rx_intf"; 750*0410b1afSXianjun Jiao interrupt-names = "not_valid_anymore\0rx_pkt_intr"; 751*0410b1afSXianjun Jiao interrupt-parent = <0x01>; 752*0410b1afSXianjun Jiao interrupts = <0x00 0x1d 0x01 0x00 0x1e 0x01>; 753*0410b1afSXianjun Jiao reg = <0x83c20000 0x10000>; 754*0410b1afSXianjun Jiao xlnx,s00-axi-addr-width = <0x07>; 755*0410b1afSXianjun Jiao xlnx,s00-axi-data-width = <0x20>; 756*0410b1afSXianjun Jiao }; 757*0410b1afSXianjun Jiao 758*0410b1afSXianjun Jiao openofdm_tx@83c10000 { 759*0410b1afSXianjun Jiao clock-names = "clk"; 760*0410b1afSXianjun Jiao clocks = <0x02 0x11>; 761*0410b1afSXianjun Jiao compatible = "sdr,openofdm_tx"; 762*0410b1afSXianjun Jiao reg = <0x83c10000 0x10000>; 763*0410b1afSXianjun Jiao }; 764*0410b1afSXianjun Jiao 765*0410b1afSXianjun Jiao openofdm_rx@83c30000 { 766*0410b1afSXianjun Jiao clock-names = "clk"; 767*0410b1afSXianjun Jiao clocks = <0x02 0x11>; 768*0410b1afSXianjun Jiao compatible = "sdr,openofdm_rx"; 769*0410b1afSXianjun Jiao reg = <0x83c30000 0x10000>; 770*0410b1afSXianjun Jiao }; 771*0410b1afSXianjun Jiao 772*0410b1afSXianjun Jiao xpu@83c40000 { 773*0410b1afSXianjun Jiao clock-names = "s00_axi_aclk"; 774*0410b1afSXianjun Jiao clocks = <0x02 0x11>; 775*0410b1afSXianjun Jiao compatible = "sdr,xpu"; 776*0410b1afSXianjun Jiao reg = <0x83c40000 0x10000>; 777*0410b1afSXianjun Jiao }; 778*0410b1afSXianjun Jiao 779*0410b1afSXianjun Jiao side_ch@83c50000 { 780*0410b1afSXianjun Jiao clock-names = "s00_axi_aclk"; 781*0410b1afSXianjun Jiao clocks = <0x02 0x11>; 782*0410b1afSXianjun Jiao compatible = "sdr,side_ch"; 783*0410b1afSXianjun Jiao reg = <0x83c50000 0x10000>; 784*0410b1afSXianjun Jiao dmas = <0x0a 0x00 0x0c 0x01>; 785*0410b1afSXianjun Jiao dma-names = "rx_dma_mm2s\0tx_dma_s2mm"; 786*0410b1afSXianjun Jiao }; 787*0410b1afSXianjun Jiao 788*0410b1afSXianjun Jiao cf-ad9361-lpc@79020000 { 789*0410b1afSXianjun Jiao compatible = "adi,axi-ad9361-6.00.a"; 790*0410b1afSXianjun Jiao reg = <0x79020000 0x6000>; 791*0410b1afSXianjun Jiao spibus-connected = <0x0b>; 792*0410b1afSXianjun Jiao }; 793*0410b1afSXianjun Jiao 794*0410b1afSXianjun Jiao cf-ad9361-dds-core-lpc@79024000 { 795*0410b1afSXianjun Jiao compatible = "adi,axi-ad9361-dds-6.00.a"; 796*0410b1afSXianjun Jiao reg = <0x79024000 0x1000>; 797*0410b1afSXianjun Jiao clocks = <0x0b 0x0d>; 798*0410b1afSXianjun Jiao clock-names = "sampl_clk"; 799*0410b1afSXianjun Jiao }; 800*0410b1afSXianjun Jiao 801*0410b1afSXianjun Jiao mwipcore@43c00000 { 802*0410b1afSXianjun Jiao compatible = "mathworks,mwipcore-axi4lite-v1.00"; 803*0410b1afSXianjun Jiao reg = <0x43c00000 0xffff>; 804*0410b1afSXianjun Jiao }; 805*0410b1afSXianjun Jiao }; 806*0410b1afSXianjun Jiao 807*0410b1afSXianjun Jiao leds { 808*0410b1afSXianjun Jiao compatible = "gpio-leds"; 809*0410b1afSXianjun Jiao 810*0410b1afSXianjun Jiao led0 { 811*0410b1afSXianjun Jiao label = "led0:green"; 812*0410b1afSXianjun Jiao gpios = <0x06 0x3a 0x00>; 813*0410b1afSXianjun Jiao }; 814*0410b1afSXianjun Jiao 815*0410b1afSXianjun Jiao led1 { 816*0410b1afSXianjun Jiao label = "led1:green"; 817*0410b1afSXianjun Jiao gpios = <0x06 0x3b 0x00>; 818*0410b1afSXianjun Jiao }; 819*0410b1afSXianjun Jiao 820*0410b1afSXianjun Jiao led2 { 821*0410b1afSXianjun Jiao label = "led2:green"; 822*0410b1afSXianjun Jiao gpios = <0x06 0x3c 0x00>; 823*0410b1afSXianjun Jiao }; 824*0410b1afSXianjun Jiao 825*0410b1afSXianjun Jiao led3 { 826*0410b1afSXianjun Jiao label = "led3:green"; 827*0410b1afSXianjun Jiao gpios = <0x06 0x3d 0x00>; 828*0410b1afSXianjun Jiao }; 829*0410b1afSXianjun Jiao }; 830*0410b1afSXianjun Jiao 831*0410b1afSXianjun Jiao gpio_keys { 832*0410b1afSXianjun Jiao compatible = "gpio-keys"; 833*0410b1afSXianjun Jiao #address-cells = <0x01>; 834*0410b1afSXianjun Jiao #size-cells = <0x00>; 835*0410b1afSXianjun Jiao autorepeat; 836*0410b1afSXianjun Jiao 837*0410b1afSXianjun Jiao pb0 { 838*0410b1afSXianjun Jiao label = "Left"; 839*0410b1afSXianjun Jiao linux,code = <0x69>; 840*0410b1afSXianjun Jiao gpios = <0x06 0x36 0x00>; 841*0410b1afSXianjun Jiao }; 842*0410b1afSXianjun Jiao 843*0410b1afSXianjun Jiao pb1 { 844*0410b1afSXianjun Jiao label = "Right"; 845*0410b1afSXianjun Jiao linux,code = <0x6a>; 846*0410b1afSXianjun Jiao gpios = <0x06 0x37 0x00>; 847*0410b1afSXianjun Jiao }; 848*0410b1afSXianjun Jiao 849*0410b1afSXianjun Jiao pb2 { 850*0410b1afSXianjun Jiao label = "Up"; 851*0410b1afSXianjun Jiao linux,code = <0x67>; 852*0410b1afSXianjun Jiao gpios = <0x06 0x38 0x00>; 853*0410b1afSXianjun Jiao }; 854*0410b1afSXianjun Jiao 855*0410b1afSXianjun Jiao pb3 { 856*0410b1afSXianjun Jiao label = "Down"; 857*0410b1afSXianjun Jiao linux,code = <0x6c>; 858*0410b1afSXianjun Jiao gpios = <0x06 0x39 0x00>; 859*0410b1afSXianjun Jiao }; 860*0410b1afSXianjun Jiao 861*0410b1afSXianjun Jiao sw0 { 862*0410b1afSXianjun Jiao label = "SW0"; 863*0410b1afSXianjun Jiao linux,input-type = <0x05>; 864*0410b1afSXianjun Jiao linux,code = <0x00>; 865*0410b1afSXianjun Jiao gpios = <0x06 0x3e 0x00>; 866*0410b1afSXianjun Jiao }; 867*0410b1afSXianjun Jiao 868*0410b1afSXianjun Jiao sw1 { 869*0410b1afSXianjun Jiao label = "SW1"; 870*0410b1afSXianjun Jiao linux,input-type = <0x05>; 871*0410b1afSXianjun Jiao linux,code = <0x01>; 872*0410b1afSXianjun Jiao gpios = <0x06 0x3f 0x00>; 873*0410b1afSXianjun Jiao }; 874*0410b1afSXianjun Jiao 875*0410b1afSXianjun Jiao sw2 { 876*0410b1afSXianjun Jiao label = "SW2"; 877*0410b1afSXianjun Jiao linux,input-type = <0x05>; 878*0410b1afSXianjun Jiao linux,code = <0x02>; 879*0410b1afSXianjun Jiao gpios = <0x06 0x40 0x00>; 880*0410b1afSXianjun Jiao }; 881*0410b1afSXianjun Jiao 882*0410b1afSXianjun Jiao sw3 { 883*0410b1afSXianjun Jiao label = "SW3"; 884*0410b1afSXianjun Jiao linux,input-type = <0x05>; 885*0410b1afSXianjun Jiao linux,code = <0x03>; 886*0410b1afSXianjun Jiao gpios = <0x06 0x41 0x00>; 887*0410b1afSXianjun Jiao }; 888*0410b1afSXianjun Jiao }; 889*0410b1afSXianjun Jiao}; 890