1/dts-v1/; 2 3/ { 4 #address-cells = <0x01>; 5 #size-cells = <0x01>; 6 compatible = "xlnx,zynq-7000"; 7 interrupt-parent = <0x01>; 8 model = "ANTSDR-E310V2"; 9 10 cpus { 11 #address-cells = <0x01>; 12 #size-cells = <0x00>; 13 14 cpu@0 { 15 compatible = "arm,cortex-a9"; 16 device_type = "cpu"; 17 reg = <0x00>; 18 clocks = <0x02 0x03>; 19 clock-latency = <0x3e8>; 20 cpu0-supply = <0x03>; 21 operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>; 22 phandle = <0x11>; 23 }; 24 25 cpu@1 { 26 compatible = "arm,cortex-a9"; 27 device_type = "cpu"; 28 reg = <0x01>; 29 clocks = <0x02 0x03>; 30 phandle = <0x13>; 31 }; 32 }; 33 34 fpga-full { 35 compatible = "fpga-region"; 36 fpga-mgr = <0x04>; 37 #address-cells = <0x01>; 38 #size-cells = <0x01>; 39 ranges; 40 phandle = <0x19>; 41 }; 42 43 pmu@f8891000 { 44 compatible = "arm,cortex-a9-pmu"; 45 interrupts = <0x00 0x05 0x04 0x00 0x06 0x04>; 46 interrupt-parent = <0x01>; 47 reg = <0xf8891000 0x1000 0xf8893000 0x1000>; 48 }; 49 50 fixedregulator { 51 compatible = "regulator-fixed"; 52 regulator-name = "VCCPINT"; 53 regulator-min-microvolt = <0xf4240>; 54 regulator-max-microvolt = <0xf4240>; 55 regulator-boot-on; 56 regulator-always-on; 57 phandle = <0x03>; 58 }; 59 60 replicator { 61 compatible = "arm,coresight-static-replicator"; 62 clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; 63 clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; 64 65 out-ports { 66 #address-cells = <0x01>; 67 #size-cells = <0x00>; 68 69 port@0 { 70 reg = <0x00>; 71 72 endpoint { 73 remote-endpoint = <0x05>; 74 phandle = <0x0d>; 75 }; 76 }; 77 78 port@1 { 79 reg = <0x01>; 80 81 endpoint { 82 remote-endpoint = <0x06>; 83 phandle = <0x0c>; 84 }; 85 }; 86 }; 87 88 in-ports { 89 90 port { 91 92 endpoint { 93 remote-endpoint = <0x07>; 94 phandle = <0x0e>; 95 }; 96 }; 97 }; 98 }; 99 100 axi { 101 u-boot,dm-pre-reloc; 102 compatible = "simple-bus"; 103 #address-cells = <0x01>; 104 #size-cells = <0x01>; 105 interrupt-parent = <0x01>; 106 ranges; 107 phandle = <0x1a>; 108 109 adc@f8007100 { 110 compatible = "xlnx,zynq-xadc-1.00.a"; 111 reg = <0xf8007100 0x20>; 112 interrupts = <0x00 0x07 0x04>; 113 interrupt-parent = <0x01>; 114 clocks = <0x02 0x0c>; 115 phandle = <0x1b>; 116 }; 117 118 can@e0008000 { 119 compatible = "xlnx,zynq-can-1.0"; 120 status = "disabled"; 121 clocks = <0x02 0x13 0x02 0x24>; 122 clock-names = "can_clk\0pclk"; 123 reg = <0xe0008000 0x1000>; 124 interrupts = <0x00 0x1c 0x04>; 125 interrupt-parent = <0x01>; 126 tx-fifo-depth = <0x40>; 127 rx-fifo-depth = <0x40>; 128 phandle = <0x1c>; 129 }; 130 131 can@e0009000 { 132 compatible = "xlnx,zynq-can-1.0"; 133 status = "disabled"; 134 clocks = <0x02 0x14 0x02 0x25>; 135 clock-names = "can_clk\0pclk"; 136 reg = <0xe0009000 0x1000>; 137 interrupts = <0x00 0x33 0x04>; 138 interrupt-parent = <0x01>; 139 tx-fifo-depth = <0x40>; 140 rx-fifo-depth = <0x40>; 141 phandle = <0x1d>; 142 }; 143 144 gpio@e000a000 { 145 compatible = "xlnx,zynq-gpio-1.0"; 146 #gpio-cells = <0x02>; 147 clocks = <0x02 0x2a>; 148 gpio-controller; 149 interrupt-controller; 150 #interrupt-cells = <0x02>; 151 interrupt-parent = <0x01>; 152 interrupts = <0x00 0x14 0x04>; 153 reg = <0xe000a000 0x1000>; 154 phandle = <0x09>; 155 }; 156 157 i2c@e0004000 { 158 compatible = "cdns,i2c-r1p10"; 159 status = "disabled"; 160 clocks = <0x02 0x26>; 161 interrupt-parent = <0x01>; 162 interrupts = <0x00 0x19 0x04>; 163 reg = <0xe0004000 0x1000>; 164 #address-cells = <0x01>; 165 #size-cells = <0x00>; 166 phandle = <0x1e>; 167 }; 168 169 i2c@e0005000 { 170 compatible = "cdns,i2c-r1p10"; 171 status = "disabled"; 172 clocks = <0x02 0x27>; 173 interrupt-parent = <0x01>; 174 interrupts = <0x00 0x30 0x04>; 175 reg = <0xe0005000 0x1000>; 176 #address-cells = <0x01>; 177 #size-cells = <0x00>; 178 phandle = <0x1f>; 179 }; 180 181 interrupt-controller@f8f01000 { 182 compatible = "arm,cortex-a9-gic"; 183 #interrupt-cells = <0x03>; 184 interrupt-controller; 185 reg = <0xf8f01000 0x1000 0xf8f00100 0x100>; 186 phandle = <0x01>; 187 }; 188 189 cache-controller@f8f02000 { 190 compatible = "arm,pl310-cache"; 191 reg = <0xf8f02000 0x1000>; 192 interrupts = <0x00 0x02 0x04>; 193 arm,data-latency = <0x03 0x02 0x02>; 194 arm,tag-latency = <0x02 0x02 0x02>; 195 cache-unified; 196 cache-level = <0x02>; 197 phandle = <0x20>; 198 }; 199 200 memory-controller@f8006000 { 201 compatible = "xlnx,zynq-ddrc-a05"; 202 reg = <0xf8006000 0x1000>; 203 phandle = <0x21>; 204 }; 205 206 ocmc@f800c000 { 207 compatible = "xlnx,zynq-ocmc-1.0"; 208 interrupt-parent = <0x01>; 209 interrupts = <0x00 0x03 0x04>; 210 reg = <0xf800c000 0x1000>; 211 phandle = <0x22>; 212 }; 213 214 serial@e0000000 { 215 compatible = "xlnx,xuartps\0cdns,uart-r1p8"; 216 status = "disabled"; 217 clocks = <0x02 0x17 0x02 0x28>; 218 clock-names = "uart_clk\0pclk"; 219 reg = <0xe0000000 0x1000>; 220 interrupts = <0x00 0x1b 0x04>; 221 phandle = <0x23>; 222 }; 223 224 serial@e0001000 { 225 compatible = "xlnx,xuartps\0cdns,uart-r1p8"; 226 status = "okay"; 227 clocks = <0x02 0x18 0x02 0x29>; 228 clock-names = "uart_clk\0pclk"; 229 reg = <0xe0001000 0x1000>; 230 interrupts = <0x00 0x32 0x04>; 231 phandle = <0x24>; 232 }; 233 234 spi@e0006000 { 235 compatible = "xlnx,zynq-spi-r1p6"; 236 reg = <0xe0006000 0x1000>; 237 status = "okay"; 238 interrupt-parent = <0x01>; 239 interrupts = <0x00 0x1a 0x04>; 240 clocks = <0x02 0x19 0x02 0x22>; 241 clock-names = "ref_clk\0pclk"; 242 #address-cells = <0x01>; 243 #size-cells = <0x00>; 244 phandle = <0x25>; 245 246 ad9361-phy@0 { 247 #address-cells = <0x1>; 248 #size-cells = <0x0>; 249 #clock-cells = <0x1>; 250 compatible = "adi,ad9361"; 251 reg = <0x0>; 252 spi-cpha; 253 spi-max-frequency = <0x989680>; 254 clocks = <0x08 0x00>; 255 clock-names = "ad9361_ext_refclk"; 256 clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; 257 adi,digital-interface-tune-skip-mode = <0x0>; 258 adi,pp-tx-swap-enable; 259 adi,pp-rx-swap-enable; 260 adi,rx-frame-pulse-mode-enable; 261 adi,lvds-mode-enable; 262 adi,lvds-bias-mV = <0x96>; 263 adi,lvds-rx-onchip-termination-enable; 264 adi,rx-data-delay = <0x4>; 265 adi,tx-fb-clock-delay = <0x7>; 266 adi,xo-disable-use-ext-refclk-enable; 267 adi,2rx-2tx-mode-enable; 268 adi,frequency-division-duplex-mode-enable; 269 adi,rx-rf-port-input-select = <0x0>; 270 adi,tx-rf-port-input-select = <0x0>; 271 adi,tx-attenuation-mdB = <0x2710>; 272 adi,tx-lo-powerdown-managed-enable; 273 adi,rf-rx-bandwidth-hz = <0x112a880>; 274 adi,rf-tx-bandwidth-hz = <0x112a880>; 275 adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>; 276 adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>; 277 adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 278 adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 279 adi,gc-rx1-mode = <0x2>; 280 adi,gc-rx2-mode = <0x2>; 281 adi,gc-adc-ovr-sample-size = <0x4>; 282 adi,gc-adc-small-overload-thresh = <0x2f>; 283 adi,gc-adc-large-overload-thresh = <0x3a>; 284 adi,gc-lmt-overload-high-thresh = <0x320>; 285 adi,gc-lmt-overload-low-thresh = <0x2c0>; 286 adi,gc-dec-pow-measurement-duration = <0x2000>; 287 adi,gc-low-power-thresh = <0x18>; 288 adi,mgc-inc-gain-step = <0x2>; 289 adi,mgc-dec-gain-step = <0x2>; 290 adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>; 291 adi,agc-attack-delay-extra-margin-us = <0x1>; 292 adi,agc-outer-thresh-high = <0x5>; 293 adi,agc-outer-thresh-high-dec-steps = <0x2>; 294 adi,agc-inner-thresh-high = <0xa>; 295 adi,agc-inner-thresh-high-dec-steps = <0x1>; 296 adi,agc-inner-thresh-low = <0xc>; 297 adi,agc-inner-thresh-low-inc-steps = <0x1>; 298 adi,agc-outer-thresh-low = <0x12>; 299 adi,agc-outer-thresh-low-inc-steps = <0x2>; 300 adi,agc-adc-small-overload-exceed-counter = <0xa>; 301 adi,agc-adc-large-overload-exceed-counter = <0xa>; 302 adi,agc-adc-large-overload-inc-steps = <0x2>; 303 adi,agc-lmt-overload-large-exceed-counter = <0xa>; 304 adi,agc-lmt-overload-small-exceed-counter = <0xa>; 305 adi,agc-lmt-overload-large-inc-steps = <0x2>; 306 adi,agc-gain-update-interval-us = <0x3e8>; 307 adi,fagc-dec-pow-measurement-duration = <0x40>; 308 adi,fagc-lp-thresh-increment-steps = <0x1>; 309 adi,fagc-lp-thresh-increment-time = <0x5>; 310 adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>; 311 adi,fagc-final-overrange-count = <0x3>; 312 adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>; 313 adi,fagc-lmt-final-settling-steps = <0x1>; 314 adi,fagc-lock-level = <0xa>; 315 adi,fagc-lock-level-gain-increase-upper-limit = <0x5>; 316 adi,fagc-lock-level-lmt-gain-increase-enable; 317 adi,fagc-lpf-final-settling-steps = <0x1>; 318 adi,fagc-optimized-gain-offset = <0x5>; 319 adi,fagc-power-measurement-duration-in-state5 = <0x40>; 320 adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable; 321 adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>; 322 adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable; 323 adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>; 324 adi,fagc-rst-gla-large-adc-overload-enable; 325 adi,fagc-rst-gla-large-lmt-overload-enable; 326 adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>; 327 adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable; 328 adi,fagc-state-wait-time-ns = <0x104>; 329 adi,fagc-use-last-lock-level-for-set-gain-enable; 330 adi,rssi-restart-mode = <0x3>; 331 adi,rssi-delay = <0x1>; 332 adi,rssi-wait = <0x1>; 333 adi,rssi-duration = <0x3e8>; 334 adi,ctrl-outs-index = <0x0>; 335 adi,ctrl-outs-enable-mask = <0xff>; 336 adi,temp-sense-measurement-interval-ms = <0x3e8>; 337 adi,temp-sense-offset-signed = <0xce>; 338 adi,temp-sense-periodic-measurement-enable; 339 adi,aux-dac-manual-mode-enable; 340 adi,aux-dac1-default-value-mV = <0x0>; 341 adi,aux-dac1-rx-delay-us = <0x0>; 342 adi,aux-dac1-tx-delay-us = <0x0>; 343 adi,aux-dac2-default-value-mV = <0x0>; 344 adi,aux-dac2-rx-delay-us = <0x0>; 345 adi,aux-dac2-tx-delay-us = <0x0>; 346 en_agc-gpios = <0x09 0x62 0x0>; 347 sync-gpios = <0x09 0x63 0x0>; 348 reset-gpios = <0x09 0x64 0x0>; 349 enable-gpios = <0x09 0x65 0x0>; 350 txnrx-gpios = <0x09 0x66 0x0>; 351 phandle = <0x17>; 352 }; 353 }; 354 355 spi@e0007000 { 356 compatible = "xlnx,zynq-spi-r1p6"; 357 reg = <0xe0007000 0x1000>; 358 status = "disabled"; 359 interrupt-parent = <0x01>; 360 interrupts = <0x00 0x31 0x04>; 361 clocks = <0x02 0x1a 0x02 0x23>; 362 clock-names = "ref_clk\0pclk"; 363 #address-cells = <0x01>; 364 #size-cells = <0x00>; 365 phandle = <0x26>; 366 }; 367 368 spi@e000d000 { 369 clock-names = "ref_clk\0pclk"; 370 clocks = <0x02 0x0a 0x02 0x2b>; 371 compatible = "xlnx,zynq-qspi-1.0"; 372 status = "okay"; 373 interrupt-parent = <0x01>; 374 interrupts = <0x00 0x13 0x04>; 375 reg = <0xe000d000 0x1000>; 376 #address-cells = <0x01>; 377 #size-cells = <0x00>; 378 is-dual = <0x00>; 379 num-cs = <0x01>; 380 phandle = <0x27>; 381 382 ps7-qspi@0 { 383 #address-cells = <0x01>; 384 #size-cells = <0x01>; 385 spi-tx-bus-width = <0x01>; 386 spi-rx-bus-width = <0x04>; 387 compatible = "n25q256a\0jedec,spi-nor"; 388 reg = <0x00>; 389 spi-max-frequency = <0x2faf080>; 390 phandle = <0x28>; 391 392 partition@qspi-fsbl-uboot { 393 label = "qspi-fsbl-uboot"; 394 reg = <0x00 0xe0000>; 395 }; 396 397 partition@qspi-uboot-env { 398 label = "qspi-uboot-env"; 399 reg = <0xe0000 0x20000>; 400 }; 401 402 partition@qspi-linux { 403 label = "qspi-linux"; 404 reg = <0x100000 0x500000>; 405 }; 406 407 partition@qspi-device-tree { 408 label = "qspi-device-tree"; 409 reg = <0x600000 0x20000>; 410 }; 411 412 partition@qspi-rootfs { 413 label = "qspi-rootfs"; 414 reg = <0x620000 0xce0000>; 415 }; 416 417 partition@qspi-bitstream { 418 label = "qspi-bitstream"; 419 reg = <0x1300000 0xd00000>; 420 }; 421 }; 422 }; 423 424 memory-controller@e000e000 { 425 #address-cells = <0x01>; 426 #size-cells = <0x01>; 427 status = "disabled"; 428 clock-names = "memclk\0apb_pclk"; 429 clocks = <0x02 0x0b 0x02 0x2c>; 430 compatible = "arm,pl353-smc-r2p1\0arm,primecell"; 431 interrupt-parent = <0x01>; 432 interrupts = <0x00 0x12 0x04>; 433 ranges; 434 reg = <0xe000e000 0x1000>; 435 phandle = <0x29>; 436 437 flash@e1000000 { 438 status = "disabled"; 439 compatible = "arm,pl353-nand-r2p1"; 440 reg = <0xe1000000 0x1000000>; 441 #address-cells = <0x01>; 442 #size-cells = <0x01>; 443 phandle = <0x2a>; 444 }; 445 446 flash@e2000000 { 447 status = "disabled"; 448 compatible = "cfi-flash"; 449 reg = <0xe2000000 0x2000000>; 450 #address-cells = <0x01>; 451 #size-cells = <0x01>; 452 phandle = <0x2b>; 453 }; 454 }; 455 456 ethernet@e000b000 { 457 compatible = "cdns,zynq-gem", "cdns,gem"; 458 reg = <0xe000b000 0x1000>; 459 status = "okay"; 460 interrupts = <0x0 0x16 0x4>; 461 clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>; 462 clock-names = "pclk", "hclk", "tx_clk"; 463 #address-cells = <0x1>; 464 #size-cells = <0x0>; 465 phy-handle = <&phy0>; 466 phy-mode = "rgmii-id"; 467 xlnx,has-mdio = <0x1>; 468 gmii2rgmii-phy-handle = <&gmii_to_rgmii_0>; 469 470 phy0: phy@1 { 471 compatible = "ethernet-phy-id011c.c916"; 472 device_type = "ethernet-phy"; 473 reg = <0x1>; 474 }; 475 476 gmii_to_rgmii_0: gmiitorgmii@8 { 477 compatible = "xlnx,gmii-to-rgmii-1.0"; 478 reg = <0x8>; 479 phy-handle = <&phy0>; 480 }; 481 }; 482 483 ethernet@e000c000 { 484 compatible = "cdns,zynq-gem\0cdns,gem"; 485 reg = <0xe000c000 0x1000>; 486 status = "disabled"; 487 interrupts = <0x00 0x2d 0x04>; 488 clocks = <0x02 0x1f 0x02 0x1f 0x02 0x0e>; 489 clock-names = "pclk\0hclk\0tx_clk"; 490 #address-cells = <0x01>; 491 #size-cells = <0x00>; 492 phandle = <0x2d>; 493 }; 494 495 mmc@e0100000 { 496 compatible = "arasan,sdhci-8.9a"; 497 status = "okay"; 498 clock-names = "clk_xin\0clk_ahb"; 499 clocks = <0x02 0x15 0x02 0x20>; 500 interrupt-parent = <0x01>; 501 interrupts = <0x00 0x18 0x04>; 502 reg = <0xe0100000 0x1000>; 503 disable-wp; 504 phandle = <0x2e>; 505 }; 506 507 mmc@e0101000 { 508 compatible = "arasan,sdhci-8.9a"; 509 status = "disabled"; 510 clock-names = "clk_xin\0clk_ahb"; 511 clocks = <0x02 0x16 0x02 0x21>; 512 interrupt-parent = <0x01>; 513 interrupts = <0x00 0x2f 0x04>; 514 reg = <0xe0101000 0x1000>; 515 phandle = <0x2f>; 516 }; 517 518 slcr@f8000000 { 519 u-boot,dm-pre-reloc; 520 #address-cells = <0x01>; 521 #size-cells = <0x01>; 522 compatible = "xlnx,zynq-slcr\0syscon\0simple-mfd"; 523 reg = <0xf8000000 0x1000>; 524 ranges; 525 phandle = <0x0b>; 526 527 clkc@100 { 528 u-boot,dm-pre-reloc; 529 #clock-cells = <0x01>; 530 compatible = "xlnx,ps7-clkc"; 531 fclk-enable = <0x0f>; 532 clock-output-names = "armpll\0ddrpll\0iopll\0cpu_6or4x\0cpu_3or2x\0cpu_2x\0cpu_1x\0ddr2x\0ddr3x\0dci\0lqspi\0smc\0pcap\0gem0\0gem1\0fclk0\0fclk1\0fclk2\0fclk3\0can0\0can1\0sdio0\0sdio1\0uart0\0uart1\0spi0\0spi1\0dma\0usb0_aper\0usb1_aper\0gem0_aper\0gem1_aper\0sdio0_aper\0sdio1_aper\0spi0_aper\0spi1_aper\0can0_aper\0can1_aper\0i2c0_aper\0i2c1_aper\0uart0_aper\0uart1_aper\0gpio_aper\0lqspi_aper\0smc_aper\0swdt\0dbg_trc\0dbg_apb"; 533 reg = <0x100 0x100>; 534 ps-clk-frequency = <0x1fca055>; 535 phandle = <0x02>; 536 }; 537 538 rstc@200 { 539 compatible = "xlnx,zynq-reset"; 540 reg = <0x200 0x48>; 541 #reset-cells = <0x01>; 542 syscon = <0x0b>; 543 phandle = <0x30>; 544 }; 545 546 pinctrl@700 { 547 compatible = "xlnx,pinctrl-zynq"; 548 reg = <0x700 0x200>; 549 syscon = <0x0b>; 550 phandle = <0x31>; 551 }; 552 }; 553 554 dmac@f8003000 { 555 compatible = "arm,pl330\0arm,primecell"; 556 reg = <0xf8003000 0x1000>; 557 interrupt-parent = <0x01>; 558 interrupt-names = "abort\0dma0\0dma1\0dma2\0dma3\0dma4\0dma5\0dma6\0dma7"; 559 interrupts = <0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04>; 560 #dma-cells = <0x01>; 561 #dma-channels = <0x08>; 562 #dma-requests = <0x04>; 563 clocks = <0x02 0x1b>; 564 clock-names = "apb_pclk"; 565 phandle = <0x32>; 566 }; 567 568 devcfg@f8007000 { 569 compatible = "xlnx,zynq-devcfg-1.0"; 570 interrupt-parent = <0x01>; 571 interrupts = <0x00 0x08 0x04>; 572 reg = <0xf8007000 0x100>; 573 clocks = <0x02 0x0c 0x02 0x0f 0x02 0x10 0x02 0x11 0x02 0x12>; 574 clock-names = "ref_clk\0fclk0\0fclk1\0fclk2\0fclk3"; 575 syscon = <0x0b>; 576 phandle = <0x04>; 577 }; 578 579 efuse@f800d000 { 580 compatible = "xlnx,zynq-efuse"; 581 reg = <0xf800d000 0x20>; 582 phandle = <0x33>; 583 }; 584 585 timer@f8f00200 { 586 compatible = "arm,cortex-a9-global-timer"; 587 reg = <0xf8f00200 0x20>; 588 interrupts = <0x01 0x0b 0x301>; 589 interrupt-parent = <0x01>; 590 clocks = <0x02 0x04>; 591 phandle = <0x34>; 592 }; 593 594 timer@f8001000 { 595 interrupt-parent = <0x01>; 596 interrupts = <0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04>; 597 compatible = "cdns,ttc"; 598 clocks = <0x02 0x06>; 599 reg = <0xf8001000 0x1000>; 600 phandle = <0x35>; 601 }; 602 603 timer@f8002000 { 604 interrupt-parent = <0x01>; 605 interrupts = <0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04>; 606 compatible = "cdns,ttc"; 607 clocks = <0x02 0x06>; 608 reg = <0xf8002000 0x1000>; 609 phandle = <0x36>; 610 }; 611 612 timer@f8f00600 { 613 interrupt-parent = <0x01>; 614 interrupts = <0x01 0x0d 0x301>; 615 compatible = "arm,cortex-a9-twd-timer"; 616 reg = <0xf8f00600 0x20>; 617 clocks = <0x02 0x04>; 618 phandle = <0x37>; 619 }; 620 621 usb@e0002000 { 622 compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2"; 623 status = "okay"; 624 clocks = <0x02 0x1c>; 625 interrupt-parent = <0x01>; 626 interrupts = <0x00 0x15 0x04>; 627 reg = <0xe0002000 0x1000>; 628 phy_type = "ulpi"; 629 dr_mode = "host"; 630 xlnx,phy-reset-gpio = <0x09 0x07 0x00>; 631 phandle = <0x38>; 632 }; 633 634 usb@e0003000 { 635 compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2"; 636 status = "disabled"; 637 clocks = <0x02 0x1d>; 638 interrupt-parent = <0x01>; 639 interrupts = <0x00 0x2c 0x04>; 640 reg = <0xe0003000 0x1000>; 641 phy_type = "ulpi"; 642 phandle = <0x39>; 643 }; 644 645 watchdog@f8005000 { 646 clocks = <0x02 0x2d>; 647 compatible = "cdns,wdt-r1p2"; 648 interrupt-parent = <0x01>; 649 interrupts = <0x00 0x09 0x01>; 650 reg = <0xf8005000 0x1000>; 651 timeout-sec = <0x0a>; 652 phandle = <0x3a>; 653 }; 654 655 etb@f8801000 { 656 compatible = "arm,coresight-etb10\0arm,primecell"; 657 reg = <0xf8801000 0x1000>; 658 clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; 659 clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; 660 661 in-ports { 662 663 port { 664 665 endpoint { 666 remote-endpoint = <0x0c>; 667 phandle = <0x06>; 668 }; 669 }; 670 }; 671 }; 672 673 tpiu@f8803000 { 674 compatible = "arm,coresight-tpiu\0arm,primecell"; 675 reg = <0xf8803000 0x1000>; 676 clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; 677 clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; 678 679 in-ports { 680 681 port { 682 683 endpoint { 684 remote-endpoint = <0x0d>; 685 phandle = <0x05>; 686 }; 687 }; 688 }; 689 }; 690 691 funnel@f8804000 { 692 compatible = "arm,coresight-static-funnel\0arm,primecell"; 693 reg = <0xf8804000 0x1000>; 694 clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; 695 clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; 696 697 out-ports { 698 699 port { 700 701 endpoint { 702 remote-endpoint = <0x0e>; 703 phandle = <0x07>; 704 }; 705 }; 706 }; 707 708 in-ports { 709 #address-cells = <0x01>; 710 #size-cells = <0x00>; 711 712 port@0 { 713 reg = <0x00>; 714 715 endpoint { 716 remote-endpoint = <0x0f>; 717 phandle = <0x12>; 718 }; 719 }; 720 721 port@1 { 722 reg = <0x01>; 723 724 endpoint { 725 remote-endpoint = <0x10>; 726 phandle = <0x14>; 727 }; 728 }; 729 730 port@2 { 731 reg = <0x02>; 732 733 endpoint { 734 phandle = <0x3b>; 735 }; 736 }; 737 }; 738 }; 739 740 ptm@f889c000 { 741 compatible = "arm,coresight-etm3x\0arm,primecell"; 742 reg = <0xf889c000 0x1000>; 743 clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; 744 clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; 745 cpu = <0x11>; 746 747 out-ports { 748 749 port { 750 751 endpoint { 752 remote-endpoint = <0x12>; 753 phandle = <0x0f>; 754 }; 755 }; 756 }; 757 }; 758 759 ptm@f889d000 { 760 compatible = "arm,coresight-etm3x\0arm,primecell"; 761 reg = <0xf889d000 0x1000>; 762 clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; 763 clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; 764 cpu = <0x13>; 765 766 out-ports { 767 768 port { 769 770 endpoint { 771 remote-endpoint = <0x14>; 772 phandle = <0x10>; 773 }; 774 }; 775 }; 776 }; 777 }; 778 779 aliases { 780 ethernet0 = "/axi/ethernet@e000b000"; 781 serial0 = "/axi/serial@e0001000"; 782 phandle = <0x3c>; 783 }; 784 785 memory { 786 device_type = "memory"; 787 reg = <0x00 0x40000000>; 788 }; 789 790 chosen { 791 stdout-path = "/amba@0/uart@E0001000"; 792 }; 793 794 clocks { 795 796 clock@0 { 797 #clock-cells = <0x00>; 798 compatible = "adjustable-clock"; 799 clock-frequency = <0x2625a00>; 800 clock-accuracy = <0x30d40>; 801 clock-output-names = "ad9364_ext_refclk"; 802 phandle = <0x08>; 803 }; 804 805 clock@1 { 806 #clock-cells = <0x00>; 807 compatible = "fixed-clock"; 808 clock-frequency = <0x16e3600>; 809 clock-output-names = "24MHz"; 810 phandle = <0x15>; 811 }; 812 }; 813 814 usb-ulpi-gpio-gate@0 { 815 compatible = "gpio-gate-clock"; 816 clocks = <0x15>; 817 #clock-cells = <0x00>; 818 enable-gpios = <0x09 0x09 0x01>; 819 phandle = <0x3d>; 820 }; 821 822 fpga-axi@0 { 823 compatible = "simple-bus"; 824 #address-cells = <0x01>; 825 #size-cells = <0x01>; 826 ranges; 827 phandle = <0x3e>; 828 829 i2c@41600000 { 830 compatible = "xlnx,axi-iic-1.02.a\0xlnx,xps-iic-2.00.a"; 831 reg = <0x41600000 0x10000>; 832 interrupt-parent = <0x01>; 833 interrupts = <0x00 0x3a 0x04>; 834 clocks = <0x02 0x0f>; 835 clock-names = "pclk"; 836 #address-cells = <0x01>; 837 #size-cells = <0x00>; 838 phandle = <0x3f>; 839 840 ad7291@20 { 841 compatible = "adi,ad7291"; 842 reg = <0x20>; 843 }; 844 845 ad7291-bob@2C { 846 compatible = "adi,ad7291"; 847 reg = <0x2c>; 848 }; 849 850 eeprom@50 { 851 compatible = "at24,24c32"; 852 reg = <0x50>; 853 }; 854 }; 855 856 // dma@7c400000 { 857 // compatible = "adi,axi-dmac-1.00.a"; 858 // reg = <0x7c400000 0x10000>; 859 // #dma-cells = <0x01>; 860 // interrupts = <0x00 0x39 0x04>; 861 // clocks = <0x02 0x10>; 862 // phandle = <0x16>; 863 864 // adi,channels { 865 // #size-cells = <0x00>; 866 // #address-cells = <0x01>; 867 868 // dma-channel@0 { 869 // reg = <0x00>; 870 // adi,source-bus-width = <0x40>; 871 // adi,source-bus-type = <0x02>; 872 // adi,destination-bus-width = <0x40>; 873 // adi,destination-bus-type = <0x00>; 874 // }; 875 // }; 876 // }; 877 878 // dma@7c420000 { 879 // compatible = "adi,axi-dmac-1.00.a"; 880 // reg = <0x7c420000 0x10000>; 881 // #dma-cells = <0x01>; 882 // interrupts = <0x00 0x38 0x04>; 883 // clocks = <0x02 0x10>; 884 // phandle = <0x18>; 885 886 // adi,channels { 887 // #size-cells = <0x00>; 888 // #address-cells = <0x01>; 889 890 // dma-channel@0 { 891 // reg = <0x00>; 892 // adi,source-bus-width = <0x40>; 893 // adi,source-bus-type = <0x00>; 894 // adi,destination-bus-width = <0x40>; 895 // adi,destination-bus-type = <0x02>; 896 // }; 897 // }; 898 // }; 899 900 sdr: sdr { 901 compatible ="sdr,sdr"; 902 dmas = <&rx_dma 1 903 &tx_dma 0>; 904 dma-names = "rx_dma_s2mm", "tx_dma_mm2s"; 905 interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt"; 906 interrupt-parent = <1>; 907 interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>; 908 } ; 909 910 // axidmatest_1: axidmatest@1 { 911 // compatible ="xlnx,axi-dma-test-1.00.a"; 912 // dmas = <&rx_dma 0 913 // &rx_dma 1>; 914 // dma-names = "axidma0", "axidma1"; 915 // } ; 916 917 tx_dma: dma@80400000 { 918 #dma-cells = <1>; 919 clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; 920 clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 921 compatible = "xlnx,axi-dma-1.00.a"; 922 interrupt-names = "mm2s_introut", "s2mm_introut"; 923 interrupt-parent = <1>; 924 interrupts = <0 35 4 0 36 4>; 925 reg = <0x80400000 0x10000>; 926 xlnx,addrwidth = <0x20>; 927 xlnx,include-sg ; 928 xlnx,sg-length-width = <0xe>; 929 dma-channel@80400000 { 930 compatible = "xlnx,axi-dma-mm2s-channel"; 931 dma-channels = <0x1>; 932 interrupts = <0 35 4>; 933 xlnx,datawidth = <0x40>; 934 xlnx,device-id = <0x0>; 935 }; 936 dma-channel@80400030 { 937 compatible = "xlnx,axi-dma-s2mm-channel"; 938 dma-channels = <0x1>; 939 interrupts = <0 36 4>; 940 xlnx,datawidth = <0x40>; 941 xlnx,device-id = <0x0>; 942 }; 943 }; 944 945 rx_dma: dma@80410000 { 946 #dma-cells = <1>; 947 clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; 948 clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 949 compatible = "xlnx,axi-dma-1.00.a"; 950 //dma-coherent ; 951 interrupt-names = "mm2s_introut", "s2mm_introut"; 952 interrupt-parent = <1>; 953 interrupts = <0 31 4 0 32 4>; 954 reg = <0x80410000 0x10000>; 955 xlnx,addrwidth = <0x20>; 956 xlnx,include-sg ; 957 xlnx,sg-length-width = <0xe>; 958 dma-channel@80410000 { 959 compatible = "xlnx,axi-dma-mm2s-channel"; 960 dma-channels = <0x1>; 961 interrupts = <0 31 4>; 962 xlnx,datawidth = <0x40>; 963 xlnx,device-id = <0x1>; 964 }; 965 dma-channel@80410030 { 966 compatible = "xlnx,axi-dma-s2mm-channel"; 967 dma-channels = <0x1>; 968 interrupts = <0 32 4>; 969 xlnx,datawidth = <0x40>; 970 xlnx,device-id = <0x1>; 971 }; 972 }; 973 974 tx_intf_0: tx_intf@83c00000 { 975 clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk"; 976 clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>; 977 compatible = "sdr,tx_intf"; 978 interrupt-names = "tx_itrpt"; 979 interrupt-parent = <1>; 980 interrupts = <0 34 1>; 981 reg = <0x83c00000 0x10000>; 982 xlnx,s00-axi-addr-width = <0x7>; 983 xlnx,s00-axi-data-width = <0x20>; 984 }; 985 986 rx_intf_0: rx_intf@83c20000 { 987 clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk"; 988 clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>; 989 compatible = "sdr,rx_intf"; 990 interrupt-names = "not_valid_anymore", "rx_pkt_intr"; 991 interrupt-parent = <1>; 992 interrupts = <0 29 1 0 30 1>; 993 reg = <0x83c20000 0x10000>; 994 xlnx,s00-axi-addr-width = <0x7>; 995 xlnx,s00-axi-data-width = <0x20>; 996 }; 997 998 openofdm_tx_0: openofdm_tx@83c10000 { 999 clock-names = "clk"; 1000 clocks = <0x2 0x11>; 1001 compatible = "sdr,openofdm_tx"; 1002 reg = <0x83c10000 0x10000>; 1003 }; 1004 1005 openofdm_rx_0: openofdm_rx@83c30000 { 1006 clock-names = "clk"; 1007 clocks = <0x2 0x11>; 1008 compatible = "sdr,openofdm_rx"; 1009 reg = <0x83c30000 0x10000>; 1010 }; 1011 1012 xpu_0: xpu@83c40000 { 1013 clock-names = "s00_axi_aclk"; 1014 clocks = <0x2 0x11>; 1015 compatible = "sdr,xpu"; 1016 reg = <0x83c40000 0x10000>; 1017 }; 1018 1019 side_ch_0: side_ch@83c50000 { 1020 clock-names = "s00_axi_aclk"; 1021 clocks = <0x2 0x11>; 1022 compatible = "sdr,side_ch"; 1023 reg = <0x83c50000 0x10000>; 1024 dmas = <&rx_dma 0 1025 &tx_dma 1>; 1026 dma-names = "rx_dma_mm2s", "tx_dma_s2mm"; 1027 }; 1028 1029 cf-ad9361-lpc@79020000 { 1030 compatible = "adi,axi-ad9361-6.00.a"; 1031 reg = <0x79020000 0x6000>; 1032 // dmas = <0x16 0x00>; 1033 // dma-names = "rx"; 1034 spibus-connected = <0x17>; 1035 phandle = <0x40>; 1036 }; 1037 1038 cf-ad9361-dds-core-lpc@79024000 { 1039 compatible = "adi,axi-ad9361-dds-6.00.a"; 1040 reg = <0x79024000 0x1000>; 1041 clocks = <0x17 0x0d>; 1042 clock-names = "sampl_clk"; 1043 // dmas = <0x18 0x00>; 1044 // dma-names = "tx"; 1045 phandle = <0x41>; 1046 }; 1047 1048 mwipcore@43c00000 { 1049 compatible = "mathworks,mwipcore-axi4lite-v1.00"; 1050 reg = <0x43c00000 0xffff>; 1051 }; 1052 1053 // axi-sysid-0@45000000 { 1054 // compatible = "adi,axi-sysid-1.00.a"; 1055 // reg = <0x45000000 0x10000>; 1056 // phandle = <0x42>; 1057 // }; 1058 }; 1059 1060 leds { 1061 compatible = "gpio-leds"; 1062 1063 led0 { 1064 label = "led0:green"; 1065 gpios = <0x09 0x15 0>; 1066 linux,default-trigger = "heartbeat"; 1067 }; 1068 1069 }; 1070 1071 1072}; 1073