xref: /openwifi/kernel_boot/boards/e310v2/devicetree.dts (revision a47b55e6cafa759d041cd8d309e454edc8a51770)

/dts-v1/;

/ {
	#address-cells = <0x01>;
	#size-cells = <0x01>;
	compatible = "xlnx,zynq-7000";
	interrupt-parent = <0x01>;
	model = "ANTSDR-E310V2";

	cpus {
		#address-cells = <0x01>;
		#size-cells = <0x00>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x00>;
			clocks = <0x02 0x03>;
			clock-latency = <0x3e8>;
			cpu0-supply = <0x03>;
			operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;
			phandle = <0x11>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x01>;
			clocks = <0x02 0x03>;
			phandle = <0x13>;
		};
	};

	fpga-full {
		compatible = "fpga-region";
		fpga-mgr = <0x04>;
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		ranges;
		phandle = <0x19>;
	};

	pmu@f8891000 {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0x00 0x05 0x04 0x00 0x06 0x04>;
		interrupt-parent = <0x01>;
		reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
	};

	fixedregulator {
		compatible = "regulator-fixed";
		regulator-name = "VCCPINT";
		regulator-min-microvolt = <0xf4240>;
		regulator-max-microvolt = <0xf4240>;
		regulator-boot-on;
		regulator-always-on;
		phandle = <0x03>;
	};

	replicator {
		compatible = "arm,coresight-static-replicator";
		clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
		clock-names = "apb_pclk\0dbg_trc\0dbg_apb";

		out-ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;

				endpoint {
					remote-endpoint = <0x05>;
					phandle = <0x0d>;
				};
			};

			port@1 {
				reg = <0x01>;

				endpoint {
					remote-endpoint = <0x06>;
					phandle = <0x0c>;
				};
			};
		};

		in-ports {

			port {

				endpoint {
					remote-endpoint = <0x07>;
					phandle = <0x0e>;
				};
			};
		};
	};

	axi {
		u-boot,dm-pre-reloc;
		compatible = "simple-bus";
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		interrupt-parent = <0x01>;
		ranges;
		phandle = <0x1a>;

		adc@f8007100 {
			compatible = "xlnx,zynq-xadc-1.00.a";
			reg = <0xf8007100 0x20>;
			interrupts = <0x00 0x07 0x04>;
			interrupt-parent = <0x01>;
			clocks = <0x02 0x0c>;
			phandle = <0x1b>;
		};

		can@e0008000 {
			compatible = "xlnx,zynq-can-1.0";
			status = "disabled";
			clocks = <0x02 0x13 0x02 0x24>;
			clock-names = "can_clk\0pclk";
			reg = <0xe0008000 0x1000>;
			interrupts = <0x00 0x1c 0x04>;
			interrupt-parent = <0x01>;
			tx-fifo-depth = <0x40>;
			rx-fifo-depth = <0x40>;
			phandle = <0x1c>;
		};

		can@e0009000 {
			compatible = "xlnx,zynq-can-1.0";
			status = "disabled";
			clocks = <0x02 0x14 0x02 0x25>;
			clock-names = "can_clk\0pclk";
			reg = <0xe0009000 0x1000>;
			interrupts = <0x00 0x33 0x04>;
			interrupt-parent = <0x01>;
			tx-fifo-depth = <0x40>;
			rx-fifo-depth = <0x40>;
			phandle = <0x1d>;
		};

		gpio@e000a000 {
			compatible = "xlnx,zynq-gpio-1.0";
			#gpio-cells = <0x02>;
			clocks = <0x02 0x2a>;
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x14 0x04>;
			reg = <0xe000a000 0x1000>;
			phandle = <0x09>;
		};

		i2c@e0004000 {
			compatible = "cdns,i2c-r1p10";
			status = "disabled";
			clocks = <0x02 0x26>;
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x19 0x04>;
			reg = <0xe0004000 0x1000>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			phandle = <0x1e>;
		};

		i2c@e0005000 {
			compatible = "cdns,i2c-r1p10";
			status = "disabled";
			clocks = <0x02 0x27>;
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x30 0x04>;
			reg = <0xe0005000 0x1000>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			phandle = <0x1f>;
		};

		interrupt-controller@f8f01000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <0x03>;
			interrupt-controller;
			reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
			phandle = <0x01>;
		};

		cache-controller@f8f02000 {
			compatible = "arm,pl310-cache";
			reg = <0xf8f02000 0x1000>;
			interrupts = <0x00 0x02 0x04>;
			arm,data-latency = <0x03 0x02 0x02>;
			arm,tag-latency = <0x02 0x02 0x02>;
			cache-unified;
			cache-level = <0x02>;
			phandle = <0x20>;
		};

		memory-controller@f8006000 {
			compatible = "xlnx,zynq-ddrc-a05";
			reg = <0xf8006000 0x1000>;
			phandle = <0x21>;
		};

		ocmc@f800c000 {
			compatible = "xlnx,zynq-ocmc-1.0";
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x03 0x04>;
			reg = <0xf800c000 0x1000>;
			phandle = <0x22>;
		};

		serial@e0000000 {
			compatible = "xlnx,xuartps\0cdns,uart-r1p8";
			status = "disabled";
			clocks = <0x02 0x17 0x02 0x28>;
			clock-names = "uart_clk\0pclk";
			reg = <0xe0000000 0x1000>;
			interrupts = <0x00 0x1b 0x04>;
			phandle = <0x23>;
		};

		serial@e0001000 {
			compatible = "xlnx,xuartps\0cdns,uart-r1p8";
			status = "okay";
			clocks = <0x02 0x18 0x02 0x29>;
			clock-names = "uart_clk\0pclk";
			reg = <0xe0001000 0x1000>;
			interrupts = <0x00 0x32 0x04>;
			phandle = <0x24>;
		};

		spi@e0006000 {
			compatible = "xlnx,zynq-spi-r1p6";
			reg = <0xe0006000 0x1000>;
			status = "okay";
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x1a 0x04>;
			clocks = <0x02 0x19 0x02 0x22>;
			clock-names = "ref_clk\0pclk";
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			phandle = <0x25>;

			ad9361-phy@0 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				#clock-cells = <0x1>;
				compatible = "adi,ad9361";
				reg = <0x0>;
				spi-cpha;
				spi-max-frequency = <0x989680>;
				clocks = <0x08 0x00>;
				clock-names = "ad9361_ext_refclk";
				clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
				adi,digital-interface-tune-skip-mode = <0x0>;
				adi,pp-tx-swap-enable;
				adi,pp-rx-swap-enable;
				adi,rx-frame-pulse-mode-enable;
				adi,lvds-mode-enable;
				adi,lvds-bias-mV = <0x96>;
				adi,lvds-rx-onchip-termination-enable;
				adi,rx-data-delay = <0x4>;
				adi,tx-fb-clock-delay = <0x7>;
				adi,xo-disable-use-ext-refclk-enable;
				adi,2rx-2tx-mode-enable;
				adi,frequency-division-duplex-mode-enable;
				adi,rx-rf-port-input-select = <0x0>;
				adi,tx-rf-port-input-select = <0x0>;
				adi,tx-attenuation-mdB = <0x2710>;
				adi,tx-lo-powerdown-managed-enable;
				adi,rf-rx-bandwidth-hz = <0x112a880>;
				adi,rf-tx-bandwidth-hz = <0x112a880>;
				adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
				adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
				adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
				adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
				adi,gc-rx1-mode = <0x2>;
				adi,gc-rx2-mode = <0x2>;
				adi,gc-adc-ovr-sample-size = <0x4>;
				adi,gc-adc-small-overload-thresh = <0x2f>;
				adi,gc-adc-large-overload-thresh = <0x3a>;
				adi,gc-lmt-overload-high-thresh = <0x320>;
				adi,gc-lmt-overload-low-thresh = <0x2c0>;
				adi,gc-dec-pow-measurement-duration = <0x2000>;
				adi,gc-low-power-thresh = <0x18>;
				adi,mgc-inc-gain-step = <0x2>;
				adi,mgc-dec-gain-step = <0x2>;
				adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
				adi,agc-attack-delay-extra-margin-us = <0x1>;
				adi,agc-outer-thresh-high = <0x5>;
				adi,agc-outer-thresh-high-dec-steps = <0x2>;
				adi,agc-inner-thresh-high = <0xa>;
				adi,agc-inner-thresh-high-dec-steps = <0x1>;
				adi,agc-inner-thresh-low = <0xc>;
				adi,agc-inner-thresh-low-inc-steps = <0x1>;
				adi,agc-outer-thresh-low = <0x12>;
				adi,agc-outer-thresh-low-inc-steps = <0x2>;
				adi,agc-adc-small-overload-exceed-counter = <0xa>;
				adi,agc-adc-large-overload-exceed-counter = <0xa>;
				adi,agc-adc-large-overload-inc-steps = <0x2>;
				adi,agc-lmt-overload-large-exceed-counter = <0xa>;
				adi,agc-lmt-overload-small-exceed-counter = <0xa>;
				adi,agc-lmt-overload-large-inc-steps = <0x2>;
				adi,agc-gain-update-interval-us = <0x3e8>;
				adi,fagc-dec-pow-measurement-duration = <0x40>;
				adi,fagc-lp-thresh-increment-steps = <0x1>;
				adi,fagc-lp-thresh-increment-time = <0x5>;
				adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
				adi,fagc-final-overrange-count = <0x3>;
				adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
				adi,fagc-lmt-final-settling-steps = <0x1>;
				adi,fagc-lock-level = <0xa>;
				adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
				adi,fagc-lock-level-lmt-gain-increase-enable;
				adi,fagc-lpf-final-settling-steps = <0x1>;
				adi,fagc-optimized-gain-offset = <0x5>;
				adi,fagc-power-measurement-duration-in-state5 = <0x40>;
				adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
				adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
				adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
				adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
				adi,fagc-rst-gla-large-adc-overload-enable;
				adi,fagc-rst-gla-large-lmt-overload-enable;
				adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
				adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
				adi,fagc-state-wait-time-ns = <0x104>;
				adi,fagc-use-last-lock-level-for-set-gain-enable;
				adi,rssi-restart-mode = <0x3>;
				adi,rssi-delay = <0x1>;
				adi,rssi-wait = <0x1>;
				adi,rssi-duration = <0x3e8>;
				adi,ctrl-outs-index = <0x0>;
				adi,ctrl-outs-enable-mask = <0xff>;
				adi,temp-sense-measurement-interval-ms = <0x3e8>;
				adi,temp-sense-offset-signed = <0xce>;
				adi,temp-sense-periodic-measurement-enable;
				adi,aux-dac-manual-mode-enable;
				adi,aux-dac1-default-value-mV = <0x0>;
				adi,aux-dac1-rx-delay-us = <0x0>;
				adi,aux-dac1-tx-delay-us = <0x0>;
				adi,aux-dac2-default-value-mV = <0x0>;
				adi,aux-dac2-rx-delay-us = <0x0>;
				adi,aux-dac2-tx-delay-us = <0x0>;
				en_agc-gpios = <0x09 0x62 0x0>;
				sync-gpios = <0x09 0x63 0x0>;
				reset-gpios = <0x09 0x64 0x0>;
				enable-gpios = <0x09 0x65 0x0>;
				txnrx-gpios = <0x09 0x66 0x0>;
				phandle = <0x17>;
			};
		};

		spi@e0007000 {
			compatible = "xlnx,zynq-spi-r1p6";
			reg = <0xe0007000 0x1000>;
			status = "disabled";
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x31 0x04>;
			clocks = <0x02 0x1a 0x02 0x23>;
			clock-names = "ref_clk\0pclk";
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			phandle = <0x26>;
		};

		spi@e000d000 {
			clock-names = "ref_clk\0pclk";
			clocks = <0x02 0x0a 0x02 0x2b>;
			compatible = "xlnx,zynq-qspi-1.0";
			status = "okay";
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x13 0x04>;
			reg = <0xe000d000 0x1000>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			is-dual = <0x00>;
			num-cs = <0x01>;
			phandle = <0x27>;

			ps7-qspi@0 {
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				spi-tx-bus-width = <0x01>;
				spi-rx-bus-width = <0x04>;
				compatible = "n25q256a\0jedec,spi-nor";
				reg = <0x00>;
				spi-max-frequency = <0x2faf080>;
				phandle = <0x28>;

				partition@qspi-fsbl-uboot {
					label = "qspi-fsbl-uboot";
					reg = <0x00 0xe0000>;
				};

				partition@qspi-uboot-env {
					label = "qspi-uboot-env";
					reg = <0xe0000 0x20000>;
				};

				partition@qspi-linux {
					label = "qspi-linux";
					reg = <0x100000 0x500000>;
				};

				partition@qspi-device-tree {
					label = "qspi-device-tree";
					reg = <0x600000 0x20000>;
				};

				partition@qspi-rootfs {
					label = "qspi-rootfs";
					reg = <0x620000 0xce0000>;
				};

				partition@qspi-bitstream {
					label = "qspi-bitstream";
					reg = <0x1300000 0xd00000>;
				};
			};
		};

		memory-controller@e000e000 {
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			status = "disabled";
			clock-names = "memclk\0apb_pclk";
			clocks = <0x02 0x0b 0x02 0x2c>;
			compatible = "arm,pl353-smc-r2p1\0arm,primecell";
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x12 0x04>;
			ranges;
			reg = <0xe000e000 0x1000>;
			phandle = <0x29>;

			flash@e1000000 {
				status = "disabled";
				compatible = "arm,pl353-nand-r2p1";
				reg = <0xe1000000 0x1000000>;
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				phandle = <0x2a>;
			};

			flash@e2000000 {
				status = "disabled";
				compatible = "cfi-flash";
				reg = <0xe2000000 0x2000000>;
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				phandle = <0x2b>;
			};
		};

		ethernet@e000b000 {
			compatible = "cdns,zynq-gem", "cdns,gem";
			reg = <0xe000b000 0x1000>;
			status = "okay";
			interrupts = <0x0 0x16 0x4>;
			clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;
			clock-names = "pclk", "hclk", "tx_clk";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			phy-handle = <&phy0>;
			phy-mode = "rgmii-id";
			xlnx,has-mdio = <0x1>;
			gmii2rgmii-phy-handle = <&gmii_to_rgmii_0>;

			phy0: phy@1 {
				compatible = "ethernet-phy-id011c.c916";
				device_type = "ethernet-phy";
				reg = <0x1>;
			};

			gmii_to_rgmii_0:  gmiitorgmii@8 {
				compatible = "xlnx,gmii-to-rgmii-1.0";
				reg = <0x8>;
				phy-handle = <&phy0>;
			};
		};

		ethernet@e000c000 {
			compatible = "cdns,zynq-gem\0cdns,gem";
			reg = <0xe000c000 0x1000>;
			status = "disabled";
			interrupts = <0x00 0x2d 0x04>;
			clocks = <0x02 0x1f 0x02 0x1f 0x02 0x0e>;
			clock-names = "pclk\0hclk\0tx_clk";
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			phandle = <0x2d>;
		};

		mmc@e0100000 {
			compatible = "arasan,sdhci-8.9a";
			status = "okay";
			clock-names = "clk_xin\0clk_ahb";
			clocks = <0x02 0x15 0x02 0x20>;
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x18 0x04>;
			reg = <0xe0100000 0x1000>;
			disable-wp;
			phandle = <0x2e>;
		};

		mmc@e0101000 {
			compatible = "arasan,sdhci-8.9a";
			status = "disabled";
			clock-names = "clk_xin\0clk_ahb";
			clocks = <0x02 0x16 0x02 0x21>;
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x2f 0x04>;
			reg = <0xe0101000 0x1000>;
			phandle = <0x2f>;
		};

		slcr@f8000000 {
			u-boot,dm-pre-reloc;
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			compatible = "xlnx,zynq-slcr\0syscon\0simple-mfd";
			reg = <0xf8000000 0x1000>;
			ranges;
			phandle = <0x0b>;

			clkc@100 {
				u-boot,dm-pre-reloc;
				#clock-cells = <0x01>;
				compatible = "xlnx,ps7-clkc";
				fclk-enable = <0x0f>;
				clock-output-names = "armpll\0ddrpll\0iopll\0cpu_6or4x\0cpu_3or2x\0cpu_2x\0cpu_1x\0ddr2x\0ddr3x\0dci\0lqspi\0smc\0pcap\0gem0\0gem1\0fclk0\0fclk1\0fclk2\0fclk3\0can0\0can1\0sdio0\0sdio1\0uart0\0uart1\0spi0\0spi1\0dma\0usb0_aper\0usb1_aper\0gem0_aper\0gem1_aper\0sdio0_aper\0sdio1_aper\0spi0_aper\0spi1_aper\0can0_aper\0can1_aper\0i2c0_aper\0i2c1_aper\0uart0_aper\0uart1_aper\0gpio_aper\0lqspi_aper\0smc_aper\0swdt\0dbg_trc\0dbg_apb";
				reg = <0x100 0x100>;
				ps-clk-frequency = <0x1fca055>;
				phandle = <0x02>;
			};

			rstc@200 {
				compatible = "xlnx,zynq-reset";
				reg = <0x200 0x48>;
				#reset-cells = <0x01>;
				syscon = <0x0b>;
				phandle = <0x30>;
			};

			pinctrl@700 {
				compatible = "xlnx,pinctrl-zynq";
				reg = <0x700 0x200>;
				syscon = <0x0b>;
				phandle = <0x31>;
			};
		};

		dmac@f8003000 {
			compatible = "arm,pl330\0arm,primecell";
			reg = <0xf8003000 0x1000>;
			interrupt-parent = <0x01>;
			interrupt-names = "abort\0dma0\0dma1\0dma2\0dma3\0dma4\0dma5\0dma6\0dma7";
			interrupts = <0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04>;
			#dma-cells = <0x01>;
			#dma-channels = <0x08>;
			#dma-requests = <0x04>;
			clocks = <0x02 0x1b>;
			clock-names = "apb_pclk";
			phandle = <0x32>;
		};

		devcfg@f8007000 {
			compatible = "xlnx,zynq-devcfg-1.0";
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x08 0x04>;
			reg = <0xf8007000 0x100>;
			clocks = <0x02 0x0c 0x02 0x0f 0x02 0x10 0x02 0x11 0x02 0x12>;
			clock-names = "ref_clk\0fclk0\0fclk1\0fclk2\0fclk3";
			syscon = <0x0b>;
			phandle = <0x04>;
		};

		efuse@f800d000 {
			compatible = "xlnx,zynq-efuse";
			reg = <0xf800d000 0x20>;
			phandle = <0x33>;
		};

		timer@f8f00200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0xf8f00200 0x20>;
			interrupts = <0x01 0x0b 0x301>;
			interrupt-parent = <0x01>;
			clocks = <0x02 0x04>;
			phandle = <0x34>;
		};

		timer@f8001000 {
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04>;
			compatible = "cdns,ttc";
			clocks = <0x02 0x06>;
			reg = <0xf8001000 0x1000>;
			phandle = <0x35>;
		};

		timer@f8002000 {
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04>;
			compatible = "cdns,ttc";
			clocks = <0x02 0x06>;
			reg = <0xf8002000 0x1000>;
			phandle = <0x36>;
		};

		timer@f8f00600 {
			interrupt-parent = <0x01>;
			interrupts = <0x01 0x0d 0x301>;
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xf8f00600 0x20>;
			clocks = <0x02 0x04>;
			phandle = <0x37>;
		};

		usb@e0002000 {
			compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2";
			status = "okay";
			clocks = <0x02 0x1c>;
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x15 0x04>;
			reg = <0xe0002000 0x1000>;
			phy_type = "ulpi";
			dr_mode = "host";
			xlnx,phy-reset-gpio = <0x09 0x07 0x00>;
			phandle = <0x38>;
		};

		usb@e0003000 {
			compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2";
			status = "disabled";
			clocks = <0x02 0x1d>;
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x2c 0x04>;
			reg = <0xe0003000 0x1000>;
			phy_type = "ulpi";
			phandle = <0x39>;
		};

		watchdog@f8005000 {
			clocks = <0x02 0x2d>;
			compatible = "cdns,wdt-r1p2";
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x09 0x01>;
			reg = <0xf8005000 0x1000>;
			timeout-sec = <0x0a>;
			phandle = <0x3a>;
		};

		etb@f8801000 {
			compatible = "arm,coresight-etb10\0arm,primecell";
			reg = <0xf8801000 0x1000>;
			clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
			clock-names = "apb_pclk\0dbg_trc\0dbg_apb";

			in-ports {

				port {

					endpoint {
						remote-endpoint = <0x0c>;
						phandle = <0x06>;
					};
				};
			};
		};

		tpiu@f8803000 {
			compatible = "arm,coresight-tpiu\0arm,primecell";
			reg = <0xf8803000 0x1000>;
			clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
			clock-names = "apb_pclk\0dbg_trc\0dbg_apb";

			in-ports {

				port {

					endpoint {
						remote-endpoint = <0x0d>;
						phandle = <0x05>;
					};
				};
			};
		};

		funnel@f8804000 {
			compatible = "arm,coresight-static-funnel\0arm,primecell";
			reg = <0xf8804000 0x1000>;
			clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
			clock-names = "apb_pclk\0dbg_trc\0dbg_apb";

			out-ports {

				port {

					endpoint {
						remote-endpoint = <0x0e>;
						phandle = <0x07>;
					};
				};
			};

			in-ports {
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				port@0 {
					reg = <0x00>;

					endpoint {
						remote-endpoint = <0x0f>;
						phandle = <0x12>;
					};
				};

				port@1 {
					reg = <0x01>;

					endpoint {
						remote-endpoint = <0x10>;
						phandle = <0x14>;
					};
				};

				port@2 {
					reg = <0x02>;

					endpoint {
						phandle = <0x3b>;
					};
				};
			};
		};

		ptm@f889c000 {
			compatible = "arm,coresight-etm3x\0arm,primecell";
			reg = <0xf889c000 0x1000>;
			clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
			clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
			cpu = <0x11>;

			out-ports {

				port {

					endpoint {
						remote-endpoint = <0x12>;
						phandle = <0x0f>;
					};
				};
			};
		};

		ptm@f889d000 {
			compatible = "arm,coresight-etm3x\0arm,primecell";
			reg = <0xf889d000 0x1000>;
			clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
			clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
			cpu = <0x13>;

			out-ports {

				port {

					endpoint {
						remote-endpoint = <0x14>;
						phandle = <0x10>;
					};
				};
			};
		};
	};

	aliases {
		ethernet0 = "/axi/ethernet@e000b000";
		serial0 = "/axi/serial@e0001000";
		phandle = <0x3c>;
	};

	memory {
		device_type = "memory";
		reg = <0x00 0x40000000>;
	};

	chosen {
		stdout-path = "/amba@0/uart@E0001000";
	};

	clocks {

		clock@0 {
			#clock-cells = <0x00>;
			compatible = "adjustable-clock";
			clock-frequency = <0x2625a00>;
			clock-accuracy = <0x30d40>;
			clock-output-names = "ad9364_ext_refclk";
			phandle = <0x08>;
		};

		clock@1 {
			#clock-cells = <0x00>;
			compatible = "fixed-clock";
			clock-frequency = <0x16e3600>;
			clock-output-names = "24MHz";
			phandle = <0x15>;
		};
	};

	usb-ulpi-gpio-gate@0 {
		compatible = "gpio-gate-clock";
		clocks = <0x15>;
		#clock-cells = <0x00>;
		enable-gpios = <0x09 0x09 0x01>;
		phandle = <0x3d>;
	};

	fpga-axi@0 {
		compatible = "simple-bus";
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		ranges;
		phandle = <0x3e>;

		i2c@41600000 {
			compatible = "xlnx,axi-iic-1.02.a\0xlnx,xps-iic-2.00.a";
			reg = <0x41600000 0x10000>;
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x3a 0x04>;
			clocks = <0x02 0x0f>;
			clock-names = "pclk";
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			phandle = <0x3f>;

			ad7291@20 {
				compatible = "adi,ad7291";
				reg = <0x20>;
			};

			ad7291-bob@2C {
				compatible = "adi,ad7291";
				reg = <0x2c>;
			};

			eeprom@50 {
				compatible = "at24,24c32";
				reg = <0x50>;
			};
		};

		// dma@7c400000 {
		// 	compatible = "adi,axi-dmac-1.00.a";
		// 	reg = <0x7c400000 0x10000>;
		// 	#dma-cells = <0x01>;
		// 	interrupts = <0x00 0x39 0x04>;
		// 	clocks = <0x02 0x10>;
		// 	phandle = <0x16>;

		// 	adi,channels {
		// 		#size-cells = <0x00>;
		// 		#address-cells = <0x01>;

		// 		dma-channel@0 {
		// 			reg = <0x00>;
		// 			adi,source-bus-width = <0x40>;
		// 			adi,source-bus-type = <0x02>;
		// 			adi,destination-bus-width = <0x40>;
		// 			adi,destination-bus-type = <0x00>;
		// 		};
		// 	};
		// };

		// dma@7c420000 {
		// 	compatible = "adi,axi-dmac-1.00.a";
		// 	reg = <0x7c420000 0x10000>;
		// 	#dma-cells = <0x01>;
		// 	interrupts = <0x00 0x38 0x04>;
		// 	clocks = <0x02 0x10>;
		// 	phandle = <0x18>;

		// 	adi,channels {
		// 		#size-cells = <0x00>;
		// 		#address-cells = <0x01>;

		// 		dma-channel@0 {
		// 			reg = <0x00>;
		// 			adi,source-bus-width = <0x40>;
		// 			adi,source-bus-type = <0x00>;
		// 			adi,destination-bus-width = <0x40>;
		// 			adi,destination-bus-type = <0x02>;
		// 		};
		// 	};
		// };

		sdr: sdr {
			compatible ="sdr,sdr";
			dmas = <&rx_dma 1
					&tx_dma 0>;
			dma-names = "rx_dma_s2mm", "tx_dma_mm2s";
			interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt";
			interrupt-parent = <1>;
			interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;
		} ;

		// axidmatest_1: axidmatest@1 {
		// 	compatible ="xlnx,axi-dma-test-1.00.a";
		// 	dmas = <&rx_dma 0
		// 		&rx_dma 1>;
		// 	dma-names = "axidma0", "axidma1";
		// } ;

		tx_dma: dma@80400000 {
			#dma-cells = <1>;
			clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
			clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
			compatible = "xlnx,axi-dma-1.00.a";
			interrupt-names = "mm2s_introut", "s2mm_introut";
			interrupt-parent = <1>;
			interrupts = <0 35 4 0 36 4>;
			reg = <0x80400000 0x10000>;
			xlnx,addrwidth = <0x20>;
			xlnx,include-sg ;
			xlnx,sg-length-width = <0xe>;
			dma-channel@80400000 {
				compatible = "xlnx,axi-dma-mm2s-channel";
				dma-channels = <0x1>;
				interrupts = <0 35 4>;
				xlnx,datawidth = <0x40>;
				xlnx,device-id = <0x0>;
			};
			dma-channel@80400030 {
				compatible = "xlnx,axi-dma-s2mm-channel";
				dma-channels = <0x1>;
				interrupts = <0 36 4>;
				xlnx,datawidth = <0x40>;
				xlnx,device-id = <0x0>;
			};
		};

		rx_dma: dma@80410000 {
			#dma-cells = <1>;
			clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
			clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
			compatible = "xlnx,axi-dma-1.00.a";
			//dma-coherent ;
			interrupt-names = "mm2s_introut", "s2mm_introut";
			interrupt-parent = <1>;
			interrupts = <0 31 4 0 32 4>;
			reg = <0x80410000 0x10000>;
			xlnx,addrwidth = <0x20>;
			xlnx,include-sg ;
			xlnx,sg-length-width = <0xe>;
			dma-channel@80410000 {
				compatible = "xlnx,axi-dma-mm2s-channel";
				dma-channels = <0x1>;
				interrupts = <0 31 4>;
				xlnx,datawidth = <0x40>;
				xlnx,device-id = <0x1>;
			};
			dma-channel@80410030 {
				compatible = "xlnx,axi-dma-s2mm-channel";
				dma-channels = <0x1>;
				interrupts = <0 32 4>;
				xlnx,datawidth = <0x40>;
				xlnx,device-id = <0x1>;
			};
		};

		tx_intf_0: tx_intf@83c00000 {
			clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk";
			clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;
			compatible = "sdr,tx_intf";
			interrupt-names = "tx_itrpt";
			interrupt-parent = <1>;
			interrupts = <0 34 1>;
			reg = <0x83c00000 0x10000>;
			xlnx,s00-axi-addr-width = <0x7>;
			xlnx,s00-axi-data-width = <0x20>;
		};

		rx_intf_0: rx_intf@83c20000 {
			clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk";
			clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;
			compatible = "sdr,rx_intf";
			interrupt-names = "not_valid_anymore", "rx_pkt_intr";
			interrupt-parent = <1>;
			interrupts = <0 29 1 0 30 1>;
			reg = <0x83c20000 0x10000>;
			xlnx,s00-axi-addr-width = <0x7>;
			xlnx,s00-axi-data-width = <0x20>;
		};

		openofdm_tx_0: openofdm_tx@83c10000 {
			clock-names = "clk";
			clocks = <0x2 0x11>;
			compatible = "sdr,openofdm_tx";
			reg = <0x83c10000 0x10000>;
		};

		openofdm_rx_0: openofdm_rx@83c30000 {
			clock-names = "clk";
			clocks = <0x2 0x11>;
			compatible = "sdr,openofdm_rx";
			reg = <0x83c30000 0x10000>;
		};

		xpu_0: xpu@83c40000 {
			clock-names = "s00_axi_aclk";
			clocks = <0x2 0x11>;
			compatible = "sdr,xpu";
			reg = <0x83c40000 0x10000>;
		};

		side_ch_0: side_ch@83c50000 {
			clock-names = "s00_axi_aclk";
			clocks = <0x2 0x11>;
			compatible = "sdr,side_ch";
			reg = <0x83c50000 0x10000>;
			dmas = <&rx_dma 0
					&tx_dma 1>;
			dma-names = "rx_dma_mm2s", "tx_dma_s2mm";
		};

		cf-ad9361-lpc@79020000 {
			compatible = "adi,axi-ad9361-6.00.a";
			reg = <0x79020000 0x6000>;
			// dmas = <0x16 0x00>;
			// dma-names = "rx";
			spibus-connected = <0x17>;
			phandle = <0x40>;
		};

		cf-ad9361-dds-core-lpc@79024000 {
			compatible = "adi,axi-ad9361-dds-6.00.a";
			reg = <0x79024000 0x1000>;
			clocks = <0x17 0x0d>;
			clock-names = "sampl_clk";
			// dmas = <0x18 0x00>;
			// dma-names = "tx";
			phandle = <0x41>;
		};

		mwipcore@43c00000 {
			compatible = "mathworks,mwipcore-axi4lite-v1.00";
			reg = <0x43c00000 0xffff>;
		};

		// axi-sysid-0@45000000 {
		// 	compatible = "adi,axi-sysid-1.00.a";
		// 	reg = <0x45000000 0x10000>;
		// 	phandle = <0x42>;
		// };
	};

	leds {
		compatible = "gpio-leds";

		led0 {
			label = "led0:green";
			gpios = <0x09 0x15 0>;
			linux,default-trigger = "heartbeat";
		};

	};


};