1/dts-v1/; 2 3/ { 4 #address-cells = <0x1>; 5 #size-cells = <0x1>; 6 compatible = "xlnx,zynq-7000"; 7 interrupt-parent = <0x1>; 8 model = "ANTSDR-E200"; 9 10 cpus { 11 #address-cells = <0x1>; 12 #size-cells = <0x0>; 13 14 cpu@0 { 15 compatible = "arm,cortex-a9"; 16 device_type = "cpu"; 17 reg = <0x0>; 18 clocks = <0x2 0x3>; 19 clock-latency = <0x3e8>; 20 cpu0-supply = <0x3>; 21 operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>; 22 }; 23 24 cpu@1 { 25 compatible = "arm,cortex-a9"; 26 device_type = "cpu"; 27 reg = <0x1>; 28 clocks = <0x2 0x3>; 29 }; 30 }; 31 32 fpga-full { 33 compatible = "fpga-region"; 34 fpga-mgr = <0x4>; 35 #address-cells = <0x1>; 36 #size-cells = <0x1>; 37 ranges; 38 }; 39 40 pmu@f8891000 { 41 compatible = "arm,cortex-a9-pmu"; 42 interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>; 43 interrupt-parent = <0x1>; 44 reg = <0xf8891000 0x1000 0xf8893000 0x1000>; 45 }; 46 47 fixedregulator { 48 compatible = "regulator-fixed"; 49 regulator-name = "VCCPINT"; 50 regulator-min-microvolt = <0xf4240>; 51 regulator-max-microvolt = <0xf4240>; 52 regulator-boot-on; 53 regulator-always-on; 54 linux,phandle = <0x3>; 55 phandle = <0x3>; 56 }; 57 58 amba { 59 u-boot,dm-pre-reloc; 60 compatible = "simple-bus"; 61 #address-cells = <0x1>; 62 #size-cells = <0x1>; 63 interrupt-parent = <0x1>; 64 ranges; 65 66 adc@f8007100 { 67 compatible = "xlnx,zynq-xadc-1.00.a"; 68 reg = <0xf8007100 0x20>; 69 interrupts = <0x0 0x7 0x4>; 70 interrupt-parent = <0x1>; 71 clocks = <0x2 0xc>; 72 }; 73 74 can@e0008000 { 75 compatible = "xlnx,zynq-can-1.0"; 76 status = "disabled"; 77 clocks = <0x2 0x13 0x2 0x24>; 78 clock-names = "can_clk", "pclk"; 79 reg = <0xe0008000 0x1000>; 80 interrupts = <0x0 0x1c 0x4>; 81 interrupt-parent = <0x1>; 82 tx-fifo-depth = <0x40>; 83 rx-fifo-depth = <0x40>; 84 }; 85 86 can@e0009000 { 87 compatible = "xlnx,zynq-can-1.0"; 88 status = "disabled"; 89 clocks = <0x2 0x14 0x2 0x25>; 90 clock-names = "can_clk", "pclk"; 91 reg = <0xe0009000 0x1000>; 92 interrupts = <0x0 0x33 0x4>; 93 interrupt-parent = <0x1>; 94 tx-fifo-depth = <0x40>; 95 rx-fifo-depth = <0x40>; 96 }; 97 98 gpio@e000a000 { 99 compatible = "xlnx,zynq-gpio-1.0"; 100 #gpio-cells = <0x2>; 101 clocks = <0x2 0x2a>; 102 gpio-controller; 103 interrupt-controller; 104 #interrupt-cells = <0x2>; 105 interrupt-parent = <0x1>; 106 interrupts = <0x0 0x14 0x4>; 107 reg = <0xe000a000 0x1000>; 108 linux,phandle = <0x6>; 109 phandle = <0x6>; 110 }; 111 112 i2c@e0004000 { 113 compatible = "cdns,i2c-r1p10"; 114 status = "disabled"; 115 clocks = <0x2 0x26>; 116 interrupt-parent = <0x1>; 117 interrupts = <0x0 0x19 0x4>; 118 reg = <0xe0004000 0x1000>; 119 #address-cells = <0x1>; 120 #size-cells = <0x0>; 121 }; 122 123 i2c@e0005000 { 124 compatible = "cdns,i2c-r1p10"; 125 status = "disabled"; 126 clocks = <0x2 0x27>; 127 interrupt-parent = <0x1>; 128 interrupts = <0x0 0x30 0x4>; 129 reg = <0xe0005000 0x1000>; 130 #address-cells = <0x1>; 131 #size-cells = <0x0>; 132 }; 133 134 interrupt-controller@f8f01000 { 135 compatible = "arm,cortex-a9-gic"; 136 #interrupt-cells = <0x3>; 137 interrupt-controller; 138 reg = <0xf8f01000 0x1000 0xf8f00100 0x100>; 139 linux,phandle = <0x1>; 140 phandle = <0x1>; 141 }; 142 143 cache-controller@f8f02000 { 144 compatible = "arm,pl310-cache"; 145 reg = <0xf8f02000 0x1000>; 146 interrupts = <0x0 0x2 0x4>; 147 arm,data-latency = <0x3 0x2 0x2>; 148 arm,tag-latency = <0x2 0x2 0x2>; 149 cache-unified; 150 cache-level = <0x2>; 151 }; 152 153 memory-controller@f8006000 { 154 compatible = "xlnx,zynq-ddrc-a05"; 155 reg = <0xf8006000 0x1000>; 156 }; 157 158 ocmc@f800c000 { 159 compatible = "xlnx,zynq-ocmc-1.0"; 160 interrupt-parent = <0x1>; 161 interrupts = <0x0 0x3 0x4>; 162 reg = <0xf800c000 0x1000>; 163 }; 164 165 serial@e0000000 { 166 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 167 status = "okay"; 168 clocks = <0x2 0x17 0x2 0x28>; 169 clock-names = "uart_clk", "pclk"; 170 reg = <0xe0000000 0x1000>; 171 interrupts = <0x0 0x1b 0x4>; 172 }; 173 174 serial@e0001000 { 175 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 176 status = "okay"; 177 clocks = <0x2 0x18 0x2 0x29>; 178 clock-names = "uart_clk", "pclk"; 179 reg = <0xe0001000 0x1000>; 180 interrupts = <0x0 0x32 0x4>; 181 }; 182 183 spi@e0006000 { 184 compatible = "xlnx,zynq-spi-r1p6"; 185 reg = <0xe0006000 0x1000>; 186 status = "okay"; 187 interrupt-parent = <0x1>; 188 interrupts = <0x0 0x1a 0x4>; 189 clocks = <0x2 0x19 0x2 0x22>; 190 clock-names = "ref_clk", "pclk"; 191 #address-cells = <0x1>; 192 #size-cells = <0x0>; 193 194 ad9361-phy@0 { 195 #address-cells = <0x1>; 196 #size-cells = <0x0>; 197 #clock-cells = <0x1>; 198 compatible = "adi,ad9361"; 199 reg = <0x0>; 200 spi-cpha; 201 spi-max-frequency = <0x989680>; 202 clocks = <0x5 0x0>; 203 clock-names = "ad9364_ext_refclk"; 204 clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; 205 adi,digital-interface-tune-skip-mode = <0x0>; 206 adi,pp-tx-swap-enable; 207 adi,pp-rx-swap-enable; 208 adi,rx-frame-pulse-mode-enable; 209 adi,lvds-mode-enable; 210 adi,lvds-bias-mV = <0x96>; 211 adi,lvds-rx-onchip-termination-enable; 212 adi,rx-data-delay = <0x4>; 213 adi,tx-fb-clock-delay = <0x7>; 214 adi,xo-disable-use-ext-refclk-enable; 215 adi,2rx-2tx-mode-enable; 216 adi,frequency-division-duplex-mode-enable; 217 adi,rx-rf-port-input-select = <0x0>; 218 adi,tx-rf-port-input-select = <0x0>; 219 adi,tx-attenuation-mdB = <0x2710>; 220 adi,tx-lo-powerdown-managed-enable; 221 adi,rf-rx-bandwidth-hz = <0x112a880>; 222 adi,rf-tx-bandwidth-hz = <0x112a880>; 223 adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>; 224 adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>; 225 adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 226 adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 227 adi,gc-rx1-mode = <0x2>; 228 adi,gc-rx2-mode = <0x2>; 229 adi,gc-adc-ovr-sample-size = <0x4>; 230 adi,gc-adc-small-overload-thresh = <0x2f>; 231 adi,gc-adc-large-overload-thresh = <0x3a>; 232 adi,gc-lmt-overload-high-thresh = <0x320>; 233 adi,gc-lmt-overload-low-thresh = <0x2c0>; 234 adi,gc-dec-pow-measurement-duration = <0x2000>; 235 adi,gc-low-power-thresh = <0x18>; 236 adi,mgc-inc-gain-step = <0x2>; 237 adi,mgc-dec-gain-step = <0x2>; 238 adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>; 239 adi,agc-attack-delay-extra-margin-us = <0x1>; 240 adi,agc-outer-thresh-high = <0x5>; 241 adi,agc-outer-thresh-high-dec-steps = <0x2>; 242 adi,agc-inner-thresh-high = <0xa>; 243 adi,agc-inner-thresh-high-dec-steps = <0x1>; 244 adi,agc-inner-thresh-low = <0xc>; 245 adi,agc-inner-thresh-low-inc-steps = <0x1>; 246 adi,agc-outer-thresh-low = <0x12>; 247 adi,agc-outer-thresh-low-inc-steps = <0x2>; 248 adi,agc-adc-small-overload-exceed-counter = <0xa>; 249 adi,agc-adc-large-overload-exceed-counter = <0xa>; 250 adi,agc-adc-large-overload-inc-steps = <0x2>; 251 adi,agc-lmt-overload-large-exceed-counter = <0xa>; 252 adi,agc-lmt-overload-small-exceed-counter = <0xa>; 253 adi,agc-lmt-overload-large-inc-steps = <0x2>; 254 adi,agc-gain-update-interval-us = <0x3e8>; 255 adi,fagc-dec-pow-measurement-duration = <0x40>; 256 adi,fagc-lp-thresh-increment-steps = <0x1>; 257 adi,fagc-lp-thresh-increment-time = <0x5>; 258 adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>; 259 adi,fagc-final-overrange-count = <0x3>; 260 adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>; 261 adi,fagc-lmt-final-settling-steps = <0x1>; 262 adi,fagc-lock-level = <0xa>; 263 adi,fagc-lock-level-gain-increase-upper-limit = <0x5>; 264 adi,fagc-lock-level-lmt-gain-increase-enable; 265 adi,fagc-lpf-final-settling-steps = <0x1>; 266 adi,fagc-optimized-gain-offset = <0x5>; 267 adi,fagc-power-measurement-duration-in-state5 = <0x40>; 268 adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable; 269 adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>; 270 adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable; 271 adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>; 272 adi,fagc-rst-gla-large-adc-overload-enable; 273 adi,fagc-rst-gla-large-lmt-overload-enable; 274 adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>; 275 adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable; 276 adi,fagc-state-wait-time-ns = <0x104>; 277 adi,fagc-use-last-lock-level-for-set-gain-enable; 278 adi,rssi-restart-mode = <0x3>; 279 adi,rssi-delay = <0x1>; 280 adi,rssi-wait = <0x1>; 281 adi,rssi-duration = <0x3e8>; 282 adi,ctrl-outs-index = <0x0>; 283 adi,ctrl-outs-enable-mask = <0xff>; 284 adi,temp-sense-measurement-interval-ms = <0x3e8>; 285 adi,temp-sense-offset-signed = <0xce>; 286 adi,temp-sense-periodic-measurement-enable; 287 adi,aux-dac-manual-mode-enable; 288 adi,aux-dac1-default-value-mV = <0x0>; 289 adi,aux-dac1-rx-delay-us = <0x0>; 290 adi,aux-dac1-tx-delay-us = <0x0>; 291 adi,aux-dac2-default-value-mV = <0x0>; 292 adi,aux-dac2-rx-delay-us = <0x0>; 293 adi,aux-dac2-tx-delay-us = <0x0>; 294 en_agc-gpios = <0x6 0x62 0x0>; 295 sync-gpios = <0x6 0x63 0x0>; 296 reset-gpios = <0x6 0x64 0x0>; 297 enable-gpios = <0x6 0x65 0x0>; 298 txnrx-gpios = <0x6 0x66 0x0>; 299 linux,phandle = <0xb>; 300 phandle = <0xb>; 301 }; 302 }; 303 304 spi@e0007000 { 305 compatible = "xlnx,zynq-spi-r1p6"; 306 reg = <0xe0007000 0x1000>; 307 status = "disabled"; 308 interrupt-parent = <0x1>; 309 interrupts = <0x0 0x31 0x4>; 310 clocks = <0x2 0x1a 0x2 0x23>; 311 clock-names = "ref_clk", "pclk"; 312 #address-cells = <0x1>; 313 #size-cells = <0x0>; 314 }; 315 316 spi@e000d000 { 317 clock-names = "ref_clk", "pclk"; 318 clocks = <0x2 0xa 0x2 0x2b>; 319 compatible = "xlnx,zynq-qspi-1.0"; 320 status = "okay"; 321 interrupt-parent = <0x1>; 322 interrupts = <0x0 0x13 0x4>; 323 reg = <0xe000d000 0x1000>; 324 #address-cells = <0x1>; 325 #size-cells = <0x0>; 326 is-dual = <0x0>; 327 num-cs = <0x1>; 328 329 ps7-qspi@0 { 330 #address-cells = <0x1>; 331 #size-cells = <0x1>; 332 spi-tx-bus-width = <0x1>; 333 spi-rx-bus-width = <0x4>; 334 compatible = "n25q256a", "jedec,spi-nor"; 335 reg = <0x0>; 336 spi-max-frequency = <0x2faf080>; 337 338 partition@qspi-fsbl-uboot { 339 label = "qspi-fsbl-uboot"; 340 reg = <0x0 0xe0000>; 341 }; 342 343 partition@qspi-uboot-env { 344 label = "qspi-uboot-env"; 345 reg = <0xe0000 0x20000>; 346 }; 347 348 partition@qspi-linux { 349 label = "qspi-linux"; 350 reg = <0x100000 0x500000>; 351 }; 352 353 partition@qspi-device-tree { 354 label = "qspi-device-tree"; 355 reg = <0x600000 0x20000>; 356 }; 357 358 partition@qspi-rootfs { 359 label = "qspi-rootfs"; 360 reg = <0x620000 0xce0000>; 361 }; 362 363 partition@qspi-bitstream { 364 label = "qspi-bitstream"; 365 reg = <0x1300000 0xd00000>; 366 }; 367 }; 368 }; 369 370 memory-controller@e000e000 { 371 #address-cells = <0x1>; 372 #size-cells = <0x1>; 373 status = "disabled"; 374 clock-names = "memclk", "aclk"; 375 clocks = <0x2 0xb 0x2 0x2c>; 376 compatible = "arm,pl353-smc-r2p1"; 377 interrupt-parent = <0x1>; 378 interrupts = <0x0 0x12 0x4>; 379 ranges; 380 reg = <0xe000e000 0x1000>; 381 382 flash@e1000000 { 383 status = "disabled"; 384 compatible = "arm,pl353-nand-r2p1"; 385 reg = <0xe1000000 0x1000000>; 386 #address-cells = <0x1>; 387 #size-cells = <0x1>; 388 }; 389 390 flash@e2000000 { 391 status = "disabled"; 392 compatible = "cfi-flash"; 393 reg = <0xe2000000 0x2000000>; 394 #address-cells = <0x1>; 395 #size-cells = <0x1>; 396 }; 397 }; 398 399 ethernet@e000b000 { 400 compatible = "cdns,zynq-gem", "cdns,gem"; 401 reg = <0xe000b000 0x1000>; 402 status = "okay"; 403 interrupts = <0x0 0x16 0x4>; 404 clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>; 405 clock-names = "pclk", "hclk", "tx_clk"; 406 #address-cells = <0x1>; 407 #size-cells = <0x0>; 408 phy-handle = <&phy0>; 409 phy-mode = "rgmii-id"; 410 xlnx,has-mdio = <0x1>; 411 gmii2rgmii-phy-handle = <&gmii_to_rgmii_0>; 412 413 phy0: phy@1 { 414 compatible = "ethernet-phy-id011c.c916"; 415 device_type = "ethernet-phy"; 416 reg = <0x1>; 417 }; 418 419 gmii_to_rgmii_0: gmiitorgmii@8 { 420 compatible = "xlnx,gmii-to-rgmii-1.0"; 421 reg = <0x8>; 422 phy-handle = <&phy0>; 423 }; 424 }; 425 426 ethernet@e000c000 { 427 compatible = "cdns,zynq-gem", "cdns,gem"; 428 reg = <0xe000c000 0x1000>; 429 status = "disabled"; 430 interrupts = <0x0 0x2d 0x4>; 431 clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>; 432 clock-names = "pclk", "hclk", "tx_clk"; 433 #address-cells = <0x1>; 434 #size-cells = <0x0>; 435 }; 436 437 mmc@e0100000 { 438 compatible = "arasan,sdhci-8.9a"; 439 status = "okay"; 440 clock-names = "clk_xin", "clk_ahb"; 441 clocks = <0x2 0x15 0x2 0x20>; 442 interrupt-parent = <0x1>; 443 interrupts = <0x0 0x18 0x4>; 444 reg = <0xe0100000 0x1000>; 445 disable-wp; 446 }; 447 448 mmc@e0101000 { 449 compatible = "arasan,sdhci-8.9a"; 450 status = "disabled"; 451 clock-names = "clk_xin", "clk_ahb"; 452 clocks = <0x2 0x16 0x2 0x21>; 453 interrupt-parent = <0x1>; 454 interrupts = <0x0 0x2f 0x4>; 455 reg = <0xe0101000 0x1000>; 456 }; 457 458 slcr@f8000000 { 459 u-boot,dm-pre-reloc; 460 #address-cells = <0x1>; 461 #size-cells = <0x1>; 462 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; 463 reg = <0xf8000000 0x1000>; 464 ranges; 465 linux,phandle = <0x8>; 466 phandle = <0x8>; 467 468 clkc@100 { 469 u-boot,dm-pre-reloc; 470 #clock-cells = <0x1>; 471 compatible = "xlnx,ps7-clkc"; 472 fclk-enable = <0xf>; 473 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; 474 reg = <0x100 0x100>; 475 ps-clk-frequency = <0x1fca055>; 476 linux,phandle = <0x2>; 477 phandle = <0x2>; 478 }; 479 480 rstc@200 { 481 compatible = "xlnx,zynq-reset"; 482 reg = <0x200 0x48>; 483 #reset-cells = <0x1>; 484 syscon = <0x8>; 485 }; 486 487 pinctrl@700 { 488 compatible = "xlnx,pinctrl-zynq"; 489 reg = <0x700 0x200>; 490 syscon = <0x8>; 491 }; 492 }; 493 494 dmac@f8003000 { 495 compatible = "arm,pl330", "arm,primecell"; 496 reg = <0xf8003000 0x1000>; 497 interrupt-parent = <0x1>; 498 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; 499 interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>; 500 #dma-cells = <0x1>; 501 #dma-channels = <0x8>; 502 #dma-requests = <0x4>; 503 clocks = <0x2 0x1b>; 504 clock-names = "apb_pclk"; 505 }; 506 507 devcfg@f8007000 { 508 compatible = "xlnx,zynq-devcfg-1.0"; 509 interrupt-parent = <0x1>; 510 interrupts = <0x0 0x8 0x4>; 511 reg = <0xf8007000 0x100>; 512 clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>; 513 clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; 514 syscon = <0x8>; 515 linux,phandle = <0x4>; 516 phandle = <0x4>; 517 }; 518 519 efuse@f800d000 { 520 compatible = "xlnx,zynq-efuse"; 521 reg = <0xf800d000 0x20>; 522 }; 523 524 timer@f8f00200 { 525 compatible = "arm,cortex-a9-global-timer"; 526 reg = <0xf8f00200 0x20>; 527 interrupts = <0x1 0xb 0x301>; 528 interrupt-parent = <0x1>; 529 clocks = <0x2 0x4>; 530 }; 531 532 timer@f8001000 { 533 interrupt-parent = <0x1>; 534 interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>; 535 compatible = "cdns,ttc"; 536 clocks = <0x2 0x6>; 537 reg = <0xf8001000 0x1000>; 538 }; 539 540 timer@f8002000 { 541 interrupt-parent = <0x1>; 542 interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>; 543 compatible = "cdns,ttc"; 544 clocks = <0x2 0x6>; 545 reg = <0xf8002000 0x1000>; 546 }; 547 548 timer@f8f00600 { 549 interrupt-parent = <0x1>; 550 interrupts = <0x1 0xd 0x301>; 551 compatible = "arm,cortex-a9-twd-timer"; 552 reg = <0xf8f00600 0x20>; 553 clocks = <0x2 0x4>; 554 }; 555 556 usb@e0002000 { 557 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 558 status = "disabled"; 559 clocks = <0x2 0x1c>; 560 interrupt-parent = <0x1>; 561 interrupts = <0x0 0x15 0x4>; 562 reg = <0xe0002000 0x1000>; 563 phy_type = "ulpi"; 564 dr_mode = "host"; 565 xlnx,phy-reset-gpio = <0x6 0x7 0x0>; 566 }; 567 568 usb@e0003000 { 569 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 570 status = "disabled"; 571 clocks = <0x2 0x1d>; 572 interrupt-parent = <0x1>; 573 interrupts = <0x0 0x2c 0x4>; 574 reg = <0xe0003000 0x1000>; 575 phy_type = "ulpi"; 576 }; 577 578 watchdog@f8005000 { 579 clocks = <0x2 0x2d>; 580 compatible = "cdns,wdt-r1p2"; 581 interrupt-parent = <0x1>; 582 interrupts = <0x0 0x9 0x1>; 583 reg = <0xf8005000 0x1000>; 584 timeout-sec = <0xa>; 585 }; 586 }; 587 588 aliases { 589 ethernet0 = "/amba/ethernet@e000b000"; 590 serial0 = "/amba/serial@e0000000"; 591 }; 592 593 memory { 594 device_type = "memory"; 595 reg = <0x0 0x20000000>; 596 }; 597 598 chosen { 599 linux,stdout-path = "/amba@0/uart@E0000000"; 600 }; 601 602 clocks { 603 604 clock@0 { 605 #clock-cells = <0x0>; 606 compatible = "adjustable-clock"; 607 clock-frequency = <0x2625a00>; 608 clock-accuracy = <0x30d40>; 609 clock-output-names = "ad9364_ext_refclk"; 610 linux,phandle = <0x5>; 611 phandle = <0x5>; 612 }; 613 614 clock@1 { 615 #clock-cells = <0x0>; 616 compatible = "fixed-clock"; 617 clock-frequency = <0x16e3600>; 618 clock-output-names = "24MHz"; 619 linux,phandle = <0x9>; 620 phandle = <0x9>; 621 }; 622 }; 623 624 usb-ulpi-gpio-gate@0 { 625 compatible = "gpio-gate-clock"; 626 clocks = <0x9>; 627 #clock-cells = <0x0>; 628 enable-gpios = <0x6 0x9 0x1>; 629 }; 630 631 fpga-axi@0 { 632 compatible = "simple-bus"; 633 #address-cells = <0x1>; 634 #size-cells = <0x1>; 635 ranges; 636 637 i2c@41600000 { 638 compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a"; 639 reg = <0x41600000 0x10000>; 640 interrupt-parent = <0x1>; 641 interrupts = <0x0 0x3a 0x4>; 642 clocks = <0x2 0xf>; 643 clock-names = "pclk"; 644 #address-cells = <0x1>; 645 #size-cells = <0x0>; 646 647 ad7291@20 { 648 compatible = "adi,ad7291"; 649 reg = <0x20>; 650 }; 651 652 ad7291-bob@2C { 653 compatible = "adi,ad7291"; 654 reg = <0x2c>; 655 }; 656 657 eeprom@50 { 658 compatible = "at24,24c32"; 659 reg = <0x50>; 660 }; 661 }; 662 663 // dma@7c400000 { 664 // compatible = "adi,axi-dmac-1.00.a"; 665 // reg = <0x7c400000 0x10000>; 666 // #dma-cells = <0x1>; 667 // interrupts = <0x0 0x39 0x0>; 668 // clocks = <0x2 0x10>; 669 // linux,phandle = <0xa>; 670 // phandle = <0xa>; 671 672 // adi,channels { 673 // #size-cells = <0x0>; 674 // #address-cells = <0x1>; 675 676 // dma-channel@0 { 677 // reg = <0x0>; 678 // adi,source-bus-width = <0x40>; 679 // adi,source-bus-type = <0x2>; 680 // adi,destination-bus-width = <0x40>; 681 // adi,destination-bus-type = <0x0>; 682 // }; 683 // }; 684 // }; 685 686 // dma@7c420000 { 687 // compatible = "adi,axi-dmac-1.00.a"; 688 // reg = <0x7c420000 0x10000>; 689 // #dma-cells = <0x1>; 690 // interrupts = <0x0 0x38 0x0>; 691 // clocks = <0x2 0x10>; 692 // linux,phandle = <0xc>; 693 // phandle = <0xc>; 694 695 // adi,channels { 696 // #size-cells = <0x0>; 697 // #address-cells = <0x1>; 698 699 // dma-channel@0 { 700 // reg = <0x0>; 701 // adi,source-bus-width = <0x40>; 702 // adi,source-bus-type = <0x0>; 703 // adi,destination-bus-width = <0x40>; 704 // adi,destination-bus-type = <0x2>; 705 // }; 706 // }; 707 // }; 708 709 sdr: sdr { 710 compatible ="sdr,sdr"; 711 dmas = <&rx_dma 1 712 &tx_dma 0>; 713 dma-names = "rx_dma_s2mm", "tx_dma_mm2s"; 714 interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt"; 715 interrupt-parent = <1>; 716 interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>; 717 } ; 718 719 axidmatest_1: axidmatest@1 { 720 compatible ="xlnx,axi-dma-test-1.00.a"; 721 dmas = <&rx_dma 0 722 &rx_dma 1>; 723 dma-names = "axidma0", "axidma1"; 724 } ; 725 726 tx_dma: dma@80400000 { 727 #dma-cells = <1>; 728 clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; 729 clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 730 compatible = "xlnx,axi-dma-1.00.a"; 731 interrupt-names = "mm2s_introut", "s2mm_introut"; 732 interrupt-parent = <1>; 733 interrupts = <0 35 4 0 36 4>; 734 reg = <0x80400000 0x10000>; 735 xlnx,addrwidth = <0x20>; 736 xlnx,include-sg ; 737 xlnx,sg-length-width = <0xe>; 738 dma-channel@80400000 { 739 compatible = "xlnx,axi-dma-mm2s-channel"; 740 dma-channels = <0x1>; 741 interrupts = <0 35 4>; 742 xlnx,datawidth = <0x40>; 743 xlnx,device-id = <0x0>; 744 }; 745 dma-channel@80400030 { 746 compatible = "xlnx,axi-dma-s2mm-channel"; 747 dma-channels = <0x1>; 748 interrupts = <0 36 4>; 749 xlnx,datawidth = <0x40>; 750 xlnx,device-id = <0x0>; 751 }; 752 }; 753 754 rx_dma: dma@80410000 { 755 #dma-cells = <1>; 756 clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; 757 clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 758 compatible = "xlnx,axi-dma-1.00.a"; 759 //dma-coherent ; 760 interrupt-names = "mm2s_introut", "s2mm_introut"; 761 interrupt-parent = <1>; 762 interrupts = <0 31 4 0 32 4>; 763 reg = <0x80410000 0x10000>; 764 xlnx,addrwidth = <0x20>; 765 xlnx,include-sg ; 766 xlnx,sg-length-width = <0xe>; 767 dma-channel@80410000 { 768 compatible = "xlnx,axi-dma-mm2s-channel"; 769 dma-channels = <0x1>; 770 interrupts = <0 31 4>; 771 xlnx,datawidth = <0x40>; 772 xlnx,device-id = <0x1>; 773 }; 774 dma-channel@80410030 { 775 compatible = "xlnx,axi-dma-s2mm-channel"; 776 dma-channels = <0x1>; 777 interrupts = <0 32 4>; 778 xlnx,datawidth = <0x40>; 779 xlnx,device-id = <0x1>; 780 }; 781 }; 782 783 tx_intf_0: tx_intf@83c00000 { 784 clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk"; 785 clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>; 786 compatible = "sdr,tx_intf"; 787 interrupt-names = "tx_itrpt"; 788 interrupt-parent = <1>; 789 interrupts = <0 34 1>; 790 reg = <0x83c00000 0x10000>; 791 xlnx,s00-axi-addr-width = <0x7>; 792 xlnx,s00-axi-data-width = <0x20>; 793 }; 794 795 rx_intf_0: rx_intf@83c20000 { 796 clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk"; 797 clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>; 798 compatible = "sdr,rx_intf"; 799 interrupt-names = "not_valid_anymore", "rx_pkt_intr"; 800 interrupt-parent = <1>; 801 interrupts = <0 29 1 0 30 1>; 802 reg = <0x83c20000 0x10000>; 803 xlnx,s00-axi-addr-width = <0x7>; 804 xlnx,s00-axi-data-width = <0x20>; 805 }; 806 807 openofdm_tx_0: openofdm_tx@83c10000 { 808 clock-names = "clk"; 809 clocks = <0x2 0x11>; 810 compatible = "sdr,openofdm_tx"; 811 reg = <0x83c10000 0x10000>; 812 }; 813 814 openofdm_rx_0: openofdm_rx@83c30000 { 815 clock-names = "clk"; 816 clocks = <0x2 0x11>; 817 compatible = "sdr,openofdm_rx"; 818 reg = <0x83c30000 0x10000>; 819 }; 820 821 xpu_0: xpu@83c40000 { 822 clock-names = "s00_axi_aclk"; 823 clocks = <0x2 0x11>; 824 compatible = "sdr,xpu"; 825 reg = <0x83c40000 0x10000>; 826 }; 827 828 side_ch_0: side_ch@83c50000 { 829 clock-names = "s00_axi_aclk"; 830 clocks = <0x2 0x11>; 831 compatible = "sdr,side_ch"; 832 reg = <0x83c50000 0x10000>; 833 dmas = <&rx_dma 0 834 &tx_dma 1>; 835 dma-names = "rx_dma_mm2s", "tx_dma_s2mm"; 836 }; 837 838 cf-ad9361-lpc@79020000 { 839 compatible = "adi,axi-ad9361-6.00.a"; 840 reg = <0x79020000 0x6000>; 841 // dmas = <0xa 0x0>; 842 // dma-names = "rx"; 843 spibus-connected = <0xb>; 844 }; 845 846 cf-ad9361-dds-core-lpc@79024000 { 847 compatible = "adi,axi-ad9361-dds-6.00.a"; 848 reg = <0x79024000 0x1000>; 849 clocks = <0xb 0xd>; 850 clock-names = "sampl_clk"; 851 // dmas = <0xc 0x0>; 852 // dma-names = "tx"; 853 }; 854 855 mwipcore@43c00000 { 856 compatible = "mathworks,mwipcore-axi4lite-v1.00"; 857 reg = <0x43c00000 0xffff>; 858 }; 859 860 /*axi-sysid-0@45000000 { 861 compatible = "adi,axi-sysid-1.00.a"; 862 reg = <0x45000000 0x10000>; 863 };*/ 864 }; 865 866 leds { 867 compatible = "gpio-leds"; 868 869 led0 { 870 label = "led0:green"; 871 gpios = <0x6 0x0 0>; 872 linux,default-trigger = "heartbeat"; 873 }; 874 }; 875 876}; 877