1*b73660adSXianjun Jiao/dts-v1/; 2*b73660adSXianjun Jiao 3*b73660adSXianjun Jiao/ { 4*b73660adSXianjun Jiao #address-cells = <0x1>; 5*b73660adSXianjun Jiao #size-cells = <0x1>; 6*b73660adSXianjun Jiao compatible = "xlnx,zynq-7000"; 7*b73660adSXianjun Jiao interrupt-parent = <0x1>; 8*b73660adSXianjun Jiao model = "Analog Devices ADRV9364-Z7020 (Z7020/AD9364)"; 9*b73660adSXianjun Jiao 10*b73660adSXianjun Jiao cpus { 11*b73660adSXianjun Jiao #address-cells = <0x1>; 12*b73660adSXianjun Jiao #size-cells = <0x0>; 13*b73660adSXianjun Jiao 14*b73660adSXianjun Jiao cpu@0 { 15*b73660adSXianjun Jiao compatible = "arm,cortex-a9"; 16*b73660adSXianjun Jiao device_type = "cpu"; 17*b73660adSXianjun Jiao reg = <0x0>; 18*b73660adSXianjun Jiao clocks = <0x2 0x3>; 19*b73660adSXianjun Jiao clock-latency = <0x3e8>; 20*b73660adSXianjun Jiao cpu0-supply = <0x3>; 21*b73660adSXianjun Jiao operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>; 22*b73660adSXianjun Jiao }; 23*b73660adSXianjun Jiao 24*b73660adSXianjun Jiao cpu@1 { 25*b73660adSXianjun Jiao compatible = "arm,cortex-a9"; 26*b73660adSXianjun Jiao device_type = "cpu"; 27*b73660adSXianjun Jiao reg = <0x1>; 28*b73660adSXianjun Jiao clocks = <0x2 0x3>; 29*b73660adSXianjun Jiao }; 30*b73660adSXianjun Jiao }; 31*b73660adSXianjun Jiao 32*b73660adSXianjun Jiao fpga-full { 33*b73660adSXianjun Jiao compatible = "fpga-region"; 34*b73660adSXianjun Jiao fpga-mgr = <0x4>; 35*b73660adSXianjun Jiao #address-cells = <0x1>; 36*b73660adSXianjun Jiao #size-cells = <0x1>; 37*b73660adSXianjun Jiao ranges; 38*b73660adSXianjun Jiao }; 39*b73660adSXianjun Jiao 40*b73660adSXianjun Jiao pmu@f8891000 { 41*b73660adSXianjun Jiao compatible = "arm,cortex-a9-pmu"; 42*b73660adSXianjun Jiao interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>; 43*b73660adSXianjun Jiao interrupt-parent = <0x1>; 44*b73660adSXianjun Jiao reg = <0xf8891000 0x1000 0xf8893000 0x1000>; 45*b73660adSXianjun Jiao }; 46*b73660adSXianjun Jiao 47*b73660adSXianjun Jiao fixedregulator { 48*b73660adSXianjun Jiao compatible = "regulator-fixed"; 49*b73660adSXianjun Jiao regulator-name = "VCCPINT"; 50*b73660adSXianjun Jiao regulator-min-microvolt = <0xf4240>; 51*b73660adSXianjun Jiao regulator-max-microvolt = <0xf4240>; 52*b73660adSXianjun Jiao regulator-boot-on; 53*b73660adSXianjun Jiao regulator-always-on; 54*b73660adSXianjun Jiao linux,phandle = <0x3>; 55*b73660adSXianjun Jiao phandle = <0x3>; 56*b73660adSXianjun Jiao }; 57*b73660adSXianjun Jiao 58*b73660adSXianjun Jiao amba { 59*b73660adSXianjun Jiao u-boot,dm-pre-reloc; 60*b73660adSXianjun Jiao compatible = "simple-bus"; 61*b73660adSXianjun Jiao #address-cells = <0x1>; 62*b73660adSXianjun Jiao #size-cells = <0x1>; 63*b73660adSXianjun Jiao interrupt-parent = <0x1>; 64*b73660adSXianjun Jiao ranges; 65*b73660adSXianjun Jiao 66*b73660adSXianjun Jiao adc@f8007100 { 67*b73660adSXianjun Jiao compatible = "xlnx,zynq-xadc-1.00.a"; 68*b73660adSXianjun Jiao reg = <0xf8007100 0x20>; 69*b73660adSXianjun Jiao interrupts = <0x0 0x7 0x4>; 70*b73660adSXianjun Jiao interrupt-parent = <0x1>; 71*b73660adSXianjun Jiao clocks = <0x2 0xc>; 72*b73660adSXianjun Jiao }; 73*b73660adSXianjun Jiao 74*b73660adSXianjun Jiao can@e0008000 { 75*b73660adSXianjun Jiao compatible = "xlnx,zynq-can-1.0"; 76*b73660adSXianjun Jiao status = "disabled"; 77*b73660adSXianjun Jiao clocks = <0x2 0x13 0x2 0x24>; 78*b73660adSXianjun Jiao clock-names = "can_clk", "pclk"; 79*b73660adSXianjun Jiao reg = <0xe0008000 0x1000>; 80*b73660adSXianjun Jiao interrupts = <0x0 0x1c 0x4>; 81*b73660adSXianjun Jiao interrupt-parent = <0x1>; 82*b73660adSXianjun Jiao tx-fifo-depth = <0x40>; 83*b73660adSXianjun Jiao rx-fifo-depth = <0x40>; 84*b73660adSXianjun Jiao }; 85*b73660adSXianjun Jiao 86*b73660adSXianjun Jiao can@e0009000 { 87*b73660adSXianjun Jiao compatible = "xlnx,zynq-can-1.0"; 88*b73660adSXianjun Jiao status = "disabled"; 89*b73660adSXianjun Jiao clocks = <0x2 0x14 0x2 0x25>; 90*b73660adSXianjun Jiao clock-names = "can_clk", "pclk"; 91*b73660adSXianjun Jiao reg = <0xe0009000 0x1000>; 92*b73660adSXianjun Jiao interrupts = <0x0 0x33 0x4>; 93*b73660adSXianjun Jiao interrupt-parent = <0x1>; 94*b73660adSXianjun Jiao tx-fifo-depth = <0x40>; 95*b73660adSXianjun Jiao rx-fifo-depth = <0x40>; 96*b73660adSXianjun Jiao }; 97*b73660adSXianjun Jiao 98*b73660adSXianjun Jiao gpio@e000a000 { 99*b73660adSXianjun Jiao compatible = "xlnx,zynq-gpio-1.0"; 100*b73660adSXianjun Jiao #gpio-cells = <0x2>; 101*b73660adSXianjun Jiao clocks = <0x2 0x2a>; 102*b73660adSXianjun Jiao gpio-controller; 103*b73660adSXianjun Jiao interrupt-controller; 104*b73660adSXianjun Jiao #interrupt-cells = <0x2>; 105*b73660adSXianjun Jiao interrupt-parent = <0x1>; 106*b73660adSXianjun Jiao interrupts = <0x0 0x14 0x4>; 107*b73660adSXianjun Jiao reg = <0xe000a000 0x1000>; 108*b73660adSXianjun Jiao linux,phandle = <0x6>; 109*b73660adSXianjun Jiao phandle = <0x6>; 110*b73660adSXianjun Jiao }; 111*b73660adSXianjun Jiao 112*b73660adSXianjun Jiao i2c@e0004000 { 113*b73660adSXianjun Jiao compatible = "cdns,i2c-r1p10"; 114*b73660adSXianjun Jiao status = "disabled"; 115*b73660adSXianjun Jiao clocks = <0x2 0x26>; 116*b73660adSXianjun Jiao interrupt-parent = <0x1>; 117*b73660adSXianjun Jiao interrupts = <0x0 0x19 0x4>; 118*b73660adSXianjun Jiao reg = <0xe0004000 0x1000>; 119*b73660adSXianjun Jiao #address-cells = <0x1>; 120*b73660adSXianjun Jiao #size-cells = <0x0>; 121*b73660adSXianjun Jiao }; 122*b73660adSXianjun Jiao 123*b73660adSXianjun Jiao i2c@e0005000 { 124*b73660adSXianjun Jiao compatible = "cdns,i2c-r1p10"; 125*b73660adSXianjun Jiao status = "disabled"; 126*b73660adSXianjun Jiao clocks = <0x2 0x27>; 127*b73660adSXianjun Jiao interrupt-parent = <0x1>; 128*b73660adSXianjun Jiao interrupts = <0x0 0x30 0x4>; 129*b73660adSXianjun Jiao reg = <0xe0005000 0x1000>; 130*b73660adSXianjun Jiao #address-cells = <0x1>; 131*b73660adSXianjun Jiao #size-cells = <0x0>; 132*b73660adSXianjun Jiao }; 133*b73660adSXianjun Jiao 134*b73660adSXianjun Jiao interrupt-controller@f8f01000 { 135*b73660adSXianjun Jiao compatible = "arm,cortex-a9-gic"; 136*b73660adSXianjun Jiao #interrupt-cells = <0x3>; 137*b73660adSXianjun Jiao interrupt-controller; 138*b73660adSXianjun Jiao reg = <0xf8f01000 0x1000 0xf8f00100 0x100>; 139*b73660adSXianjun Jiao linux,phandle = <0x1>; 140*b73660adSXianjun Jiao phandle = <0x1>; 141*b73660adSXianjun Jiao }; 142*b73660adSXianjun Jiao 143*b73660adSXianjun Jiao cache-controller@f8f02000 { 144*b73660adSXianjun Jiao compatible = "arm,pl310-cache"; 145*b73660adSXianjun Jiao reg = <0xf8f02000 0x1000>; 146*b73660adSXianjun Jiao interrupts = <0x0 0x2 0x4>; 147*b73660adSXianjun Jiao arm,data-latency = <0x3 0x2 0x2>; 148*b73660adSXianjun Jiao arm,tag-latency = <0x2 0x2 0x2>; 149*b73660adSXianjun Jiao cache-unified; 150*b73660adSXianjun Jiao cache-level = <0x2>; 151*b73660adSXianjun Jiao }; 152*b73660adSXianjun Jiao 153*b73660adSXianjun Jiao memory-controller@f8006000 { 154*b73660adSXianjun Jiao compatible = "xlnx,zynq-ddrc-a05"; 155*b73660adSXianjun Jiao reg = <0xf8006000 0x1000>; 156*b73660adSXianjun Jiao }; 157*b73660adSXianjun Jiao 158*b73660adSXianjun Jiao ocmc@f800c000 { 159*b73660adSXianjun Jiao compatible = "xlnx,zynq-ocmc-1.0"; 160*b73660adSXianjun Jiao interrupt-parent = <0x1>; 161*b73660adSXianjun Jiao interrupts = <0x0 0x3 0x4>; 162*b73660adSXianjun Jiao reg = <0xf800c000 0x1000>; 163*b73660adSXianjun Jiao }; 164*b73660adSXianjun Jiao 165*b73660adSXianjun Jiao serial@e0000000 { 166*b73660adSXianjun Jiao compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 167*b73660adSXianjun Jiao status = "disabled"; 168*b73660adSXianjun Jiao clocks = <0x2 0x17 0x2 0x28>; 169*b73660adSXianjun Jiao clock-names = "uart_clk", "pclk"; 170*b73660adSXianjun Jiao reg = <0xe0000000 0x1000>; 171*b73660adSXianjun Jiao interrupts = <0x0 0x1b 0x4>; 172*b73660adSXianjun Jiao }; 173*b73660adSXianjun Jiao 174*b73660adSXianjun Jiao serial@e0001000 { 175*b73660adSXianjun Jiao compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 176*b73660adSXianjun Jiao status = "okay"; 177*b73660adSXianjun Jiao clocks = <0x2 0x18 0x2 0x29>; 178*b73660adSXianjun Jiao clock-names = "uart_clk", "pclk"; 179*b73660adSXianjun Jiao reg = <0xe0001000 0x1000>; 180*b73660adSXianjun Jiao interrupts = <0x0 0x32 0x4>; 181*b73660adSXianjun Jiao }; 182*b73660adSXianjun Jiao 183*b73660adSXianjun Jiao spi@e0006000 { 184*b73660adSXianjun Jiao compatible = "xlnx,zynq-spi-r1p6"; 185*b73660adSXianjun Jiao reg = <0xe0006000 0x1000>; 186*b73660adSXianjun Jiao status = "okay"; 187*b73660adSXianjun Jiao interrupt-parent = <0x1>; 188*b73660adSXianjun Jiao interrupts = <0x0 0x1a 0x4>; 189*b73660adSXianjun Jiao clocks = <0x2 0x19 0x2 0x22>; 190*b73660adSXianjun Jiao clock-names = "ref_clk", "pclk"; 191*b73660adSXianjun Jiao #address-cells = <0x1>; 192*b73660adSXianjun Jiao #size-cells = <0x0>; 193*b73660adSXianjun Jiao 194*b73660adSXianjun Jiao ad9361-phy@0 { 195*b73660adSXianjun Jiao #address-cells = <0x1>; 196*b73660adSXianjun Jiao #size-cells = <0x0>; 197*b73660adSXianjun Jiao #clock-cells = <0x1>; 198*b73660adSXianjun Jiao compatible = "adi,ad9361"; 199*b73660adSXianjun Jiao reg = <0x0>; 200*b73660adSXianjun Jiao spi-cpha; 201*b73660adSXianjun Jiao spi-max-frequency = <0x989680>; 202*b73660adSXianjun Jiao clocks = <0x5 0x0>; 203*b73660adSXianjun Jiao clock-names = "ad9364_ext_refclk"; 204*b73660adSXianjun Jiao clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; 205*b73660adSXianjun Jiao adi,digital-interface-tune-skip-mode = <0x0>; 206*b73660adSXianjun Jiao adi,pp-tx-swap-enable; 207*b73660adSXianjun Jiao adi,pp-rx-swap-enable; 208*b73660adSXianjun Jiao adi,rx-frame-pulse-mode-enable; 209*b73660adSXianjun Jiao adi,lvds-mode-enable; 210*b73660adSXianjun Jiao adi,lvds-bias-mV = <0x96>; 211*b73660adSXianjun Jiao adi,lvds-rx-onchip-termination-enable; 212*b73660adSXianjun Jiao adi,rx-data-delay = <0x4>; 213*b73660adSXianjun Jiao adi,tx-fb-clock-delay = <0x7>; 214*b73660adSXianjun Jiao adi,xo-disable-use-ext-refclk-enable; 215*b73660adSXianjun Jiao adi,2rx-2tx-mode-enable; 216*b73660adSXianjun Jiao adi,frequency-division-duplex-mode-enable; 217*b73660adSXianjun Jiao adi,rx-rf-port-input-select = <0x0>; 218*b73660adSXianjun Jiao adi,tx-rf-port-input-select = <0x0>; 219*b73660adSXianjun Jiao adi,tx-attenuation-mdB = <0x2710>; 220*b73660adSXianjun Jiao adi,rf-rx-bandwidth-hz = <0x112a880>; 221*b73660adSXianjun Jiao adi,rf-tx-bandwidth-hz = <0x112a880>; 222*b73660adSXianjun Jiao adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>; 223*b73660adSXianjun Jiao adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>; 224*b73660adSXianjun Jiao adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 225*b73660adSXianjun Jiao adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 226*b73660adSXianjun Jiao adi,gc-rx1-mode = <0x2>; 227*b73660adSXianjun Jiao adi,gc-rx2-mode = <0x2>; 228*b73660adSXianjun Jiao adi,gc-adc-ovr-sample-size = <0x4>; 229*b73660adSXianjun Jiao adi,gc-adc-small-overload-thresh = <0x2f>; 230*b73660adSXianjun Jiao adi,gc-adc-large-overload-thresh = <0x3a>; 231*b73660adSXianjun Jiao adi,gc-lmt-overload-high-thresh = <0x320>; 232*b73660adSXianjun Jiao adi,gc-lmt-overload-low-thresh = <0x2c0>; 233*b73660adSXianjun Jiao adi,gc-dec-pow-measurement-duration = <0x2000>; 234*b73660adSXianjun Jiao adi,gc-low-power-thresh = <0x18>; 235*b73660adSXianjun Jiao adi,mgc-inc-gain-step = <0x2>; 236*b73660adSXianjun Jiao adi,mgc-dec-gain-step = <0x2>; 237*b73660adSXianjun Jiao adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>; 238*b73660adSXianjun Jiao adi,agc-attack-delay-extra-margin-us = <0x1>; 239*b73660adSXianjun Jiao adi,agc-outer-thresh-high = <0x5>; 240*b73660adSXianjun Jiao adi,agc-outer-thresh-high-dec-steps = <0x2>; 241*b73660adSXianjun Jiao adi,agc-inner-thresh-high = <0xa>; 242*b73660adSXianjun Jiao adi,agc-inner-thresh-high-dec-steps = <0x1>; 243*b73660adSXianjun Jiao adi,agc-inner-thresh-low = <0xc>; 244*b73660adSXianjun Jiao adi,agc-inner-thresh-low-inc-steps = <0x1>; 245*b73660adSXianjun Jiao adi,agc-outer-thresh-low = <0x12>; 246*b73660adSXianjun Jiao adi,agc-outer-thresh-low-inc-steps = <0x2>; 247*b73660adSXianjun Jiao adi,agc-adc-small-overload-exceed-counter = <0xa>; 248*b73660adSXianjun Jiao adi,agc-adc-large-overload-exceed-counter = <0xa>; 249*b73660adSXianjun Jiao adi,agc-adc-large-overload-inc-steps = <0x2>; 250*b73660adSXianjun Jiao adi,agc-lmt-overload-large-exceed-counter = <0xa>; 251*b73660adSXianjun Jiao adi,agc-lmt-overload-small-exceed-counter = <0xa>; 252*b73660adSXianjun Jiao adi,agc-lmt-overload-large-inc-steps = <0x2>; 253*b73660adSXianjun Jiao adi,agc-gain-update-interval-us = <0x3e8>; 254*b73660adSXianjun Jiao adi,fagc-dec-pow-measurement-duration = <0x40>; 255*b73660adSXianjun Jiao adi,fagc-lp-thresh-increment-steps = <0x1>; 256*b73660adSXianjun Jiao adi,fagc-lp-thresh-increment-time = <0x5>; 257*b73660adSXianjun Jiao adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>; 258*b73660adSXianjun Jiao adi,fagc-final-overrange-count = <0x3>; 259*b73660adSXianjun Jiao adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>; 260*b73660adSXianjun Jiao adi,fagc-lmt-final-settling-steps = <0x1>; 261*b73660adSXianjun Jiao adi,fagc-lock-level = <0xa>; 262*b73660adSXianjun Jiao adi,fagc-lock-level-gain-increase-upper-limit = <0x5>; 263*b73660adSXianjun Jiao adi,fagc-lock-level-lmt-gain-increase-enable; 264*b73660adSXianjun Jiao adi,fagc-lpf-final-settling-steps = <0x1>; 265*b73660adSXianjun Jiao adi,fagc-optimized-gain-offset = <0x5>; 266*b73660adSXianjun Jiao adi,fagc-power-measurement-duration-in-state5 = <0x40>; 267*b73660adSXianjun Jiao adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable; 268*b73660adSXianjun Jiao adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>; 269*b73660adSXianjun Jiao adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable; 270*b73660adSXianjun Jiao adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>; 271*b73660adSXianjun Jiao adi,fagc-rst-gla-large-adc-overload-enable; 272*b73660adSXianjun Jiao adi,fagc-rst-gla-large-lmt-overload-enable; 273*b73660adSXianjun Jiao adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>; 274*b73660adSXianjun Jiao adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable; 275*b73660adSXianjun Jiao adi,fagc-state-wait-time-ns = <0x104>; 276*b73660adSXianjun Jiao adi,fagc-use-last-lock-level-for-set-gain-enable; 277*b73660adSXianjun Jiao adi,rssi-restart-mode = <0x3>; 278*b73660adSXianjun Jiao adi,rssi-delay = <0x1>; 279*b73660adSXianjun Jiao adi,rssi-wait = <0x1>; 280*b73660adSXianjun Jiao adi,rssi-duration = <0x3e8>; 281*b73660adSXianjun Jiao adi,ctrl-outs-index = <0x0>; 282*b73660adSXianjun Jiao adi,ctrl-outs-enable-mask = <0xff>; 283*b73660adSXianjun Jiao adi,temp-sense-measurement-interval-ms = <0x3e8>; 284*b73660adSXianjun Jiao adi,temp-sense-offset-signed = <0xce>; 285*b73660adSXianjun Jiao adi,temp-sense-periodic-measurement-enable; 286*b73660adSXianjun Jiao adi,aux-dac-manual-mode-enable; 287*b73660adSXianjun Jiao adi,aux-dac1-default-value-mV = <0x0>; 288*b73660adSXianjun Jiao adi,aux-dac1-rx-delay-us = <0x0>; 289*b73660adSXianjun Jiao adi,aux-dac1-tx-delay-us = <0x0>; 290*b73660adSXianjun Jiao adi,aux-dac2-default-value-mV = <0x0>; 291*b73660adSXianjun Jiao adi,aux-dac2-rx-delay-us = <0x0>; 292*b73660adSXianjun Jiao adi,aux-dac2-tx-delay-us = <0x0>; 293*b73660adSXianjun Jiao en_agc-gpios = <0x6 0x62 0x0>; 294*b73660adSXianjun Jiao sync-gpios = <0x6 0x63 0x0>; 295*b73660adSXianjun Jiao reset-gpios = <0x6 0x64 0x0>; 296*b73660adSXianjun Jiao enable-gpios = <0x6 0x65 0x0>; 297*b73660adSXianjun Jiao txnrx-gpios = <0x6 0x66 0x0>; 298*b73660adSXianjun Jiao linux,phandle = <0xb>; 299*b73660adSXianjun Jiao phandle = <0xb>; 300*b73660adSXianjun Jiao }; 301*b73660adSXianjun Jiao }; 302*b73660adSXianjun Jiao 303*b73660adSXianjun Jiao spi@e0007000 { 304*b73660adSXianjun Jiao compatible = "xlnx,zynq-spi-r1p6"; 305*b73660adSXianjun Jiao reg = <0xe0007000 0x1000>; 306*b73660adSXianjun Jiao status = "disabled"; 307*b73660adSXianjun Jiao interrupt-parent = <0x1>; 308*b73660adSXianjun Jiao interrupts = <0x0 0x31 0x4>; 309*b73660adSXianjun Jiao clocks = <0x2 0x1a 0x2 0x23>; 310*b73660adSXianjun Jiao clock-names = "ref_clk", "pclk"; 311*b73660adSXianjun Jiao #address-cells = <0x1>; 312*b73660adSXianjun Jiao #size-cells = <0x0>; 313*b73660adSXianjun Jiao }; 314*b73660adSXianjun Jiao 315*b73660adSXianjun Jiao spi@e000d000 { 316*b73660adSXianjun Jiao clock-names = "ref_clk", "pclk"; 317*b73660adSXianjun Jiao clocks = <0x2 0xa 0x2 0x2b>; 318*b73660adSXianjun Jiao compatible = "xlnx,zynq-qspi-1.0"; 319*b73660adSXianjun Jiao status = "okay"; 320*b73660adSXianjun Jiao interrupt-parent = <0x1>; 321*b73660adSXianjun Jiao interrupts = <0x0 0x13 0x4>; 322*b73660adSXianjun Jiao reg = <0xe000d000 0x1000>; 323*b73660adSXianjun Jiao #address-cells = <0x1>; 324*b73660adSXianjun Jiao #size-cells = <0x0>; 325*b73660adSXianjun Jiao is-dual = <0x0>; 326*b73660adSXianjun Jiao num-cs = <0x1>; 327*b73660adSXianjun Jiao 328*b73660adSXianjun Jiao ps7-qspi@0 { 329*b73660adSXianjun Jiao #address-cells = <0x1>; 330*b73660adSXianjun Jiao #size-cells = <0x1>; 331*b73660adSXianjun Jiao spi-tx-bus-width = <0x1>; 332*b73660adSXianjun Jiao spi-rx-bus-width = <0x4>; 333*b73660adSXianjun Jiao compatible = "n25q256a", "jedec,spi-nor"; 334*b73660adSXianjun Jiao reg = <0x0>; 335*b73660adSXianjun Jiao spi-max-frequency = <0x2faf080>; 336*b73660adSXianjun Jiao 337*b73660adSXianjun Jiao partition@qspi-fsbl-uboot { 338*b73660adSXianjun Jiao label = "qspi-fsbl-uboot"; 339*b73660adSXianjun Jiao reg = <0x0 0xe0000>; 340*b73660adSXianjun Jiao }; 341*b73660adSXianjun Jiao 342*b73660adSXianjun Jiao partition@qspi-uboot-env { 343*b73660adSXianjun Jiao label = "qspi-uboot-env"; 344*b73660adSXianjun Jiao reg = <0xe0000 0x20000>; 345*b73660adSXianjun Jiao }; 346*b73660adSXianjun Jiao 347*b73660adSXianjun Jiao partition@qspi-linux { 348*b73660adSXianjun Jiao label = "qspi-linux"; 349*b73660adSXianjun Jiao reg = <0x100000 0x500000>; 350*b73660adSXianjun Jiao }; 351*b73660adSXianjun Jiao 352*b73660adSXianjun Jiao partition@qspi-device-tree { 353*b73660adSXianjun Jiao label = "qspi-device-tree"; 354*b73660adSXianjun Jiao reg = <0x600000 0x20000>; 355*b73660adSXianjun Jiao }; 356*b73660adSXianjun Jiao 357*b73660adSXianjun Jiao partition@qspi-rootfs { 358*b73660adSXianjun Jiao label = "qspi-rootfs"; 359*b73660adSXianjun Jiao reg = <0x620000 0xce0000>; 360*b73660adSXianjun Jiao }; 361*b73660adSXianjun Jiao 362*b73660adSXianjun Jiao partition@qspi-bitstream { 363*b73660adSXianjun Jiao label = "qspi-bitstream"; 364*b73660adSXianjun Jiao reg = <0x1300000 0xd00000>; 365*b73660adSXianjun Jiao }; 366*b73660adSXianjun Jiao }; 367*b73660adSXianjun Jiao }; 368*b73660adSXianjun Jiao 369*b73660adSXianjun Jiao memory-controller@e000e000 { 370*b73660adSXianjun Jiao #address-cells = <0x1>; 371*b73660adSXianjun Jiao #size-cells = <0x1>; 372*b73660adSXianjun Jiao status = "disabled"; 373*b73660adSXianjun Jiao clock-names = "memclk", "aclk"; 374*b73660adSXianjun Jiao clocks = <0x2 0xb 0x2 0x2c>; 375*b73660adSXianjun Jiao compatible = "arm,pl353-smc-r2p1"; 376*b73660adSXianjun Jiao interrupt-parent = <0x1>; 377*b73660adSXianjun Jiao interrupts = <0x0 0x12 0x4>; 378*b73660adSXianjun Jiao ranges; 379*b73660adSXianjun Jiao reg = <0xe000e000 0x1000>; 380*b73660adSXianjun Jiao 381*b73660adSXianjun Jiao flash@e1000000 { 382*b73660adSXianjun Jiao status = "disabled"; 383*b73660adSXianjun Jiao compatible = "arm,pl353-nand-r2p1"; 384*b73660adSXianjun Jiao reg = <0xe1000000 0x1000000>; 385*b73660adSXianjun Jiao #address-cells = <0x1>; 386*b73660adSXianjun Jiao #size-cells = <0x1>; 387*b73660adSXianjun Jiao }; 388*b73660adSXianjun Jiao 389*b73660adSXianjun Jiao flash@e2000000 { 390*b73660adSXianjun Jiao status = "disabled"; 391*b73660adSXianjun Jiao compatible = "cfi-flash"; 392*b73660adSXianjun Jiao reg = <0xe2000000 0x2000000>; 393*b73660adSXianjun Jiao #address-cells = <0x1>; 394*b73660adSXianjun Jiao #size-cells = <0x1>; 395*b73660adSXianjun Jiao }; 396*b73660adSXianjun Jiao }; 397*b73660adSXianjun Jiao 398*b73660adSXianjun Jiao ethernet@e000b000 { 399*b73660adSXianjun Jiao compatible = "cdns,zynq-gem", "cdns,gem"; 400*b73660adSXianjun Jiao reg = <0xe000b000 0x1000>; 401*b73660adSXianjun Jiao status = "okay"; 402*b73660adSXianjun Jiao interrupts = <0x0 0x16 0x4>; 403*b73660adSXianjun Jiao clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>; 404*b73660adSXianjun Jiao clock-names = "pclk", "hclk", "tx_clk"; 405*b73660adSXianjun Jiao #address-cells = <0x1>; 406*b73660adSXianjun Jiao #size-cells = <0x0>; 407*b73660adSXianjun Jiao phy-handle = <0x7>; 408*b73660adSXianjun Jiao phy-mode = "rgmii-id"; 409*b73660adSXianjun Jiao 410*b73660adSXianjun Jiao phy@0 { 411*b73660adSXianjun Jiao device_type = "ethernet-phy"; 412*b73660adSXianjun Jiao reg = <0x0>; 413*b73660adSXianjun Jiao marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>; 414*b73660adSXianjun Jiao linux,phandle = <0x7>; 415*b73660adSXianjun Jiao phandle = <0x7>; 416*b73660adSXianjun Jiao }; 417*b73660adSXianjun Jiao }; 418*b73660adSXianjun Jiao 419*b73660adSXianjun Jiao ethernet@e000c000 { 420*b73660adSXianjun Jiao compatible = "cdns,zynq-gem", "cdns,gem"; 421*b73660adSXianjun Jiao reg = <0xe000c000 0x1000>; 422*b73660adSXianjun Jiao status = "disabled"; 423*b73660adSXianjun Jiao interrupts = <0x0 0x2d 0x4>; 424*b73660adSXianjun Jiao clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>; 425*b73660adSXianjun Jiao clock-names = "pclk", "hclk", "tx_clk"; 426*b73660adSXianjun Jiao #address-cells = <0x1>; 427*b73660adSXianjun Jiao #size-cells = <0x0>; 428*b73660adSXianjun Jiao }; 429*b73660adSXianjun Jiao 430*b73660adSXianjun Jiao sdhci@e0100000 { 431*b73660adSXianjun Jiao compatible = "arasan,sdhci-8.9a"; 432*b73660adSXianjun Jiao status = "okay"; 433*b73660adSXianjun Jiao clock-names = "clk_xin", "clk_ahb"; 434*b73660adSXianjun Jiao clocks = <0x2 0x15 0x2 0x20>; 435*b73660adSXianjun Jiao interrupt-parent = <0x1>; 436*b73660adSXianjun Jiao interrupts = <0x0 0x18 0x4>; 437*b73660adSXianjun Jiao reg = <0xe0100000 0x1000>; 438*b73660adSXianjun Jiao broken-adma2; 439*b73660adSXianjun Jiao disable-wp; 440*b73660adSXianjun Jiao }; 441*b73660adSXianjun Jiao 442*b73660adSXianjun Jiao sdhci@e0101000 { 443*b73660adSXianjun Jiao compatible = "arasan,sdhci-8.9a"; 444*b73660adSXianjun Jiao status = "disabled"; 445*b73660adSXianjun Jiao clock-names = "clk_xin", "clk_ahb"; 446*b73660adSXianjun Jiao clocks = <0x2 0x16 0x2 0x21>; 447*b73660adSXianjun Jiao interrupt-parent = <0x1>; 448*b73660adSXianjun Jiao interrupts = <0x0 0x2f 0x4>; 449*b73660adSXianjun Jiao reg = <0xe0101000 0x1000>; 450*b73660adSXianjun Jiao broken-adma2; 451*b73660adSXianjun Jiao }; 452*b73660adSXianjun Jiao 453*b73660adSXianjun Jiao slcr@f8000000 { 454*b73660adSXianjun Jiao #address-cells = <0x1>; 455*b73660adSXianjun Jiao #size-cells = <0x1>; 456*b73660adSXianjun Jiao compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; 457*b73660adSXianjun Jiao reg = <0xf8000000 0x1000>; 458*b73660adSXianjun Jiao ranges; 459*b73660adSXianjun Jiao linux,phandle = <0x8>; 460*b73660adSXianjun Jiao phandle = <0x8>; 461*b73660adSXianjun Jiao 462*b73660adSXianjun Jiao clkc@100 { 463*b73660adSXianjun Jiao #clock-cells = <0x1>; 464*b73660adSXianjun Jiao compatible = "xlnx,ps7-clkc"; 465*b73660adSXianjun Jiao fclk-enable = <0xf>; 466*b73660adSXianjun Jiao clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; 467*b73660adSXianjun Jiao reg = <0x100 0x100>; 468*b73660adSXianjun Jiao ps-clk-frequency = <0x1fca055>; 469*b73660adSXianjun Jiao linux,phandle = <0x2>; 470*b73660adSXianjun Jiao phandle = <0x2>; 471*b73660adSXianjun Jiao }; 472*b73660adSXianjun Jiao 473*b73660adSXianjun Jiao rstc@200 { 474*b73660adSXianjun Jiao compatible = "xlnx,zynq-reset"; 475*b73660adSXianjun Jiao reg = <0x200 0x48>; 476*b73660adSXianjun Jiao #reset-cells = <0x1>; 477*b73660adSXianjun Jiao syscon = <0x8>; 478*b73660adSXianjun Jiao }; 479*b73660adSXianjun Jiao 480*b73660adSXianjun Jiao pinctrl@700 { 481*b73660adSXianjun Jiao compatible = "xlnx,pinctrl-zynq"; 482*b73660adSXianjun Jiao reg = <0x700 0x200>; 483*b73660adSXianjun Jiao syscon = <0x8>; 484*b73660adSXianjun Jiao }; 485*b73660adSXianjun Jiao }; 486*b73660adSXianjun Jiao 487*b73660adSXianjun Jiao dmac@f8003000 { 488*b73660adSXianjun Jiao compatible = "arm,pl330", "arm,primecell"; 489*b73660adSXianjun Jiao reg = <0xf8003000 0x1000>; 490*b73660adSXianjun Jiao interrupt-parent = <0x1>; 491*b73660adSXianjun Jiao interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; 492*b73660adSXianjun Jiao interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>; 493*b73660adSXianjun Jiao #dma-cells = <0x1>; 494*b73660adSXianjun Jiao #dma-channels = <0x8>; 495*b73660adSXianjun Jiao #dma-requests = <0x4>; 496*b73660adSXianjun Jiao clocks = <0x2 0x1b>; 497*b73660adSXianjun Jiao clock-names = "apb_pclk"; 498*b73660adSXianjun Jiao }; 499*b73660adSXianjun Jiao 500*b73660adSXianjun Jiao devcfg@f8007000 { 501*b73660adSXianjun Jiao compatible = "xlnx,zynq-devcfg-1.0"; 502*b73660adSXianjun Jiao interrupt-parent = <0x1>; 503*b73660adSXianjun Jiao interrupts = <0x0 0x8 0x4>; 504*b73660adSXianjun Jiao reg = <0xf8007000 0x100>; 505*b73660adSXianjun Jiao clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>; 506*b73660adSXianjun Jiao clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; 507*b73660adSXianjun Jiao syscon = <0x8>; 508*b73660adSXianjun Jiao linux,phandle = <0x4>; 509*b73660adSXianjun Jiao phandle = <0x4>; 510*b73660adSXianjun Jiao }; 511*b73660adSXianjun Jiao 512*b73660adSXianjun Jiao efuse@f800d000 { 513*b73660adSXianjun Jiao compatible = "xlnx,zynq-efuse"; 514*b73660adSXianjun Jiao reg = <0xf800d000 0x20>; 515*b73660adSXianjun Jiao }; 516*b73660adSXianjun Jiao 517*b73660adSXianjun Jiao timer@f8f00200 { 518*b73660adSXianjun Jiao compatible = "arm,cortex-a9-global-timer"; 519*b73660adSXianjun Jiao reg = <0xf8f00200 0x20>; 520*b73660adSXianjun Jiao interrupts = <0x1 0xb 0x301>; 521*b73660adSXianjun Jiao interrupt-parent = <0x1>; 522*b73660adSXianjun Jiao clocks = <0x2 0x4>; 523*b73660adSXianjun Jiao }; 524*b73660adSXianjun Jiao 525*b73660adSXianjun Jiao timer@f8001000 { 526*b73660adSXianjun Jiao interrupt-parent = <0x1>; 527*b73660adSXianjun Jiao interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>; 528*b73660adSXianjun Jiao compatible = "cdns,ttc"; 529*b73660adSXianjun Jiao clocks = <0x2 0x6>; 530*b73660adSXianjun Jiao reg = <0xf8001000 0x1000>; 531*b73660adSXianjun Jiao }; 532*b73660adSXianjun Jiao 533*b73660adSXianjun Jiao timer@f8002000 { 534*b73660adSXianjun Jiao interrupt-parent = <0x1>; 535*b73660adSXianjun Jiao interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>; 536*b73660adSXianjun Jiao compatible = "cdns,ttc"; 537*b73660adSXianjun Jiao clocks = <0x2 0x6>; 538*b73660adSXianjun Jiao reg = <0xf8002000 0x1000>; 539*b73660adSXianjun Jiao }; 540*b73660adSXianjun Jiao 541*b73660adSXianjun Jiao timer@f8f00600 { 542*b73660adSXianjun Jiao interrupt-parent = <0x1>; 543*b73660adSXianjun Jiao interrupts = <0x1 0xd 0x301>; 544*b73660adSXianjun Jiao compatible = "arm,cortex-a9-twd-timer"; 545*b73660adSXianjun Jiao reg = <0xf8f00600 0x20>; 546*b73660adSXianjun Jiao clocks = <0x2 0x4>; 547*b73660adSXianjun Jiao }; 548*b73660adSXianjun Jiao 549*b73660adSXianjun Jiao usb@e0002000 { 550*b73660adSXianjun Jiao compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 551*b73660adSXianjun Jiao status = "okay"; 552*b73660adSXianjun Jiao clocks = <0x2 0x1c>; 553*b73660adSXianjun Jiao interrupt-parent = <0x1>; 554*b73660adSXianjun Jiao interrupts = <0x0 0x15 0x4>; 555*b73660adSXianjun Jiao reg = <0xe0002000 0x1000>; 556*b73660adSXianjun Jiao phy_type = "ulpi"; 557*b73660adSXianjun Jiao dr_mode = "host"; 558*b73660adSXianjun Jiao xlnx,phy-reset-gpio = <0x6 0x7 0x0>; 559*b73660adSXianjun Jiao }; 560*b73660adSXianjun Jiao 561*b73660adSXianjun Jiao usb@e0003000 { 562*b73660adSXianjun Jiao compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 563*b73660adSXianjun Jiao status = "disabled"; 564*b73660adSXianjun Jiao clocks = <0x2 0x1d>; 565*b73660adSXianjun Jiao interrupt-parent = <0x1>; 566*b73660adSXianjun Jiao interrupts = <0x0 0x2c 0x4>; 567*b73660adSXianjun Jiao reg = <0xe0003000 0x1000>; 568*b73660adSXianjun Jiao phy_type = "ulpi"; 569*b73660adSXianjun Jiao }; 570*b73660adSXianjun Jiao 571*b73660adSXianjun Jiao watchdog@f8005000 { 572*b73660adSXianjun Jiao clocks = <0x2 0x2d>; 573*b73660adSXianjun Jiao compatible = "cdns,wdt-r1p2"; 574*b73660adSXianjun Jiao interrupt-parent = <0x1>; 575*b73660adSXianjun Jiao interrupts = <0x0 0x9 0x1>; 576*b73660adSXianjun Jiao reg = <0xf8005000 0x1000>; 577*b73660adSXianjun Jiao timeout-sec = <0xa>; 578*b73660adSXianjun Jiao }; 579*b73660adSXianjun Jiao }; 580*b73660adSXianjun Jiao 581*b73660adSXianjun Jiao aliases { 582*b73660adSXianjun Jiao ethernet0 = "/amba/ethernet@e000b000"; 583*b73660adSXianjun Jiao serial0 = "/amba/serial@e0001000"; 584*b73660adSXianjun Jiao }; 585*b73660adSXianjun Jiao 586*b73660adSXianjun Jiao memory { 587*b73660adSXianjun Jiao device_type = "memory"; 588*b73660adSXianjun Jiao reg = <0x0 0x40000000>; 589*b73660adSXianjun Jiao }; 590*b73660adSXianjun Jiao 591*b73660adSXianjun Jiao chosen { 592*b73660adSXianjun Jiao linux,stdout-path = "/amba@0/uart@E0001000"; 593*b73660adSXianjun Jiao }; 594*b73660adSXianjun Jiao 595*b73660adSXianjun Jiao clocks { 596*b73660adSXianjun Jiao 597*b73660adSXianjun Jiao clock@0 { 598*b73660adSXianjun Jiao #clock-cells = <0x0>; 599*b73660adSXianjun Jiao compatible = "adjustable-clock"; 600*b73660adSXianjun Jiao clock-frequency = <0x2625a00>; 601*b73660adSXianjun Jiao clock-accuracy = <0x30d40>; 602*b73660adSXianjun Jiao clock-output-names = "ad9364_ext_refclk"; 603*b73660adSXianjun Jiao linux,phandle = <0x5>; 604*b73660adSXianjun Jiao phandle = <0x5>; 605*b73660adSXianjun Jiao }; 606*b73660adSXianjun Jiao 607*b73660adSXianjun Jiao clock@1 { 608*b73660adSXianjun Jiao #clock-cells = <0x0>; 609*b73660adSXianjun Jiao compatible = "fixed-clock"; 610*b73660adSXianjun Jiao clock-frequency = <0x16e3600>; 611*b73660adSXianjun Jiao clock-output-names = "24MHz"; 612*b73660adSXianjun Jiao linux,phandle = <0x9>; 613*b73660adSXianjun Jiao phandle = <0x9>; 614*b73660adSXianjun Jiao }; 615*b73660adSXianjun Jiao }; 616*b73660adSXianjun Jiao 617*b73660adSXianjun Jiao usb-ulpi-gpio-gate@0 { 618*b73660adSXianjun Jiao compatible = "gpio-gate-clock"; 619*b73660adSXianjun Jiao clocks = <0x9>; 620*b73660adSXianjun Jiao #clock-cells = <0x0>; 621*b73660adSXianjun Jiao enable-gpios = <0x6 0x9 0x1>; 622*b73660adSXianjun Jiao }; 623*b73660adSXianjun Jiao 624*b73660adSXianjun Jiao fpga-axi@0 { 625*b73660adSXianjun Jiao compatible = "simple-bus"; 626*b73660adSXianjun Jiao #address-cells = <0x1>; 627*b73660adSXianjun Jiao #size-cells = <0x1>; 628*b73660adSXianjun Jiao ranges; 629*b73660adSXianjun Jiao 630*b73660adSXianjun Jiao i2c@41600000 { 631*b73660adSXianjun Jiao compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a"; 632*b73660adSXianjun Jiao reg = <0x41600000 0x10000>; 633*b73660adSXianjun Jiao interrupt-parent = <0x1>; 634*b73660adSXianjun Jiao interrupts = <0x0 0x3a 0x4>; 635*b73660adSXianjun Jiao clocks = <0x2 0xf>; 636*b73660adSXianjun Jiao clock-names = "pclk"; 637*b73660adSXianjun Jiao #address-cells = <0x1>; 638*b73660adSXianjun Jiao #size-cells = <0x0>; 639*b73660adSXianjun Jiao 640*b73660adSXianjun Jiao ad7291@20 { 641*b73660adSXianjun Jiao compatible = "adi,ad7291"; 642*b73660adSXianjun Jiao reg = <0x20>; 643*b73660adSXianjun Jiao }; 644*b73660adSXianjun Jiao 645*b73660adSXianjun Jiao ad7291-bob@2C { 646*b73660adSXianjun Jiao compatible = "adi,ad7291"; 647*b73660adSXianjun Jiao reg = <0x2c>; 648*b73660adSXianjun Jiao }; 649*b73660adSXianjun Jiao 650*b73660adSXianjun Jiao eeprom@50 { 651*b73660adSXianjun Jiao compatible = "at24,24c32"; 652*b73660adSXianjun Jiao reg = <0x50>; 653*b73660adSXianjun Jiao }; 654*b73660adSXianjun Jiao }; 655*b73660adSXianjun Jiao 656*b73660adSXianjun Jiao dma@7c400000 { 657*b73660adSXianjun Jiao compatible = "adi,axi-dmac-1.00.a"; 658*b73660adSXianjun Jiao reg = <0x7c400000 0x10000>; 659*b73660adSXianjun Jiao #dma-cells = <0x1>; 660*b73660adSXianjun Jiao interrupts = <0x0 0x39 0x0>; 661*b73660adSXianjun Jiao clocks = <0x2 0x10>; 662*b73660adSXianjun Jiao linux,phandle = <0xa>; 663*b73660adSXianjun Jiao phandle = <0xa>; 664*b73660adSXianjun Jiao 665*b73660adSXianjun Jiao adi,channels { 666*b73660adSXianjun Jiao #size-cells = <0x0>; 667*b73660adSXianjun Jiao #address-cells = <0x1>; 668*b73660adSXianjun Jiao 669*b73660adSXianjun Jiao dma-channel@0 { 670*b73660adSXianjun Jiao reg = <0x0>; 671*b73660adSXianjun Jiao adi,source-bus-width = <0x40>; 672*b73660adSXianjun Jiao adi,source-bus-type = <0x2>; 673*b73660adSXianjun Jiao adi,destination-bus-width = <0x40>; 674*b73660adSXianjun Jiao adi,destination-bus-type = <0x0>; 675*b73660adSXianjun Jiao adi,length-width = <0x18>; 676*b73660adSXianjun Jiao }; 677*b73660adSXianjun Jiao }; 678*b73660adSXianjun Jiao }; 679*b73660adSXianjun Jiao 680*b73660adSXianjun Jiao dma@7c420000 { 681*b73660adSXianjun Jiao compatible = "adi,axi-dmac-1.00.a"; 682*b73660adSXianjun Jiao reg = <0x7c420000 0x10000>; 683*b73660adSXianjun Jiao #dma-cells = <0x1>; 684*b73660adSXianjun Jiao interrupts = <0x0 0x38 0x0>; 685*b73660adSXianjun Jiao clocks = <0x2 0x10>; 686*b73660adSXianjun Jiao linux,phandle = <0xc>; 687*b73660adSXianjun Jiao phandle = <0xc>; 688*b73660adSXianjun Jiao 689*b73660adSXianjun Jiao adi,channels { 690*b73660adSXianjun Jiao #size-cells = <0x0>; 691*b73660adSXianjun Jiao #address-cells = <0x1>; 692*b73660adSXianjun Jiao 693*b73660adSXianjun Jiao dma-channel@0 { 694*b73660adSXianjun Jiao reg = <0x0>; 695*b73660adSXianjun Jiao adi,source-bus-width = <0x40>; 696*b73660adSXianjun Jiao adi,source-bus-type = <0x0>; 697*b73660adSXianjun Jiao adi,destination-bus-width = <0x40>; 698*b73660adSXianjun Jiao adi,destination-bus-type = <0x2>; 699*b73660adSXianjun Jiao adi,length-width = <0x18>; 700*b73660adSXianjun Jiao adi,cyclic; 701*b73660adSXianjun Jiao }; 702*b73660adSXianjun Jiao }; 703*b73660adSXianjun Jiao }; 704*b73660adSXianjun Jiao 705*b73660adSXianjun Jiao sdr: sdr { 706*b73660adSXianjun Jiao compatible ="sdr,sdr"; 707*b73660adSXianjun Jiao dmas = <&rx_dma 0 708*b73660adSXianjun Jiao &rx_dma 1 709*b73660adSXianjun Jiao &tx_dma 0 710*b73660adSXianjun Jiao &tx_dma 1>; 711*b73660adSXianjun Jiao dma-names = "rx_dma_mm2s", "rx_dma_s2mm", "tx_dma_mm2s", "tx_dma_s2mm"; 712*b73660adSXianjun Jiao interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt0", "tx_itrpt1"; 713*b73660adSXianjun Jiao interrupt-parent = <1>; 714*b73660adSXianjun Jiao interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>; 715*b73660adSXianjun Jiao } ; 716*b73660adSXianjun Jiao 717*b73660adSXianjun Jiao axidmatest_1: axidmatest@1 { 718*b73660adSXianjun Jiao compatible ="xlnx,axi-dma-test-1.00.a"; 719*b73660adSXianjun Jiao dmas = <&rx_dma 0 720*b73660adSXianjun Jiao &rx_dma 1>; 721*b73660adSXianjun Jiao dma-names = "axidma0", "axidma1"; 722*b73660adSXianjun Jiao } ; 723*b73660adSXianjun Jiao 724*b73660adSXianjun Jiao tx_dma: dma@80400000 { 725*b73660adSXianjun Jiao #dma-cells = <1>; 726*b73660adSXianjun Jiao clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; 727*b73660adSXianjun Jiao clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 728*b73660adSXianjun Jiao compatible = "xlnx,axi-dma-1.00.a"; 729*b73660adSXianjun Jiao interrupt-names = "mm2s_introut", "s2mm_introut"; 730*b73660adSXianjun Jiao interrupt-parent = <1>; 731*b73660adSXianjun Jiao interrupts = <0 35 4 0 36 4>; 732*b73660adSXianjun Jiao reg = <0x80400000 0x10000>; 733*b73660adSXianjun Jiao xlnx,addrwidth = <0x20>; 734*b73660adSXianjun Jiao xlnx,include-sg ; 735*b73660adSXianjun Jiao xlnx,sg-length-width = <0xe>; 736*b73660adSXianjun Jiao dma-channel@80400000 { 737*b73660adSXianjun Jiao compatible = "xlnx,axi-dma-mm2s-channel"; 738*b73660adSXianjun Jiao dma-channels = <0x1>; 739*b73660adSXianjun Jiao interrupts = <0 35 4>; 740*b73660adSXianjun Jiao xlnx,datawidth = <0x40>; 741*b73660adSXianjun Jiao xlnx,device-id = <0x0>; 742*b73660adSXianjun Jiao }; 743*b73660adSXianjun Jiao dma-channel@80400030 { 744*b73660adSXianjun Jiao compatible = "xlnx,axi-dma-s2mm-channel"; 745*b73660adSXianjun Jiao dma-channels = <0x1>; 746*b73660adSXianjun Jiao interrupts = <0 36 4>; 747*b73660adSXianjun Jiao xlnx,datawidth = <0x40>; 748*b73660adSXianjun Jiao xlnx,device-id = <0x0>; 749*b73660adSXianjun Jiao }; 750*b73660adSXianjun Jiao }; 751*b73660adSXianjun Jiao 752*b73660adSXianjun Jiao rx_dma: dma@80410000 { 753*b73660adSXianjun Jiao #dma-cells = <1>; 754*b73660adSXianjun Jiao clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; 755*b73660adSXianjun Jiao clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 756*b73660adSXianjun Jiao compatible = "xlnx,axi-dma-1.00.a"; 757*b73660adSXianjun Jiao //dma-coherent ; 758*b73660adSXianjun Jiao interrupt-names = "mm2s_introut", "s2mm_introut"; 759*b73660adSXianjun Jiao interrupt-parent = <1>; 760*b73660adSXianjun Jiao interrupts = <0 31 4 0 32 4>; 761*b73660adSXianjun Jiao reg = <0x80410000 0x10000>; 762*b73660adSXianjun Jiao xlnx,addrwidth = <0x20>; 763*b73660adSXianjun Jiao xlnx,include-sg ; 764*b73660adSXianjun Jiao xlnx,sg-length-width = <0xe>; 765*b73660adSXianjun Jiao dma-channel@80410000 { 766*b73660adSXianjun Jiao compatible = "xlnx,axi-dma-mm2s-channel"; 767*b73660adSXianjun Jiao dma-channels = <0x1>; 768*b73660adSXianjun Jiao interrupts = <0 31 4>; 769*b73660adSXianjun Jiao xlnx,datawidth = <0x40>; 770*b73660adSXianjun Jiao xlnx,device-id = <0x1>; 771*b73660adSXianjun Jiao }; 772*b73660adSXianjun Jiao dma-channel@80410030 { 773*b73660adSXianjun Jiao compatible = "xlnx,axi-dma-s2mm-channel"; 774*b73660adSXianjun Jiao dma-channels = <0x1>; 775*b73660adSXianjun Jiao interrupts = <0 32 4>; 776*b73660adSXianjun Jiao xlnx,datawidth = <0x40>; 777*b73660adSXianjun Jiao xlnx,device-id = <0x1>; 778*b73660adSXianjun Jiao }; 779*b73660adSXianjun Jiao }; 780*b73660adSXianjun Jiao 781*b73660adSXianjun Jiao tx_intf_0: tx_intf@83c00000 { 782*b73660adSXianjun Jiao clock-names = "s00_axi_aclk", "s00_axis_aclk", "s01_axis_aclk", "m00_axis_aclk"; 783*b73660adSXianjun Jiao clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 784*b73660adSXianjun Jiao compatible = "sdr,tx_intf"; 785*b73660adSXianjun Jiao interrupt-names = "tx_itrpt0", "tx_itrpt1"; 786*b73660adSXianjun Jiao interrupt-parent = <1>; 787*b73660adSXianjun Jiao interrupts = <0 33 1 0 34 1>; 788*b73660adSXianjun Jiao reg = <0x83c00000 0x10000>; 789*b73660adSXianjun Jiao xlnx,s00-axi-addr-width = <0x7>; 790*b73660adSXianjun Jiao xlnx,s00-axi-data-width = <0x20>; 791*b73660adSXianjun Jiao }; 792*b73660adSXianjun Jiao 793*b73660adSXianjun Jiao rx_intf_0: rx_intf@83c20000 { 794*b73660adSXianjun Jiao clock-names = "s00_axi_aclk", "s00_axis_aclk", "m00_axis_aclk"; 795*b73660adSXianjun Jiao clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 796*b73660adSXianjun Jiao compatible = "sdr,rx_intf"; 797*b73660adSXianjun Jiao interrupt-names = "not_valid_anymore", "rx_pkt_intr"; 798*b73660adSXianjun Jiao interrupt-parent = <1>; 799*b73660adSXianjun Jiao interrupts = <0 29 1 0 30 1>; 800*b73660adSXianjun Jiao reg = <0x83c20000 0x10000>; 801*b73660adSXianjun Jiao xlnx,s00-axi-addr-width = <0x7>; 802*b73660adSXianjun Jiao xlnx,s00-axi-data-width = <0x20>; 803*b73660adSXianjun Jiao }; 804*b73660adSXianjun Jiao 805*b73660adSXianjun Jiao openofdm_tx_0: openofdm_tx@83c10000 { 806*b73660adSXianjun Jiao clock-names = "clk"; 807*b73660adSXianjun Jiao clocks = <0x2 0x11>; 808*b73660adSXianjun Jiao compatible = "sdr,openofdm_tx"; 809*b73660adSXianjun Jiao reg = <0x83c10000 0x10000>; 810*b73660adSXianjun Jiao }; 811*b73660adSXianjun Jiao 812*b73660adSXianjun Jiao openofdm_rx_0: openofdm_rx@83c30000 { 813*b73660adSXianjun Jiao clock-names = "clk"; 814*b73660adSXianjun Jiao clocks = <0x2 0x11>; 815*b73660adSXianjun Jiao compatible = "sdr,openofdm_rx"; 816*b73660adSXianjun Jiao reg = <0x83c30000 0x10000>; 817*b73660adSXianjun Jiao }; 818*b73660adSXianjun Jiao 819*b73660adSXianjun Jiao xpu_0: xpu@83c40000 { 820*b73660adSXianjun Jiao clock-names = "s00_axi_aclk"; 821*b73660adSXianjun Jiao clocks = <0x2 0x11>; 822*b73660adSXianjun Jiao compatible = "sdr,xpu"; 823*b73660adSXianjun Jiao reg = <0x83c40000 0x10000>; 824*b73660adSXianjun Jiao }; 825*b73660adSXianjun Jiao 826*b73660adSXianjun Jiao cf-ad9361-lpc@79020000 { 827*b73660adSXianjun Jiao compatible = "adi,axi-ad9361-6.00.a"; 828*b73660adSXianjun Jiao reg = <0x79020000 0x6000>; 829*b73660adSXianjun Jiao dmas = <0xa 0x0>; 830*b73660adSXianjun Jiao dma-names = "rx"; 831*b73660adSXianjun Jiao spibus-connected = <0xb>; 832*b73660adSXianjun Jiao }; 833*b73660adSXianjun Jiao 834*b73660adSXianjun Jiao cf-ad9361-dds-core-lpc@79024000 { 835*b73660adSXianjun Jiao compatible = "adi,axi-ad9361-dds-6.00.a"; 836*b73660adSXianjun Jiao reg = <0x79024000 0x1000>; 837*b73660adSXianjun Jiao clocks = <0xb 0xd>; 838*b73660adSXianjun Jiao clock-names = "sampl_clk"; 839*b73660adSXianjun Jiao dmas = <0xc 0x0>; 840*b73660adSXianjun Jiao dma-names = "tx"; 841*b73660adSXianjun Jiao }; 842*b73660adSXianjun Jiao 843*b73660adSXianjun Jiao mwipcore@43c00000 { 844*b73660adSXianjun Jiao compatible = "mathworks,mwipcore-axi4lite-v1.00"; 845*b73660adSXianjun Jiao reg = <0x43c00000 0xffff>; 846*b73660adSXianjun Jiao }; 847*b73660adSXianjun Jiao }; 848*b73660adSXianjun Jiao 849*b73660adSXianjun Jiao leds { 850*b73660adSXianjun Jiao compatible = "gpio-leds"; 851*b73660adSXianjun Jiao 852*b73660adSXianjun Jiao led0 { 853*b73660adSXianjun Jiao label = "led0:green"; 854*b73660adSXianjun Jiao gpios = <0x6 0x3a 0x0>; 855*b73660adSXianjun Jiao }; 856*b73660adSXianjun Jiao 857*b73660adSXianjun Jiao led1 { 858*b73660adSXianjun Jiao label = "led1:green"; 859*b73660adSXianjun Jiao gpios = <0x6 0x3b 0x0>; 860*b73660adSXianjun Jiao }; 861*b73660adSXianjun Jiao 862*b73660adSXianjun Jiao led2 { 863*b73660adSXianjun Jiao label = "led2:green"; 864*b73660adSXianjun Jiao gpios = <0x6 0x3c 0x0>; 865*b73660adSXianjun Jiao }; 866*b73660adSXianjun Jiao 867*b73660adSXianjun Jiao led3 { 868*b73660adSXianjun Jiao label = "led3:green"; 869*b73660adSXianjun Jiao gpios = <0x6 0x3d 0x0>; 870*b73660adSXianjun Jiao }; 871*b73660adSXianjun Jiao }; 872*b73660adSXianjun Jiao 873*b73660adSXianjun Jiao gpio_keys { 874*b73660adSXianjun Jiao compatible = "gpio-keys"; 875*b73660adSXianjun Jiao #address-cells = <0x1>; 876*b73660adSXianjun Jiao #size-cells = <0x0>; 877*b73660adSXianjun Jiao autorepeat; 878*b73660adSXianjun Jiao 879*b73660adSXianjun Jiao pb0 { 880*b73660adSXianjun Jiao label = "Left"; 881*b73660adSXianjun Jiao linux,code = <0x69>; 882*b73660adSXianjun Jiao gpios = <0x6 0x36 0x0>; 883*b73660adSXianjun Jiao }; 884*b73660adSXianjun Jiao 885*b73660adSXianjun Jiao pb1 { 886*b73660adSXianjun Jiao label = "Right"; 887*b73660adSXianjun Jiao linux,code = <0x6a>; 888*b73660adSXianjun Jiao gpios = <0x6 0x37 0x0>; 889*b73660adSXianjun Jiao }; 890*b73660adSXianjun Jiao 891*b73660adSXianjun Jiao pb2 { 892*b73660adSXianjun Jiao label = "Up"; 893*b73660adSXianjun Jiao linux,code = <0x67>; 894*b73660adSXianjun Jiao gpios = <0x6 0x38 0x0>; 895*b73660adSXianjun Jiao }; 896*b73660adSXianjun Jiao 897*b73660adSXianjun Jiao pb3 { 898*b73660adSXianjun Jiao label = "Down"; 899*b73660adSXianjun Jiao linux,code = <0x6c>; 900*b73660adSXianjun Jiao gpios = <0x6 0x39 0x0>; 901*b73660adSXianjun Jiao }; 902*b73660adSXianjun Jiao 903*b73660adSXianjun Jiao sw0 { 904*b73660adSXianjun Jiao label = "SW0"; 905*b73660adSXianjun Jiao linux,input-type = <0x5>; 906*b73660adSXianjun Jiao linux,code = <0x0>; 907*b73660adSXianjun Jiao gpios = <0x6 0x3e 0x0>; 908*b73660adSXianjun Jiao }; 909*b73660adSXianjun Jiao 910*b73660adSXianjun Jiao sw1 { 911*b73660adSXianjun Jiao label = "SW1"; 912*b73660adSXianjun Jiao linux,input-type = <0x5>; 913*b73660adSXianjun Jiao linux,code = <0x1>; 914*b73660adSXianjun Jiao gpios = <0x6 0x3f 0x0>; 915*b73660adSXianjun Jiao }; 916*b73660adSXianjun Jiao 917*b73660adSXianjun Jiao sw2 { 918*b73660adSXianjun Jiao label = "SW2"; 919*b73660adSXianjun Jiao linux,input-type = <0x5>; 920*b73660adSXianjun Jiao linux,code = <0x2>; 921*b73660adSXianjun Jiao gpios = <0x6 0x40 0x0>; 922*b73660adSXianjun Jiao }; 923*b73660adSXianjun Jiao 924*b73660adSXianjun Jiao sw3 { 925*b73660adSXianjun Jiao label = "SW3"; 926*b73660adSXianjun Jiao linux,input-type = <0x5>; 927*b73660adSXianjun Jiao linux,code = <0x3>; 928*b73660adSXianjun Jiao gpios = <0x6 0x41 0x0>; 929*b73660adSXianjun Jiao }; 930*b73660adSXianjun Jiao }; 931*b73660adSXianjun Jiao}; 932