1/dts-v1/; 2 3/ { 4 #address-cells = <0x1>; 5 #size-cells = <0x1>; 6 compatible = "xlnx,zynq-7000"; 7 interrupt-parent = <0x1>; 8 model = "Analog Devices ADRV9361-Z7035 (Z7035/AD9361)"; 9 10 cpus { 11 #address-cells = <0x1>; 12 #size-cells = <0x0>; 13 14 cpu@0 { 15 compatible = "arm,cortex-a9"; 16 device_type = "cpu"; 17 reg = <0x0>; 18 clocks = <0x2 0x3>; 19 clock-latency = <0x3e8>; 20 cpu0-supply = <0x3>; 21 operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>; 22 }; 23 24 cpu@1 { 25 compatible = "arm,cortex-a9"; 26 device_type = "cpu"; 27 reg = <0x1>; 28 clocks = <0x2 0x3>; 29 }; 30 }; 31 32 fpga-full { 33 compatible = "fpga-region"; 34 fpga-mgr = <0x4>; 35 #address-cells = <0x1>; 36 #size-cells = <0x1>; 37 ranges; 38 }; 39 40 pmu@f8891000 { 41 compatible = "arm,cortex-a9-pmu"; 42 interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>; 43 interrupt-parent = <0x1>; 44 reg = <0xf8891000 0x1000 0xf8893000 0x1000>; 45 }; 46 47 fixedregulator { 48 compatible = "regulator-fixed"; 49 regulator-name = "VCCPINT"; 50 regulator-min-microvolt = <0xf4240>; 51 regulator-max-microvolt = <0xf4240>; 52 regulator-boot-on; 53 regulator-always-on; 54 linux,phandle = <0x3>; 55 phandle = <0x3>; 56 }; 57 58 amba { 59 u-boot,dm-pre-reloc; 60 compatible = "simple-bus"; 61 #address-cells = <0x1>; 62 #size-cells = <0x1>; 63 interrupt-parent = <0x1>; 64 ranges; 65 66 adc@f8007100 { 67 compatible = "xlnx,zynq-xadc-1.00.a"; 68 reg = <0xf8007100 0x20>; 69 interrupts = <0x0 0x7 0x4>; 70 interrupt-parent = <0x1>; 71 clocks = <0x2 0xc>; 72 }; 73 74 can@e0008000 { 75 compatible = "xlnx,zynq-can-1.0"; 76 status = "disabled"; 77 clocks = <0x2 0x13 0x2 0x24>; 78 clock-names = "can_clk", "pclk"; 79 reg = <0xe0008000 0x1000>; 80 interrupts = <0x0 0x1c 0x4>; 81 interrupt-parent = <0x1>; 82 tx-fifo-depth = <0x40>; 83 rx-fifo-depth = <0x40>; 84 }; 85 86 can@e0009000 { 87 compatible = "xlnx,zynq-can-1.0"; 88 status = "disabled"; 89 clocks = <0x2 0x14 0x2 0x25>; 90 clock-names = "can_clk", "pclk"; 91 reg = <0xe0009000 0x1000>; 92 interrupts = <0x0 0x33 0x4>; 93 interrupt-parent = <0x1>; 94 tx-fifo-depth = <0x40>; 95 rx-fifo-depth = <0x40>; 96 }; 97 98 gpio@e000a000 { 99 compatible = "xlnx,zynq-gpio-1.0"; 100 #gpio-cells = <0x2>; 101 clocks = <0x2 0x2a>; 102 gpio-controller; 103 interrupt-controller; 104 #interrupt-cells = <0x2>; 105 interrupt-parent = <0x1>; 106 interrupts = <0x0 0x14 0x4>; 107 reg = <0xe000a000 0x1000>; 108 linux,phandle = <0x6>; 109 phandle = <0x6>; 110 }; 111 112 i2c@e0004000 { 113 compatible = "cdns,i2c-r1p10"; 114 status = "disabled"; 115 clocks = <0x2 0x26>; 116 interrupt-parent = <0x1>; 117 interrupts = <0x0 0x19 0x4>; 118 reg = <0xe0004000 0x1000>; 119 #address-cells = <0x1>; 120 #size-cells = <0x0>; 121 }; 122 123 i2c@e0005000 { 124 compatible = "cdns,i2c-r1p10"; 125 status = "disabled"; 126 clocks = <0x2 0x27>; 127 interrupt-parent = <0x1>; 128 interrupts = <0x0 0x30 0x4>; 129 reg = <0xe0005000 0x1000>; 130 #address-cells = <0x1>; 131 #size-cells = <0x0>; 132 }; 133 134 interrupt-controller@f8f01000 { 135 compatible = "arm,cortex-a9-gic"; 136 #interrupt-cells = <0x3>; 137 interrupt-controller; 138 reg = <0xf8f01000 0x1000 0xf8f00100 0x100>; 139 linux,phandle = <0x1>; 140 phandle = <0x1>; 141 }; 142 143 cache-controller@f8f02000 { 144 compatible = "arm,pl310-cache"; 145 reg = <0xf8f02000 0x1000>; 146 interrupts = <0x0 0x2 0x4>; 147 arm,data-latency = <0x3 0x2 0x2>; 148 arm,tag-latency = <0x2 0x2 0x2>; 149 cache-unified; 150 cache-level = <0x2>; 151 }; 152 153 memory-controller@f8006000 { 154 compatible = "xlnx,zynq-ddrc-a05"; 155 reg = <0xf8006000 0x1000>; 156 }; 157 158 ocmc@f800c000 { 159 compatible = "xlnx,zynq-ocmc-1.0"; 160 interrupt-parent = <0x1>; 161 interrupts = <0x0 0x3 0x4>; 162 reg = <0xf800c000 0x1000>; 163 }; 164 165 serial@e0000000 { 166 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 167 status = "disabled"; 168 clocks = <0x2 0x17 0x2 0x28>; 169 clock-names = "uart_clk", "pclk"; 170 reg = <0xe0000000 0x1000>; 171 interrupts = <0x0 0x1b 0x4>; 172 }; 173 174 serial@e0001000 { 175 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 176 status = "okay"; 177 clocks = <0x2 0x18 0x2 0x29>; 178 clock-names = "uart_clk", "pclk"; 179 reg = <0xe0001000 0x1000>; 180 interrupts = <0x0 0x32 0x4>; 181 }; 182 183 spi@e0006000 { 184 compatible = "xlnx,zynq-spi-r1p6"; 185 reg = <0xe0006000 0x1000>; 186 status = "okay"; 187 interrupt-parent = <0x1>; 188 interrupts = <0x0 0x1a 0x4>; 189 clocks = <0x2 0x19 0x2 0x22>; 190 clock-names = "ref_clk", "pclk"; 191 #address-cells = <0x1>; 192 #size-cells = <0x0>; 193 194 ad9361-phy@0 { 195 #address-cells = <0x1>; 196 #size-cells = <0x0>; 197 #clock-cells = <0x1>; 198 compatible = "adi,ad9361"; 199 reg = <0x0>; 200 spi-cpha; 201 spi-max-frequency = <0x989680>; 202 clocks = <0x5 0x0>; 203 clock-names = "ad9361_ext_refclk"; 204 clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; 205 adi,digital-interface-tune-skip-mode = <0x0>; 206 adi,pp-tx-swap-enable; 207 adi,pp-rx-swap-enable; 208 adi,rx-frame-pulse-mode-enable; 209 adi,lvds-mode-enable; 210 adi,lvds-bias-mV = <0x96>; 211 adi,lvds-rx-onchip-termination-enable; 212 adi,rx-data-delay = <0x4>; 213 adi,tx-fb-clock-delay = <0x7>; 214 adi,xo-disable-use-ext-refclk-enable; 215 adi,2rx-2tx-mode-enable; 216 adi,frequency-division-duplex-mode-enable; 217 adi,rx-rf-port-input-select = <0x0>; 218 adi,tx-rf-port-input-select = <0x0>; 219 adi,tx-attenuation-mdB = <0x2710>; 220 adi,rf-rx-bandwidth-hz = <0x112a880>; 221 adi,rf-tx-bandwidth-hz = <0x112a880>; 222 adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>; 223 adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>; 224 adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 225 adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 226 adi,gc-rx1-mode = <0x2>; 227 adi,gc-rx2-mode = <0x2>; 228 adi,gc-adc-ovr-sample-size = <0x4>; 229 adi,gc-adc-small-overload-thresh = <0x2f>; 230 adi,gc-adc-large-overload-thresh = <0x3a>; 231 adi,gc-lmt-overload-high-thresh = <0x320>; 232 adi,gc-lmt-overload-low-thresh = <0x2c0>; 233 adi,gc-dec-pow-measurement-duration = <0x2000>; 234 adi,gc-low-power-thresh = <0x18>; 235 adi,mgc-inc-gain-step = <0x2>; 236 adi,mgc-dec-gain-step = <0x2>; 237 adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>; 238 adi,agc-attack-delay-extra-margin-us = <0x1>; 239 adi,agc-outer-thresh-high = <0x5>; 240 adi,agc-outer-thresh-high-dec-steps = <0x2>; 241 adi,agc-inner-thresh-high = <0xa>; 242 adi,agc-inner-thresh-high-dec-steps = <0x1>; 243 adi,agc-inner-thresh-low = <0xc>; 244 adi,agc-inner-thresh-low-inc-steps = <0x1>; 245 adi,agc-outer-thresh-low = <0x12>; 246 adi,agc-outer-thresh-low-inc-steps = <0x2>; 247 adi,agc-adc-small-overload-exceed-counter = <0xa>; 248 adi,agc-adc-large-overload-exceed-counter = <0xa>; 249 adi,agc-adc-large-overload-inc-steps = <0x2>; 250 adi,agc-lmt-overload-large-exceed-counter = <0xa>; 251 adi,agc-lmt-overload-small-exceed-counter = <0xa>; 252 adi,agc-lmt-overload-large-inc-steps = <0x2>; 253 adi,agc-gain-update-interval-us = <0x3e8>; 254 adi,fagc-dec-pow-measurement-duration = <0x40>; 255 adi,fagc-lp-thresh-increment-steps = <0x1>; 256 adi,fagc-lp-thresh-increment-time = <0x5>; 257 adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>; 258 adi,fagc-final-overrange-count = <0x3>; 259 adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>; 260 adi,fagc-lmt-final-settling-steps = <0x1>; 261 adi,fagc-lock-level = <0xa>; 262 adi,fagc-lock-level-gain-increase-upper-limit = <0x5>; 263 adi,fagc-lock-level-lmt-gain-increase-enable; 264 adi,fagc-lpf-final-settling-steps = <0x1>; 265 adi,fagc-optimized-gain-offset = <0x5>; 266 adi,fagc-power-measurement-duration-in-state5 = <0x40>; 267 adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable; 268 adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>; 269 adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable; 270 adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>; 271 adi,fagc-rst-gla-large-adc-overload-enable; 272 adi,fagc-rst-gla-large-lmt-overload-enable; 273 adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>; 274 adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable; 275 adi,fagc-state-wait-time-ns = <0x104>; 276 adi,fagc-use-last-lock-level-for-set-gain-enable; 277 adi,rssi-restart-mode = <0x3>; 278 adi,rssi-delay = <0x1>; 279 adi,rssi-wait = <0x1>; 280 adi,rssi-duration = <0x3e8>; 281 adi,ctrl-outs-index = <0x0>; 282 adi,ctrl-outs-enable-mask = <0xff>; 283 adi,temp-sense-measurement-interval-ms = <0x3e8>; 284 adi,temp-sense-offset-signed = <0xce>; 285 adi,temp-sense-periodic-measurement-enable; 286 adi,aux-dac-manual-mode-enable; 287 adi,aux-dac1-default-value-mV = <0x0>; 288 adi,aux-dac1-rx-delay-us = <0x0>; 289 adi,aux-dac1-tx-delay-us = <0x0>; 290 adi,aux-dac2-default-value-mV = <0x0>; 291 adi,aux-dac2-rx-delay-us = <0x0>; 292 adi,aux-dac2-tx-delay-us = <0x0>; 293 en_agc-gpios = <0x6 0x62 0x0>; 294 sync-gpios = <0x6 0x63 0x0>; 295 reset-gpios = <0x6 0x64 0x0>; 296 enable-gpios = <0x6 0x65 0x0>; 297 txnrx-gpios = <0x6 0x66 0x0>; 298 linux,phandle = <0xc>; 299 phandle = <0xc>; 300 }; 301 }; 302 303 spi@e0007000 { 304 compatible = "xlnx,zynq-spi-r1p6"; 305 reg = <0xe0007000 0x1000>; 306 status = "disabled"; 307 interrupt-parent = <0x1>; 308 interrupts = <0x0 0x31 0x4>; 309 clocks = <0x2 0x1a 0x2 0x23>; 310 clock-names = "ref_clk", "pclk"; 311 #address-cells = <0x1>; 312 #size-cells = <0x0>; 313 }; 314 315 spi@e000d000 { 316 clock-names = "ref_clk", "pclk"; 317 clocks = <0x2 0xa 0x2 0x2b>; 318 compatible = "xlnx,zynq-qspi-1.0"; 319 status = "okay"; 320 interrupt-parent = <0x1>; 321 interrupts = <0x0 0x13 0x4>; 322 reg = <0xe000d000 0x1000>; 323 #address-cells = <0x1>; 324 #size-cells = <0x0>; 325 is-dual = <0x0>; 326 num-cs = <0x1>; 327 328 ps7-qspi@0 { 329 #address-cells = <0x1>; 330 #size-cells = <0x1>; 331 spi-tx-bus-width = <0x1>; 332 spi-rx-bus-width = <0x4>; 333 compatible = "n25q256a", "jedec,spi-nor"; 334 reg = <0x0>; 335 spi-max-frequency = <0x2faf080>; 336 337 partition@qspi-fsbl-uboot { 338 label = "qspi-fsbl-uboot"; 339 reg = <0x0 0xe0000>; 340 }; 341 342 partition@qspi-uboot-env { 343 label = "qspi-uboot-env"; 344 reg = <0xe0000 0x20000>; 345 }; 346 347 partition@qspi-linux { 348 label = "qspi-linux"; 349 reg = <0x100000 0x500000>; 350 }; 351 352 partition@qspi-device-tree { 353 label = "qspi-device-tree"; 354 reg = <0x600000 0x20000>; 355 }; 356 357 partition@qspi-rootfs { 358 label = "qspi-rootfs"; 359 reg = <0x620000 0xce0000>; 360 }; 361 362 partition@qspi-bitstream { 363 label = "qspi-bitstream"; 364 reg = <0x1300000 0xd00000>; 365 }; 366 }; 367 }; 368 369 memory-controller@e000e000 { 370 #address-cells = <0x1>; 371 #size-cells = <0x1>; 372 status = "disabled"; 373 clock-names = "memclk", "aclk"; 374 clocks = <0x2 0xb 0x2 0x2c>; 375 compatible = "arm,pl353-smc-r2p1"; 376 interrupt-parent = <0x1>; 377 interrupts = <0x0 0x12 0x4>; 378 ranges; 379 reg = <0xe000e000 0x1000>; 380 381 flash@e1000000 { 382 status = "disabled"; 383 compatible = "arm,pl353-nand-r2p1"; 384 reg = <0xe1000000 0x1000000>; 385 #address-cells = <0x1>; 386 #size-cells = <0x1>; 387 }; 388 389 flash@e2000000 { 390 status = "disabled"; 391 compatible = "cfi-flash"; 392 reg = <0xe2000000 0x2000000>; 393 #address-cells = <0x1>; 394 #size-cells = <0x1>; 395 }; 396 }; 397 398 ethernet@e000b000 { 399 compatible = "cdns,zynq-gem", "cdns,gem"; 400 reg = <0xe000b000 0x1000>; 401 status = "okay"; 402 interrupts = <0x0 0x16 0x4>; 403 clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>; 404 clock-names = "pclk", "hclk", "tx_clk"; 405 #address-cells = <0x1>; 406 #size-cells = <0x0>; 407 phy-handle = <0x7>; 408 phy-mode = "rgmii-id"; 409 410 phy@0 { 411 device_type = "ethernet-phy"; 412 reg = <0x0>; 413 marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>; 414 linux,phandle = <0x7>; 415 phandle = <0x7>; 416 }; 417 }; 418 419 ethernet@e000c000 { 420 compatible = "cdns,zynq-gem", "cdns,gem"; 421 reg = <0xe000c000 0x1000>; 422 status = "disabled"; 423 interrupts = <0x0 0x2d 0x4>; 424 clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>; 425 clock-names = "pclk", "hclk", "tx_clk"; 426 #address-cells = <0x1>; 427 #size-cells = <0x0>; 428 }; 429 430 sdhci@e0100000 { 431 compatible = "arasan,sdhci-8.9a"; 432 status = "okay"; 433 clock-names = "clk_xin", "clk_ahb"; 434 clocks = <0x2 0x15 0x2 0x20>; 435 interrupt-parent = <0x1>; 436 interrupts = <0x0 0x18 0x4>; 437 reg = <0xe0100000 0x1000>; 438 broken-adma2; 439 disable-wp; 440 }; 441 442 sdhci@e0101000 { 443 compatible = "arasan,sdhci-8.9a"; 444 status = "disabled"; 445 clock-names = "clk_xin", "clk_ahb"; 446 clocks = <0x2 0x16 0x2 0x21>; 447 interrupt-parent = <0x1>; 448 interrupts = <0x0 0x2f 0x4>; 449 reg = <0xe0101000 0x1000>; 450 broken-adma2; 451 }; 452 453 slcr@f8000000 { 454 #address-cells = <0x1>; 455 #size-cells = <0x1>; 456 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; 457 reg = <0xf8000000 0x1000>; 458 ranges; 459 linux,phandle = <0x8>; 460 phandle = <0x8>; 461 462 clkc@100 { 463 #clock-cells = <0x1>; 464 compatible = "xlnx,ps7-clkc"; 465 fclk-enable = <0xf>; 466 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; 467 reg = <0x100 0x100>; 468 ps-clk-frequency = <0x1fca055>; 469 linux,phandle = <0x2>; 470 phandle = <0x2>; 471 }; 472 473 rstc@200 { 474 compatible = "xlnx,zynq-reset"; 475 reg = <0x200 0x48>; 476 #reset-cells = <0x1>; 477 syscon = <0x8>; 478 }; 479 480 pinctrl@700 { 481 compatible = "xlnx,pinctrl-zynq"; 482 reg = <0x700 0x200>; 483 syscon = <0x8>; 484 }; 485 }; 486 487 dmac@f8003000 { 488 compatible = "arm,pl330", "arm,primecell"; 489 reg = <0xf8003000 0x1000>; 490 interrupt-parent = <0x1>; 491 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; 492 interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>; 493 #dma-cells = <0x1>; 494 #dma-channels = <0x8>; 495 #dma-requests = <0x4>; 496 clocks = <0x2 0x1b>; 497 clock-names = "apb_pclk"; 498 }; 499 500 devcfg@f8007000 { 501 compatible = "xlnx,zynq-devcfg-1.0"; 502 interrupt-parent = <0x1>; 503 interrupts = <0x0 0x8 0x4>; 504 reg = <0xf8007000 0x100>; 505 clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>; 506 clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; 507 syscon = <0x8>; 508 linux,phandle = <0x4>; 509 phandle = <0x4>; 510 }; 511 512 efuse@f800d000 { 513 compatible = "xlnx,zynq-efuse"; 514 reg = <0xf800d000 0x20>; 515 }; 516 517 timer@f8f00200 { 518 compatible = "arm,cortex-a9-global-timer"; 519 reg = <0xf8f00200 0x20>; 520 interrupts = <0x1 0xb 0x301>; 521 interrupt-parent = <0x1>; 522 clocks = <0x2 0x4>; 523 }; 524 525 timer@f8001000 { 526 interrupt-parent = <0x1>; 527 interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>; 528 compatible = "cdns,ttc"; 529 clocks = <0x2 0x6>; 530 reg = <0xf8001000 0x1000>; 531 }; 532 533 timer@f8002000 { 534 interrupt-parent = <0x1>; 535 interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>; 536 compatible = "cdns,ttc"; 537 clocks = <0x2 0x6>; 538 reg = <0xf8002000 0x1000>; 539 }; 540 541 timer@f8f00600 { 542 interrupt-parent = <0x1>; 543 interrupts = <0x1 0xd 0x301>; 544 compatible = "arm,cortex-a9-twd-timer"; 545 reg = <0xf8f00600 0x20>; 546 clocks = <0x2 0x4>; 547 }; 548 549 usb@e0002000 { 550 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 551 status = "okay"; 552 clocks = <0x2 0x1c>; 553 interrupt-parent = <0x1>; 554 interrupts = <0x0 0x15 0x4>; 555 reg = <0xe0002000 0x1000>; 556 phy_type = "ulpi"; 557 dr_mode = "host"; 558 xlnx,phy-reset-gpio = <0x6 0x7 0x0>; 559 }; 560 561 usb@e0003000 { 562 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 563 status = "disabled"; 564 clocks = <0x2 0x1d>; 565 interrupt-parent = <0x1>; 566 interrupts = <0x0 0x2c 0x4>; 567 reg = <0xe0003000 0x1000>; 568 phy_type = "ulpi"; 569 }; 570 571 watchdog@f8005000 { 572 clocks = <0x2 0x2d>; 573 compatible = "cdns,wdt-r1p2"; 574 interrupt-parent = <0x1>; 575 interrupts = <0x0 0x9 0x1>; 576 reg = <0xf8005000 0x1000>; 577 timeout-sec = <0xa>; 578 }; 579 }; 580 581 aliases { 582 ethernet0 = "/amba/ethernet@e000b000"; 583 serial0 = "/amba/serial@e0001000"; 584 }; 585 586 memory { 587 device_type = "memory"; 588 reg = <0x0 0x40000000>; 589 }; 590 591 chosen { 592 linux,stdout-path = "/amba@0/uart@E0001000"; 593 }; 594 595 clocks { 596 597 clock@0 { 598 #clock-cells = <0x0>; 599 compatible = "adjustable-clock"; 600 clock-frequency = <0x2625a00>; 601 clock-accuracy = <0x30d40>; 602 clock-output-names = "XO_40MHz"; 603 linux,phandle = <0x9>; 604 phandle = <0x9>; 605 }; 606 607 clock@2 { 608 #clock-cells = <0x0>; 609 compatible = "fixed-clock"; 610 clock-frequency = <0x16e3600>; 611 clock-output-names = "24MHz"; 612 linux,phandle = <0xa>; 613 phandle = <0xa>; 614 }; 615 }; 616 617 ad9361-refclk-gpio-gate@0 { 618 #clock-cells = <0x0>; 619 compatible = "gpio-gate-clock"; 620 clocks = <0x9>; 621 enable-gpios = <0x6 0x69 0x0>; 622 clk-set-rate-parent-enable; 623 clock-output-names = "ad9361_ext_refclk"; 624 linux,phandle = <0x5>; 625 phandle = <0x5>; 626 }; 627 628 usb-ulpe-gpio-gate@0 { 629 #clock-cells = <0x0>; 630 compatible = "gpio-gate-clock"; 631 clocks = <0xa>; 632 enable-gpios = <0x6 0x9 0x1>; 633 }; 634 635 fpga-axi@0 { 636 compatible = "simple-bus"; 637 #address-cells = <0x1>; 638 #size-cells = <0x1>; 639 ranges; 640 641 i2c@41600000 { 642 compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a"; 643 reg = <0x41600000 0x10000>; 644 interrupt-parent = <0x1>; 645 interrupts = <0x0 0x3a 0x4>; 646 clocks = <0x2 0xf>; 647 clock-names = "pclk"; 648 #address-cells = <0x1>; 649 #size-cells = <0x0>; 650 651 adm1166@68 { 652 compatible = "adi,adm1166"; 653 reg = <0x68>; 654 }; 655 656 ad7291-bob@2f { 657 compatible = "adi,ad7291"; 658 reg = <0x2f>; 659 }; 660 661 eeprom@50 { 662 compatible = "at24,24c32"; 663 reg = <0x50>; 664 }; 665 }; 666 667 dma@7c400000 { 668 compatible = "adi,axi-dmac-1.00.a"; 669 reg = <0x7c400000 0x10000>; 670 #dma-cells = <0x1>; 671 interrupts = <0 57 4>; 672 clocks = <0x2 0xf 0xf>; 673 linux,phandle = <0xb>; 674 phandle = <0xb>; 675 676 adi,channels { 677 #size-cells = <0x0>; 678 #address-cells = <0x1>; 679 680 dma-channel@0 { 681 reg = <0x0>; 682 adi,source-bus-width = <0x40>; 683 adi,source-bus-type = <0x2>; 684 adi,destination-bus-width = <0x40>; 685 adi,destination-bus-type = <0x0>; 686 adi,length-width = <0x18>; 687 }; 688 }; 689 }; 690 691 dma@7c420000 { 692 compatible = "adi,axi-dmac-1.00.a"; 693 reg = <0x7c420000 0x10000>; 694 #dma-cells = <0x1>; 695 interrupts = <0 56 4>; 696 clocks = <0x2 0xf 0xf>; 697 linux,phandle = <0xd>; 698 phandle = <0xd>; 699 700 adi,channels { 701 #size-cells = <0x0>; 702 #address-cells = <0x1>; 703 704 dma-channel@0 { 705 reg = <0x0>; 706 adi,source-bus-width = <0x40>; 707 adi,source-bus-type = <0x0>; 708 adi,destination-bus-width = <0x40>; 709 adi,destination-bus-type = <0x2>; 710 adi,length-width = <0x18>; 711 adi,cyclic; 712 }; 713 }; 714 }; 715 716 sdr: sdr { 717 compatible ="sdr,sdr"; 718 dmas = <&rx_dma 0 719 &rx_dma 1 720 &tx_dma 0 721 &tx_dma 1>; 722 dma-names = "rx_dma_mm2s", "rx_dma_s2mm", "tx_dma_mm2s", "tx_dma_s2mm"; 723 interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt0", "tx_itrpt1"; 724 interrupt-parent = <1>; 725 interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>; 726 } ; 727 728 axidmatest_1: axidmatest@1 { 729 compatible ="xlnx,axi-dma-test-1.00.a"; 730 dmas = <&rx_dma 0 731 &rx_dma 1>; 732 dma-names = "axidma0", "axidma1"; 733 } ; 734 735 tx_dma: dma@80400000 { 736 #dma-cells = <1>; 737 clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; 738 clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 739 compatible = "xlnx,axi-dma-1.00.a"; 740 interrupt-names = "mm2s_introut", "s2mm_introut"; 741 interrupt-parent = <1>; 742 interrupts = <0 35 4 0 36 4>; 743 reg = <0x80400000 0x10000>; 744 xlnx,addrwidth = <0x20>; 745 xlnx,include-sg ; 746 xlnx,sg-length-width = <0xe>; 747 dma-channel@80400000 { 748 compatible = "xlnx,axi-dma-mm2s-channel"; 749 dma-channels = <0x1>; 750 interrupts = <0 35 4>; 751 xlnx,datawidth = <0x40>; 752 xlnx,device-id = <0x0>; 753 }; 754 dma-channel@80400030 { 755 compatible = "xlnx,axi-dma-s2mm-channel"; 756 dma-channels = <0x1>; 757 interrupts = <0 36 4>; 758 xlnx,datawidth = <0x40>; 759 xlnx,device-id = <0x0>; 760 }; 761 }; 762 763 rx_dma: dma@80410000 { 764 #dma-cells = <1>; 765 clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; 766 clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 767 compatible = "xlnx,axi-dma-1.00.a"; 768 //dma-coherent ; 769 interrupt-names = "mm2s_introut", "s2mm_introut"; 770 interrupt-parent = <1>; 771 interrupts = <0 31 4 0 32 4>; 772 reg = <0x80410000 0x10000>; 773 xlnx,addrwidth = <0x20>; 774 xlnx,include-sg ; 775 xlnx,sg-length-width = <0xe>; 776 dma-channel@80410000 { 777 compatible = "xlnx,axi-dma-mm2s-channel"; 778 dma-channels = <0x1>; 779 interrupts = <0 31 4>; 780 xlnx,datawidth = <0x40>; 781 xlnx,device-id = <0x1>; 782 }; 783 dma-channel@80410030 { 784 compatible = "xlnx,axi-dma-s2mm-channel"; 785 dma-channels = <0x1>; 786 interrupts = <0 32 4>; 787 xlnx,datawidth = <0x40>; 788 xlnx,device-id = <0x1>; 789 }; 790 }; 791 792 tx_intf_0: tx_intf@83c00000 { 793 clock-names = "s00_axi_aclk", "s00_axis_aclk", "s01_axis_aclk", "m00_axis_aclk"; 794 clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 795 compatible = "sdr,tx_intf"; 796 interrupt-names = "tx_itrpt0", "tx_itrpt1"; 797 interrupt-parent = <1>; 798 interrupts = <0 33 1 0 34 1>; 799 reg = <0x83c00000 0x10000>; 800 xlnx,s00-axi-addr-width = <0x7>; 801 xlnx,s00-axi-data-width = <0x20>; 802 }; 803 804 rx_intf_0: rx_intf@83c20000 { 805 clock-names = "s00_axi_aclk", "s00_axis_aclk", "m00_axis_aclk"; 806 clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 807 compatible = "sdr,rx_intf"; 808 interrupt-names = "not_valid_anymore", "rx_pkt_intr"; 809 interrupt-parent = <1>; 810 interrupts = <0 29 1 0 30 1>; 811 reg = <0x83c20000 0x10000>; 812 xlnx,s00-axi-addr-width = <0x7>; 813 xlnx,s00-axi-data-width = <0x20>; 814 }; 815 816 openofdm_tx_0: openofdm_tx@83c10000 { 817 clock-names = "clk"; 818 clocks = <0x2 0x11>; 819 compatible = "sdr,openofdm_tx"; 820 reg = <0x83c10000 0x10000>; 821 }; 822 823 openofdm_rx_0: openofdm_rx@83c30000 { 824 clock-names = "clk"; 825 clocks = <0x2 0x11>; 826 compatible = "sdr,openofdm_rx"; 827 reg = <0x83c30000 0x10000>; 828 }; 829 830 xpu_0: xpu@83c40000 { 831 clock-names = "s00_axi_aclk"; 832 clocks = <0x2 0x11>; 833 compatible = "sdr,xpu"; 834 reg = <0x83c40000 0x10000>; 835 }; 836 837 cf-ad9361-lpc@79020000 { 838 compatible = "adi,axi-ad9361-6.00.a"; 839 reg = <0x79020000 0x6000>; 840 dmas = <0xb 0x0>; 841 dma-names = "rx"; 842 spibus-connected = <0xc>; 843 }; 844 845 cf-ad9361-dds-core-lpc@79024000 { 846 compatible = "adi,axi-ad9361-dds-6.00.a"; 847 reg = <0x79024000 0x1000>; 848 clocks = <0xc 0xd>; 849 clock-names = "sampl_clk"; 850 dmas = <0xd 0x0>; 851 dma-names = "tx"; 852 }; 853 854 mwipcore@43c00000 { 855 compatible = "mathworks,mwipcore-axi4lite-v1.00"; 856 reg = <0x43c00000 0xffff>; 857 }; 858 }; 859 860 leds { 861 compatible = "gpio-leds"; 862 863 led0 { 864 label = "led0:green"; 865 gpios = <0x6 0x3a 0x0>; 866 }; 867 868 led1 { 869 label = "led1:green"; 870 gpios = <0x6 0x3b 0x0>; 871 }; 872 873 led2 { 874 label = "led2:green"; 875 gpios = <0x6 0x3c 0x0>; 876 }; 877 878 led3 { 879 label = "led3:green"; 880 gpios = <0x6 0x3d 0x0>; 881 }; 882 }; 883 884 gpio_keys { 885 compatible = "gpio-keys"; 886 #address-cells = <0x1>; 887 #size-cells = <0x0>; 888 autorepeat; 889 890 pb0 { 891 label = "Left"; 892 linux,code = <0x69>; 893 gpios = <0x6 0x36 0x0>; 894 }; 895 896 pb1 { 897 label = "Right"; 898 linux,code = <0x6a>; 899 gpios = <0x6 0x37 0x0>; 900 }; 901 902 pb2 { 903 label = "Up"; 904 linux,code = <0x67>; 905 gpios = <0x6 0x38 0x0>; 906 }; 907 908 pb3 { 909 label = "Down"; 910 linux,code = <0x6c>; 911 gpios = <0x6 0x39 0x0>; 912 }; 913 914 sw0 { 915 label = "SW0"; 916 linux,input-type = <0x5>; 917 linux,code = <0x0>; 918 gpios = <0x6 0x3e 0x0>; 919 }; 920 921 sw1 { 922 label = "SW1"; 923 linux,input-type = <0x5>; 924 linux,code = <0x1>; 925 gpios = <0x6 0x3f 0x0>; 926 }; 927 928 sw2 { 929 label = "SW2"; 930 linux,input-type = <0x5>; 931 linux,code = <0x2>; 932 gpios = <0x6 0x40 0x0>; 933 }; 934 935 sw3 { 936 label = "SW3"; 937 linux,input-type = <0x5>; 938 linux,code = <0x3>; 939 gpios = <0x6 0x41 0x0>; 940 }; 941 }; 942}; 943