1/dts-v1/; 2 3/ { 4 #address-cells = <0x1>; 5 #size-cells = <0x1>; 6 compatible = "xlnx,zynq-7000"; 7 interrupt-parent = <0x1>; 8 model = "Analog Devices ADRV9361-Z7035 (Z7035/AD9361)"; 9 10 cpus { 11 #address-cells = <0x1>; 12 #size-cells = <0x0>; 13 14 cpu@0 { 15 compatible = "arm,cortex-a9"; 16 device_type = "cpu"; 17 reg = <0x0>; 18 clocks = <0x2 0x3>; 19 clock-latency = <0x3e8>; 20 cpu0-supply = <0x3>; 21 operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>; 22 }; 23 24 cpu@1 { 25 compatible = "arm,cortex-a9"; 26 device_type = "cpu"; 27 reg = <0x1>; 28 clocks = <0x2 0x3>; 29 }; 30 }; 31 32 fpga-full { 33 compatible = "fpga-region"; 34 fpga-mgr = <0x4>; 35 #address-cells = <0x1>; 36 #size-cells = <0x1>; 37 ranges; 38 }; 39 40 pmu@f8891000 { 41 compatible = "arm,cortex-a9-pmu"; 42 interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>; 43 interrupt-parent = <0x1>; 44 reg = <0xf8891000 0x1000 0xf8893000 0x1000>; 45 }; 46 47 fixedregulator { 48 compatible = "regulator-fixed"; 49 regulator-name = "VCCPINT"; 50 regulator-min-microvolt = <0xf4240>; 51 regulator-max-microvolt = <0xf4240>; 52 regulator-boot-on; 53 regulator-always-on; 54 linux,phandle = <0x3>; 55 phandle = <0x3>; 56 }; 57 58 amba { 59 u-boot,dm-pre-reloc; 60 compatible = "simple-bus"; 61 #address-cells = <0x1>; 62 #size-cells = <0x1>; 63 interrupt-parent = <0x1>; 64 ranges; 65 66 adc@f8007100 { 67 compatible = "xlnx,zynq-xadc-1.00.a"; 68 reg = <0xf8007100 0x20>; 69 interrupts = <0x0 0x7 0x4>; 70 interrupt-parent = <0x1>; 71 clocks = <0x2 0xc>; 72 }; 73 74 can@e0008000 { 75 compatible = "xlnx,zynq-can-1.0"; 76 status = "disabled"; 77 clocks = <0x2 0x13 0x2 0x24>; 78 clock-names = "can_clk", "pclk"; 79 reg = <0xe0008000 0x1000>; 80 interrupts = <0x0 0x1c 0x4>; 81 interrupt-parent = <0x1>; 82 tx-fifo-depth = <0x40>; 83 rx-fifo-depth = <0x40>; 84 }; 85 86 can@e0009000 { 87 compatible = "xlnx,zynq-can-1.0"; 88 status = "disabled"; 89 clocks = <0x2 0x14 0x2 0x25>; 90 clock-names = "can_clk", "pclk"; 91 reg = <0xe0009000 0x1000>; 92 interrupts = <0x0 0x33 0x4>; 93 interrupt-parent = <0x1>; 94 tx-fifo-depth = <0x40>; 95 rx-fifo-depth = <0x40>; 96 }; 97 98 gpio@e000a000 { 99 compatible = "xlnx,zynq-gpio-1.0"; 100 #gpio-cells = <0x2>; 101 clocks = <0x2 0x2a>; 102 gpio-controller; 103 interrupt-controller; 104 #interrupt-cells = <0x2>; 105 interrupt-parent = <0x1>; 106 interrupts = <0x0 0x14 0x4>; 107 reg = <0xe000a000 0x1000>; 108 linux,phandle = <0x6>; 109 phandle = <0x6>; 110 }; 111 112 i2c@e0004000 { 113 compatible = "cdns,i2c-r1p10"; 114 status = "disabled"; 115 clocks = <0x2 0x26>; 116 interrupt-parent = <0x1>; 117 interrupts = <0x0 0x19 0x4>; 118 reg = <0xe0004000 0x1000>; 119 #address-cells = <0x1>; 120 #size-cells = <0x0>; 121 }; 122 123 i2c@e0005000 { 124 compatible = "cdns,i2c-r1p10"; 125 status = "disabled"; 126 clocks = <0x2 0x27>; 127 interrupt-parent = <0x1>; 128 interrupts = <0x0 0x30 0x4>; 129 reg = <0xe0005000 0x1000>; 130 #address-cells = <0x1>; 131 #size-cells = <0x0>; 132 }; 133 134 interrupt-controller@f8f01000 { 135 compatible = "arm,cortex-a9-gic"; 136 #interrupt-cells = <0x3>; 137 interrupt-controller; 138 reg = <0xf8f01000 0x1000 0xf8f00100 0x100>; 139 linux,phandle = <0x1>; 140 phandle = <0x1>; 141 }; 142 143 cache-controller@f8f02000 { 144 compatible = "arm,pl310-cache"; 145 reg = <0xf8f02000 0x1000>; 146 interrupts = <0x0 0x2 0x4>; 147 arm,data-latency = <0x3 0x2 0x2>; 148 arm,tag-latency = <0x2 0x2 0x2>; 149 cache-unified; 150 cache-level = <0x2>; 151 }; 152 153 memory-controller@f8006000 { 154 compatible = "xlnx,zynq-ddrc-a05"; 155 reg = <0xf8006000 0x1000>; 156 }; 157 158 ocmc@f800c000 { 159 compatible = "xlnx,zynq-ocmc-1.0"; 160 interrupt-parent = <0x1>; 161 interrupts = <0x0 0x3 0x4>; 162 reg = <0xf800c000 0x1000>; 163 }; 164 165 serial@e0000000 { 166 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 167 status = "disabled"; 168 clocks = <0x2 0x17 0x2 0x28>; 169 clock-names = "uart_clk", "pclk"; 170 reg = <0xe0000000 0x1000>; 171 interrupts = <0x0 0x1b 0x4>; 172 }; 173 174 serial@e0001000 { 175 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 176 status = "okay"; 177 clocks = <0x2 0x18 0x2 0x29>; 178 clock-names = "uart_clk", "pclk"; 179 reg = <0xe0001000 0x1000>; 180 interrupts = <0x0 0x32 0x4>; 181 }; 182 183 spi@e0006000 { 184 compatible = "xlnx,zynq-spi-r1p6"; 185 reg = <0xe0006000 0x1000>; 186 status = "okay"; 187 interrupt-parent = <0x1>; 188 interrupts = <0x0 0x1a 0x4>; 189 clocks = <0x2 0x19 0x2 0x22>; 190 clock-names = "ref_clk", "pclk"; 191 #address-cells = <0x1>; 192 #size-cells = <0x0>; 193 194 ad9361-phy@0 { 195 #address-cells = <0x1>; 196 #size-cells = <0x0>; 197 #clock-cells = <0x1>; 198 compatible = "adi,ad9361"; 199 reg = <0x0>; 200 spi-cpha; 201 spi-max-frequency = <0x989680>; 202 clocks = <0x5 0x0>; 203 clock-names = "ad9361_ext_refclk"; 204 clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; 205 adi,digital-interface-tune-skip-mode = <0x0>; 206 adi,pp-tx-swap-enable; 207 adi,pp-rx-swap-enable; 208 adi,rx-frame-pulse-mode-enable; 209 adi,lvds-mode-enable; 210 adi,lvds-bias-mV = <0x96>; 211 adi,lvds-rx-onchip-termination-enable; 212 adi,rx-data-delay = <0x4>; 213 adi,tx-fb-clock-delay = <0x7>; 214 adi,xo-disable-use-ext-refclk-enable; 215 adi,2rx-2tx-mode-enable; 216 adi,frequency-division-duplex-mode-enable; 217 adi,rx-rf-port-input-select = <0x0>; 218 adi,tx-rf-port-input-select = <0x0>; 219 adi,tx-attenuation-mdB = <0x2710>; 220 adi,tx-lo-powerdown-managed-enable; 221 adi,rf-rx-bandwidth-hz = <0x112a880>; 222 adi,rf-tx-bandwidth-hz = <0x112a880>; 223 adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>; 224 adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>; 225 adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 226 adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 227 adi,gc-rx1-mode = <0x2>; 228 adi,gc-rx2-mode = <0x2>; 229 adi,gc-adc-ovr-sample-size = <0x4>; 230 adi,gc-adc-small-overload-thresh = <0x2f>; 231 adi,gc-adc-large-overload-thresh = <0x3a>; 232 adi,gc-lmt-overload-high-thresh = <0x320>; 233 adi,gc-lmt-overload-low-thresh = <0x2c0>; 234 adi,gc-dec-pow-measurement-duration = <0x2000>; 235 adi,gc-low-power-thresh = <0x18>; 236 adi,mgc-inc-gain-step = <0x2>; 237 adi,mgc-dec-gain-step = <0x2>; 238 adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>; 239 adi,agc-attack-delay-extra-margin-us = <0x1>; 240 adi,agc-outer-thresh-high = <0x5>; 241 adi,agc-outer-thresh-high-dec-steps = <0x2>; 242 adi,agc-inner-thresh-high = <0xa>; 243 adi,agc-inner-thresh-high-dec-steps = <0x1>; 244 adi,agc-inner-thresh-low = <0xc>; 245 adi,agc-inner-thresh-low-inc-steps = <0x1>; 246 adi,agc-outer-thresh-low = <0x12>; 247 adi,agc-outer-thresh-low-inc-steps = <0x2>; 248 adi,agc-adc-small-overload-exceed-counter = <0xa>; 249 adi,agc-adc-large-overload-exceed-counter = <0xa>; 250 adi,agc-adc-large-overload-inc-steps = <0x2>; 251 adi,agc-lmt-overload-large-exceed-counter = <0xa>; 252 adi,agc-lmt-overload-small-exceed-counter = <0xa>; 253 adi,agc-lmt-overload-large-inc-steps = <0x2>; 254 adi,agc-gain-update-interval-us = <0x3e8>; 255 adi,fagc-dec-pow-measurement-duration = <0x40>; 256 adi,fagc-lp-thresh-increment-steps = <0x1>; 257 adi,fagc-lp-thresh-increment-time = <0x5>; 258 adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>; 259 adi,fagc-final-overrange-count = <0x3>; 260 adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>; 261 adi,fagc-lmt-final-settling-steps = <0x1>; 262 adi,fagc-lock-level = <0xa>; 263 adi,fagc-lock-level-gain-increase-upper-limit = <0x5>; 264 adi,fagc-lock-level-lmt-gain-increase-enable; 265 adi,fagc-lpf-final-settling-steps = <0x1>; 266 adi,fagc-optimized-gain-offset = <0x5>; 267 adi,fagc-power-measurement-duration-in-state5 = <0x40>; 268 adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable; 269 adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>; 270 adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable; 271 adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>; 272 adi,fagc-rst-gla-large-adc-overload-enable; 273 adi,fagc-rst-gla-large-lmt-overload-enable; 274 adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>; 275 adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable; 276 adi,fagc-state-wait-time-ns = <0x104>; 277 adi,fagc-use-last-lock-level-for-set-gain-enable; 278 adi,rssi-restart-mode = <0x3>; 279 adi,rssi-delay = <0x1>; 280 adi,rssi-wait = <0x1>; 281 adi,rssi-duration = <0x3e8>; 282 adi,ctrl-outs-index = <0x0>; 283 adi,ctrl-outs-enable-mask = <0xff>; 284 adi,temp-sense-measurement-interval-ms = <0x3e8>; 285 adi,temp-sense-offset-signed = <0xce>; 286 adi,temp-sense-periodic-measurement-enable; 287 adi,aux-dac-manual-mode-enable; 288 adi,aux-dac1-default-value-mV = <0x0>; 289 adi,aux-dac1-rx-delay-us = <0x0>; 290 adi,aux-dac1-tx-delay-us = <0x0>; 291 adi,aux-dac2-default-value-mV = <0x0>; 292 adi,aux-dac2-rx-delay-us = <0x0>; 293 adi,aux-dac2-tx-delay-us = <0x0>; 294 en_agc-gpios = <0x6 0x62 0x0>; 295 sync-gpios = <0x6 0x63 0x0>; 296 reset-gpios = <0x6 0x64 0x0>; 297 enable-gpios = <0x6 0x65 0x0>; 298 txnrx-gpios = <0x6 0x66 0x0>; 299 linux,phandle = <0xc>; 300 phandle = <0xc>; 301 }; 302 }; 303 304 spi@e0007000 { 305 compatible = "xlnx,zynq-spi-r1p6"; 306 reg = <0xe0007000 0x1000>; 307 status = "disabled"; 308 interrupt-parent = <0x1>; 309 interrupts = <0x0 0x31 0x4>; 310 clocks = <0x2 0x1a 0x2 0x23>; 311 clock-names = "ref_clk", "pclk"; 312 #address-cells = <0x1>; 313 #size-cells = <0x0>; 314 }; 315 316 spi@e000d000 { 317 clock-names = "ref_clk", "pclk"; 318 clocks = <0x2 0xa 0x2 0x2b>; 319 compatible = "xlnx,zynq-qspi-1.0"; 320 status = "okay"; 321 interrupt-parent = <0x1>; 322 interrupts = <0x0 0x13 0x4>; 323 reg = <0xe000d000 0x1000>; 324 #address-cells = <0x1>; 325 #size-cells = <0x0>; 326 is-dual = <0x0>; 327 num-cs = <0x1>; 328 329 ps7-qspi@0 { 330 #address-cells = <0x1>; 331 #size-cells = <0x1>; 332 spi-tx-bus-width = <0x1>; 333 spi-rx-bus-width = <0x4>; 334 compatible = "n25q256a", "jedec,spi-nor"; 335 reg = <0x0>; 336 spi-max-frequency = <0x2faf080>; 337 338 partition@qspi-fsbl-uboot { 339 label = "qspi-fsbl-uboot"; 340 reg = <0x0 0xe0000>; 341 }; 342 343 partition@qspi-uboot-env { 344 label = "qspi-uboot-env"; 345 reg = <0xe0000 0x20000>; 346 }; 347 348 partition@qspi-linux { 349 label = "qspi-linux"; 350 reg = <0x100000 0x500000>; 351 }; 352 353 partition@qspi-device-tree { 354 label = "qspi-device-tree"; 355 reg = <0x600000 0x20000>; 356 }; 357 358 partition@qspi-rootfs { 359 label = "qspi-rootfs"; 360 reg = <0x620000 0xce0000>; 361 }; 362 363 partition@qspi-bitstream { 364 label = "qspi-bitstream"; 365 reg = <0x1300000 0xd00000>; 366 }; 367 }; 368 }; 369 370 memory-controller@e000e000 { 371 #address-cells = <0x1>; 372 #size-cells = <0x1>; 373 status = "disabled"; 374 clock-names = "memclk", "aclk"; 375 clocks = <0x2 0xb 0x2 0x2c>; 376 compatible = "arm,pl353-smc-r2p1"; 377 interrupt-parent = <0x1>; 378 interrupts = <0x0 0x12 0x4>; 379 ranges; 380 reg = <0xe000e000 0x1000>; 381 382 flash@e1000000 { 383 status = "disabled"; 384 compatible = "arm,pl353-nand-r2p1"; 385 reg = <0xe1000000 0x1000000>; 386 #address-cells = <0x1>; 387 #size-cells = <0x1>; 388 }; 389 390 flash@e2000000 { 391 status = "disabled"; 392 compatible = "cfi-flash"; 393 reg = <0xe2000000 0x2000000>; 394 #address-cells = <0x1>; 395 #size-cells = <0x1>; 396 }; 397 }; 398 399 ethernet@e000b000 { 400 compatible = "cdns,zynq-gem", "cdns,gem"; 401 reg = <0xe000b000 0x1000>; 402 status = "okay"; 403 interrupts = <0x0 0x16 0x4>; 404 clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>; 405 clock-names = "pclk", "hclk", "tx_clk"; 406 #address-cells = <0x1>; 407 #size-cells = <0x0>; 408 phy-handle = <0x7>; 409 phy-mode = "rgmii-id"; 410 411 phy@0 { 412 device_type = "ethernet-phy"; 413 reg = <0x0>; 414 marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>; 415 linux,phandle = <0x7>; 416 phandle = <0x7>; 417 }; 418 }; 419 420 ethernet@e000c000 { 421 compatible = "cdns,zynq-gem", "cdns,gem"; 422 reg = <0xe000c000 0x1000>; 423 status = "disabled"; 424 interrupts = <0x0 0x2d 0x4>; 425 clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>; 426 clock-names = "pclk", "hclk", "tx_clk"; 427 #address-cells = <0x1>; 428 #size-cells = <0x0>; 429 }; 430 431 mmc@e0100000 { 432 compatible = "arasan,sdhci-8.9a"; 433 status = "okay"; 434 clock-names = "clk_xin", "clk_ahb"; 435 clocks = <0x2 0x15 0x2 0x20>; 436 interrupt-parent = <0x1>; 437 interrupts = <0x0 0x18 0x4>; 438 reg = <0xe0100000 0x1000>; 439 disable-wp; 440 }; 441 442 mmc@e0101000 { 443 compatible = "arasan,sdhci-8.9a"; 444 status = "disabled"; 445 clock-names = "clk_xin", "clk_ahb"; 446 clocks = <0x2 0x16 0x2 0x21>; 447 interrupt-parent = <0x1>; 448 interrupts = <0x0 0x2f 0x4>; 449 reg = <0xe0101000 0x1000>; 450 }; 451 452 slcr@f8000000 { 453 u-boot,dm-pre-reloc; 454 #address-cells = <0x1>; 455 #size-cells = <0x1>; 456 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; 457 reg = <0xf8000000 0x1000>; 458 ranges; 459 linux,phandle = <0x8>; 460 phandle = <0x8>; 461 462 clkc@100 { 463 u-boot,dm-pre-reloc; 464 #clock-cells = <0x1>; 465 compatible = "xlnx,ps7-clkc"; 466 fclk-enable = <0xf>; 467 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; 468 reg = <0x100 0x100>; 469 ps-clk-frequency = <0x1fca055>; 470 linux,phandle = <0x2>; 471 phandle = <0x2>; 472 }; 473 474 rstc@200 { 475 compatible = "xlnx,zynq-reset"; 476 reg = <0x200 0x48>; 477 #reset-cells = <0x1>; 478 syscon = <0x8>; 479 }; 480 481 pinctrl@700 { 482 compatible = "xlnx,pinctrl-zynq"; 483 reg = <0x700 0x200>; 484 syscon = <0x8>; 485 }; 486 }; 487 488 dmac@f8003000 { 489 compatible = "arm,pl330", "arm,primecell"; 490 reg = <0xf8003000 0x1000>; 491 interrupt-parent = <0x1>; 492 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; 493 interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>; 494 #dma-cells = <0x1>; 495 #dma-channels = <0x8>; 496 #dma-requests = <0x4>; 497 clocks = <0x2 0x1b>; 498 clock-names = "apb_pclk"; 499 }; 500 501 devcfg@f8007000 { 502 compatible = "xlnx,zynq-devcfg-1.0"; 503 interrupt-parent = <0x1>; 504 interrupts = <0x0 0x8 0x4>; 505 reg = <0xf8007000 0x100>; 506 clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>; 507 clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; 508 syscon = <0x8>; 509 linux,phandle = <0x4>; 510 phandle = <0x4>; 511 }; 512 513 efuse@f800d000 { 514 compatible = "xlnx,zynq-efuse"; 515 reg = <0xf800d000 0x20>; 516 }; 517 518 timer@f8f00200 { 519 compatible = "arm,cortex-a9-global-timer"; 520 reg = <0xf8f00200 0x20>; 521 interrupts = <0x1 0xb 0x301>; 522 interrupt-parent = <0x1>; 523 clocks = <0x2 0x4>; 524 }; 525 526 timer@f8001000 { 527 interrupt-parent = <0x1>; 528 interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>; 529 compatible = "cdns,ttc"; 530 clocks = <0x2 0x6>; 531 reg = <0xf8001000 0x1000>; 532 }; 533 534 timer@f8002000 { 535 interrupt-parent = <0x1>; 536 interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>; 537 compatible = "cdns,ttc"; 538 clocks = <0x2 0x6>; 539 reg = <0xf8002000 0x1000>; 540 }; 541 542 timer@f8f00600 { 543 interrupt-parent = <0x1>; 544 interrupts = <0x1 0xd 0x301>; 545 compatible = "arm,cortex-a9-twd-timer"; 546 reg = <0xf8f00600 0x20>; 547 clocks = <0x2 0x4>; 548 }; 549 550 usb@e0002000 { 551 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 552 status = "okay"; 553 clocks = <0x2 0x1c>; 554 interrupt-parent = <0x1>; 555 interrupts = <0x0 0x15 0x4>; 556 reg = <0xe0002000 0x1000>; 557 phy_type = "ulpi"; 558 dr_mode = "host"; 559 xlnx,phy-reset-gpio = <0x6 0x7 0x0>; 560 }; 561 562 usb@e0003000 { 563 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 564 status = "disabled"; 565 clocks = <0x2 0x1d>; 566 interrupt-parent = <0x1>; 567 interrupts = <0x0 0x2c 0x4>; 568 reg = <0xe0003000 0x1000>; 569 phy_type = "ulpi"; 570 }; 571 572 watchdog@f8005000 { 573 clocks = <0x2 0x2d>; 574 compatible = "cdns,wdt-r1p2"; 575 interrupt-parent = <0x1>; 576 interrupts = <0x0 0x9 0x1>; 577 reg = <0xf8005000 0x1000>; 578 timeout-sec = <0xa>; 579 }; 580 }; 581 582 aliases { 583 ethernet0 = "/amba/ethernet@e000b000"; 584 serial0 = "/amba/serial@e0001000"; 585 }; 586 587 memory { 588 device_type = "memory"; 589 reg = <0x0 0x40000000>; 590 }; 591 592 chosen { 593 linux,stdout-path = "/amba@0/uart@E0001000"; 594 }; 595 596 clocks { 597 598 clock@0 { 599 #clock-cells = <0x0>; 600 compatible = "adjustable-clock"; 601 clock-frequency = <0x2625a00>; 602 clock-accuracy = <0x30d40>; 603 clock-output-names = "XO_40MHz"; 604 linux,phandle = <0x9>; 605 phandle = <0x9>; 606 }; 607 608 clock@2 { 609 #clock-cells = <0x0>; 610 compatible = "fixed-clock"; 611 clock-frequency = <0x16e3600>; 612 clock-output-names = "24MHz"; 613 linux,phandle = <0xa>; 614 phandle = <0xa>; 615 }; 616 }; 617 618 ad9361-refclk-gpio-gate@0 { 619 #clock-cells = <0x0>; 620 compatible = "gpio-gate-clock"; 621 clocks = <0x9>; 622 enable-gpios = <0x6 0x69 0x0>; 623 clk-set-rate-parent-enable; 624 clock-output-names = "ad9361_ext_refclk"; 625 linux,phandle = <0x5>; 626 phandle = <0x5>; 627 }; 628 629 usb-ulpe-gpio-gate@0 { 630 #clock-cells = <0x0>; 631 compatible = "gpio-gate-clock"; 632 clocks = <0xa>; 633 enable-gpios = <0x6 0x9 0x1>; 634 }; 635 636 fpga-axi@0 { 637 compatible = "simple-bus"; 638 #address-cells = <0x1>; 639 #size-cells = <0x1>; 640 ranges; 641 642 i2c@41600000 { 643 compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a"; 644 reg = <0x41600000 0x10000>; 645 interrupt-parent = <0x1>; 646 interrupts = <0x0 0x3a 0x4>; 647 clocks = <0x2 0xf>; 648 clock-names = "pclk"; 649 #address-cells = <0x1>; 650 #size-cells = <0x0>; 651 652 adm1166@68 { 653 compatible = "adi,adm1166"; 654 reg = <0x68>; 655 }; 656 657 ad7291-bob@2f { 658 compatible = "adi,ad7291"; 659 reg = <0x2f>; 660 }; 661 662 eeprom@50 { 663 compatible = "at24,24c32"; 664 reg = <0x50>; 665 }; 666 }; 667 668 // dma@7c400000 { 669 // compatible = "adi,axi-dmac-1.00.a"; 670 // reg = <0x7c400000 0x10000>; 671 // #dma-cells = <0x1>; 672 // interrupts = <0x0 0x39 0x0>; 673 // clocks = <0x2 0x10>; 674 // linux,phandle = <0xb>; 675 // phandle = <0xb>; 676 677 // adi,channels { 678 // #size-cells = <0x0>; 679 // #address-cells = <0x1>; 680 681 // dma-channel@0 { 682 // reg = <0x0>; 683 // adi,source-bus-width = <0x40>; 684 // adi,source-bus-type = <0x2>; 685 // adi,destination-bus-width = <0x40>; 686 // adi,destination-bus-type = <0x0>; 687 // }; 688 // }; 689 // }; 690 691 // dma@7c420000 { 692 // compatible = "adi,axi-dmac-1.00.a"; 693 // reg = <0x7c420000 0x10000>; 694 // #dma-cells = <0x1>; 695 // interrupts = <0x0 0x38 0x0>; 696 // clocks = <0x2 0x10>; 697 // linux,phandle = <0xd>; 698 // phandle = <0xd>; 699 700 // adi,channels { 701 // #size-cells = <0x0>; 702 // #address-cells = <0x1>; 703 704 // dma-channel@0 { 705 // reg = <0x0>; 706 // adi,source-bus-width = <0x40>; 707 // adi,source-bus-type = <0x0>; 708 // adi,destination-bus-width = <0x40>; 709 // adi,destination-bus-type = <0x2>; 710 // }; 711 // }; 712 // }; 713 714 sdr: sdr { 715 compatible ="sdr,sdr"; 716 dmas = <&rx_dma 1 717 &tx_dma 0>; 718 dma-names = "rx_dma_s2mm", "tx_dma_mm2s"; 719 interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt"; 720 interrupt-parent = <1>; 721 interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>; 722 } ; 723 724 axidmatest_1: axidmatest@1 { 725 compatible ="xlnx,axi-dma-test-1.00.a"; 726 dmas = <&rx_dma 0 727 &rx_dma 1>; 728 dma-names = "axidma0", "axidma1"; 729 } ; 730 731 tx_dma: dma@80400000 { 732 #dma-cells = <1>; 733 clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; 734 clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 735 compatible = "xlnx,axi-dma-1.00.a"; 736 interrupt-names = "mm2s_introut", "s2mm_introut"; 737 interrupt-parent = <1>; 738 interrupts = <0 35 4 0 36 4>; 739 reg = <0x80400000 0x10000>; 740 xlnx,addrwidth = <0x20>; 741 xlnx,include-sg ; 742 xlnx,sg-length-width = <0xe>; 743 dma-channel@80400000 { 744 compatible = "xlnx,axi-dma-mm2s-channel"; 745 dma-channels = <0x1>; 746 interrupts = <0 35 4>; 747 xlnx,datawidth = <0x40>; 748 xlnx,device-id = <0x0>; 749 }; 750 dma-channel@80400030 { 751 compatible = "xlnx,axi-dma-s2mm-channel"; 752 dma-channels = <0x1>; 753 interrupts = <0 36 4>; 754 xlnx,datawidth = <0x40>; 755 xlnx,device-id = <0x0>; 756 }; 757 }; 758 759 rx_dma: dma@80410000 { 760 #dma-cells = <1>; 761 clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; 762 clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 763 compatible = "xlnx,axi-dma-1.00.a"; 764 //dma-coherent ; 765 interrupt-names = "mm2s_introut", "s2mm_introut"; 766 interrupt-parent = <1>; 767 interrupts = <0 31 4 0 32 4>; 768 reg = <0x80410000 0x10000>; 769 xlnx,addrwidth = <0x20>; 770 xlnx,include-sg ; 771 xlnx,sg-length-width = <0xe>; 772 dma-channel@80410000 { 773 compatible = "xlnx,axi-dma-mm2s-channel"; 774 dma-channels = <0x1>; 775 interrupts = <0 31 4>; 776 xlnx,datawidth = <0x40>; 777 xlnx,device-id = <0x1>; 778 }; 779 dma-channel@80410030 { 780 compatible = "xlnx,axi-dma-s2mm-channel"; 781 dma-channels = <0x1>; 782 interrupts = <0 32 4>; 783 xlnx,datawidth = <0x40>; 784 xlnx,device-id = <0x1>; 785 }; 786 }; 787 788 tx_intf_0: tx_intf@83c00000 { 789 clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk"; 790 clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>; 791 compatible = "sdr,tx_intf"; 792 interrupt-names = "tx_itrpt"; 793 interrupt-parent = <1>; 794 interrupts = <0 34 1>; 795 reg = <0x83c00000 0x10000>; 796 xlnx,s00-axi-addr-width = <0x7>; 797 xlnx,s00-axi-data-width = <0x20>; 798 }; 799 800 rx_intf_0: rx_intf@83c20000 { 801 clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk"; 802 clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>; 803 compatible = "sdr,rx_intf"; 804 interrupt-names = "not_valid_anymore", "rx_pkt_intr"; 805 interrupt-parent = <1>; 806 interrupts = <0 29 1 0 30 1>; 807 reg = <0x83c20000 0x10000>; 808 xlnx,s00-axi-addr-width = <0x7>; 809 xlnx,s00-axi-data-width = <0x20>; 810 }; 811 812 openofdm_tx_0: openofdm_tx@83c10000 { 813 clock-names = "clk"; 814 clocks = <0x2 0x11>; 815 compatible = "sdr,openofdm_tx"; 816 reg = <0x83c10000 0x10000>; 817 }; 818 819 openofdm_rx_0: openofdm_rx@83c30000 { 820 clock-names = "clk"; 821 clocks = <0x2 0x11>; 822 compatible = "sdr,openofdm_rx"; 823 reg = <0x83c30000 0x10000>; 824 }; 825 826 xpu_0: xpu@83c40000 { 827 clock-names = "s00_axi_aclk"; 828 clocks = <0x2 0x11>; 829 compatible = "sdr,xpu"; 830 reg = <0x83c40000 0x10000>; 831 }; 832 833 side_ch_0: side_ch@83c50000 { 834 clock-names = "s00_axi_aclk"; 835 clocks = <0x2 0x11>; 836 compatible = "sdr,side_ch"; 837 reg = <0x83c50000 0x10000>; 838 dmas = <&rx_dma 0 839 &tx_dma 1>; 840 dma-names = "rx_dma_mm2s", "tx_dma_s2mm"; 841 }; 842 843 cf-ad9361-lpc@79020000 { 844 compatible = "adi,axi-ad9361-6.00.a"; 845 reg = <0x79020000 0x6000>; 846 // dmas = <0xb 0x0>; 847 // dma-names = "rx"; 848 spibus-connected = <0xc>; 849 }; 850 851 cf-ad9361-dds-core-lpc@79024000 { 852 compatible = "adi,axi-ad9361-dds-6.00.a"; 853 reg = <0x79024000 0x1000>; 854 clocks = <0xc 0xd>; 855 clock-names = "sampl_clk"; 856 // dmas = <0xd 0x0>; 857 // dma-names = "tx"; 858 }; 859 860 mwipcore@43c00000 { 861 compatible = "mathworks,mwipcore-axi4lite-v1.00"; 862 reg = <0x43c00000 0xffff>; 863 }; 864 865 /*axi-sysid-0@45000000 { 866 compatible = "adi,axi-sysid-1.00.a"; 867 reg = <0x45000000 0x10000>; 868 };*/ 869 }; 870 871 leds { 872 compatible = "gpio-leds"; 873 874 led0 { 875 label = "led0:green"; 876 gpios = <0x6 0x3a 0x0>; 877 }; 878 879 led1 { 880 label = "led1:green"; 881 gpios = <0x6 0x3b 0x0>; 882 }; 883 884 led2 { 885 label = "led2:green"; 886 gpios = <0x6 0x3c 0x0>; 887 }; 888 889 led3 { 890 label = "led3:green"; 891 gpios = <0x6 0x3d 0x0>; 892 }; 893 }; 894 895 gpio_keys { 896 compatible = "gpio-keys"; 897 #address-cells = <0x1>; 898 #size-cells = <0x0>; 899 autorepeat; 900 901 pb0 { 902 label = "Left"; 903 linux,code = <0x69>; 904 gpios = <0x6 0x36 0x0>; 905 }; 906 907 pb1 { 908 label = "Right"; 909 linux,code = <0x6a>; 910 gpios = <0x6 0x37 0x0>; 911 }; 912 913 pb2 { 914 label = "Up"; 915 linux,code = <0x67>; 916 gpios = <0x6 0x38 0x0>; 917 }; 918 919 pb3 { 920 label = "Down"; 921 linux,code = <0x6c>; 922 gpios = <0x6 0x39 0x0>; 923 }; 924 925 sw0 { 926 label = "SW0"; 927 linux,input-type = <0x5>; 928 linux,code = <0x0>; 929 gpios = <0x6 0x3e 0x0>; 930 }; 931 932 sw1 { 933 label = "SW1"; 934 linux,input-type = <0x5>; 935 linux,code = <0x1>; 936 gpios = <0x6 0x3f 0x0>; 937 }; 938 939 sw2 { 940 label = "SW2"; 941 linux,input-type = <0x5>; 942 linux,code = <0x2>; 943 gpios = <0x6 0x40 0x0>; 944 }; 945 946 sw3 { 947 label = "SW3"; 948 linux,input-type = <0x5>; 949 linux,code = <0x3>; 950 gpios = <0x6 0x41 0x0>; 951 }; 952 }; 953}; 954