1 /* 2 * axi lite register access driver 3 * SPDX-FileCopyrightText: 2019 Jiao Xianjun <[email protected]> 4 * SPDX-License-Identifier: AGPL-3.0-or-later 5 */ 6 7 #include <linux/bitops.h> 8 #include <linux/dmapool.h> 9 #include <linux/dma/xilinx_dma.h> 10 #include <linux/init.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/module.h> 15 #include <linux/of_address.h> 16 #include <linux/of_dma.h> 17 #include <linux/of_platform.h> 18 #include <linux/of_irq.h> 19 #include <linux/slab.h> 20 #include <linux/clk.h> 21 #include <linux/io-64-nonatomic-lo-hi.h> 22 #include <linux/delay.h> 23 #include <net/mac80211.h> 24 25 #include "../hw_def.h" 26 27 static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design 28 29 /* IO accessors */ 30 static inline u32 reg_read(u32 reg) 31 { 32 return ioread32(base_addr + reg); 33 } 34 35 static inline void reg_write(u32 reg, u32 value) 36 { 37 iowrite32(value, base_addr + reg); 38 } 39 40 static inline void XPU_REG_MULTI_RST_write(u32 Data) { 41 reg_write(XPU_REG_MULTI_RST_ADDR, Data); 42 } 43 44 static inline u32 XPU_REG_MULTI_RST_read(void){ 45 return reg_read(XPU_REG_MULTI_RST_ADDR); 46 } 47 48 static inline void XPU_REG_SRC_SEL_write(u32 Data) { 49 reg_write(XPU_REG_SRC_SEL_ADDR, Data); 50 } 51 52 static inline u32 XPU_REG_SRC_SEL_read(void){ 53 return reg_read(XPU_REG_SRC_SEL_ADDR); 54 } 55 56 static inline void XPU_REG_RECV_ACK_COUNT_TOP0_write(u32 Data) { 57 reg_write(XPU_REG_RECV_ACK_COUNT_TOP0_ADDR, Data); 58 } 59 60 static inline u32 XPU_REG_RECV_ACK_COUNT_TOP0_read(void){ 61 return reg_read(XPU_REG_RECV_ACK_COUNT_TOP0_ADDR); 62 } 63 64 static inline void XPU_REG_RECV_ACK_COUNT_TOP1_write(u32 Data) { 65 reg_write(XPU_REG_RECV_ACK_COUNT_TOP1_ADDR, Data); 66 } 67 68 static inline u32 XPU_REG_RECV_ACK_COUNT_TOP1_read(void){ 69 return reg_read(XPU_REG_RECV_ACK_COUNT_TOP1_ADDR); 70 } 71 72 static inline void XPU_REG_SEND_ACK_WAIT_TOP_write(u32 Data) { 73 reg_write(XPU_REG_SEND_ACK_WAIT_TOP_ADDR, Data); 74 } 75 76 static inline u32 XPU_REG_SEND_ACK_WAIT_TOP_read(void){ 77 return reg_read(XPU_REG_SEND_ACK_WAIT_TOP_ADDR); 78 } 79 80 static inline void XPU_REG_FILTER_FLAG_write(u32 Data) { 81 reg_write(XPU_REG_FILTER_FLAG_ADDR, Data); 82 } 83 84 static inline u32 XPU_REG_FILTER_FLAG_read(void){ 85 return reg_read(XPU_REG_FILTER_FLAG_ADDR); 86 } 87 88 static inline void XPU_REG_CTS_TO_RTS_CONFIG_write(u32 Data) { 89 reg_write(XPU_REG_CTS_TO_RTS_CONFIG_ADDR, Data); 90 } 91 92 static inline u32 XPU_REG_CTS_TO_RTS_CONFIG_read(void){ 93 return reg_read(XPU_REG_CTS_TO_RTS_CONFIG_ADDR); 94 } 95 96 static inline void XPU_REG_MAC_ADDR_LOW_write(u32 Data) { 97 reg_write(XPU_REG_MAC_ADDR_LOW_ADDR, Data); 98 } 99 100 static inline u32 XPU_REG_MAC_ADDR_LOW_read(void){ 101 return reg_read(XPU_REG_MAC_ADDR_LOW_ADDR); 102 } 103 104 static inline void XPU_REG_MAC_ADDR_HIGH_write(u32 Data) { 105 reg_write(XPU_REG_MAC_ADDR_HIGH_ADDR, Data); 106 } 107 108 static inline u32 XPU_REG_MAC_ADDR_HIGH_read(void){ 109 return reg_read(XPU_REG_MAC_ADDR_HIGH_ADDR); 110 } 111 112 static inline void XPU_REG_BSSID_FILTER_LOW_write(u32 Data) { 113 reg_write(XPU_REG_BSSID_FILTER_LOW_ADDR, Data); 114 } 115 116 static inline u32 XPU_REG_BSSID_FILTER_LOW_read(void){ 117 return reg_read(XPU_REG_BSSID_FILTER_LOW_ADDR); 118 } 119 120 static inline void XPU_REG_BSSID_FILTER_HIGH_write(u32 Data) { 121 reg_write(XPU_REG_BSSID_FILTER_HIGH_ADDR, Data); 122 } 123 124 static inline u32 XPU_REG_BSSID_FILTER_HIGH_read(void){ 125 return reg_read(XPU_REG_BSSID_FILTER_HIGH_ADDR); 126 } 127 128 static inline void XPU_REG_BAND_CHANNEL_write(u32 Data) { 129 reg_write(XPU_REG_BAND_CHANNEL_ADDR, Data); 130 } 131 132 static inline u32 XPU_REG_BAND_CHANNEL_read(void){ 133 return reg_read(XPU_REG_BAND_CHANNEL_ADDR); 134 } 135 136 static inline void XPU_REG_DIFS_ADVANCE_write(u32 Data) { 137 reg_write(XPU_REG_DIFS_ADVANCE_ADDR, Data); 138 } 139 140 static inline u32 XPU_REG_DIFS_ADVANCE_read(void){ 141 return reg_read(XPU_REG_DIFS_ADVANCE_ADDR); 142 } 143 144 static inline u32 XPU_REG_TRX_STATUS_read(void){ 145 return reg_read(XPU_REG_TRX_STATUS_ADDR); 146 } 147 148 static inline u32 XPU_REG_TX_RESULT_read(void){ 149 return reg_read(XPU_REG_TX_RESULT_ADDR); 150 } 151 152 static inline u32 XPU_REG_TSF_RUNTIME_VAL_LOW_read(void){ 153 return reg_read(XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR); 154 } 155 156 static inline u32 XPU_REG_TSF_RUNTIME_VAL_HIGH_read(void){ 157 return reg_read(XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR); 158 } 159 160 static inline void XPU_REG_TSF_LOAD_VAL_LOW_write(u32 value){ 161 reg_write(XPU_REG_TSF_LOAD_VAL_LOW_ADDR, value); 162 } 163 164 static inline void XPU_REG_TSF_LOAD_VAL_HIGH_write(u32 value){ 165 reg_write(XPU_REG_TSF_LOAD_VAL_HIGH_ADDR, value); 166 } 167 168 static inline void XPU_REG_TSF_LOAD_VAL_write(u32 high_value, u32 low_value){ 169 XPU_REG_TSF_LOAD_VAL_LOW_write(low_value); 170 XPU_REG_TSF_LOAD_VAL_HIGH_write(high_value|0x80000000); // msb high 171 XPU_REG_TSF_LOAD_VAL_HIGH_write(high_value&(~0x80000000)); // msb low 172 } 173 174 static inline u32 XPU_REG_FC_DI_read(void){ 175 return reg_read(XPU_REG_FC_DI_ADDR); 176 } 177 178 static inline u32 XPU_REG_ADDR1_LOW_read(void){ 179 return reg_read(XPU_REG_ADDR1_LOW_ADDR); 180 } 181 182 static inline u32 XPU_REG_ADDR1_HIGH_read(void){ 183 return reg_read(XPU_REG_ADDR1_HIGH_ADDR); 184 } 185 186 static inline u32 XPU_REG_ADDR2_LOW_read(void){ 187 return reg_read(XPU_REG_ADDR2_LOW_ADDR); 188 } 189 190 static inline u32 XPU_REG_ADDR2_HIGH_read(void){ 191 return reg_read(XPU_REG_ADDR2_HIGH_ADDR); 192 } 193 194 // static inline void XPU_REG_LBT_TH_write(u32 value, u32 en_flag) { 195 // if (en_flag) { 196 // reg_write(XPU_REG_LBT_TH_ADDR, value&0x7FFFFFFF); 197 // } else { 198 // reg_write(XPU_REG_LBT_TH_ADDR, value|0x80000000); 199 // } 200 // } 201 202 static inline void XPU_REG_LBT_TH_write(u32 value) { 203 reg_write(XPU_REG_LBT_TH_ADDR, value); 204 } 205 206 static inline u32 XPU_REG_RSSI_DB_CFG_read(void){ 207 return reg_read(XPU_REG_RSSI_DB_CFG_ADDR); 208 } 209 210 static inline void XPU_REG_RSSI_DB_CFG_write(u32 Data) { 211 reg_write(XPU_REG_RSSI_DB_CFG_ADDR, Data); 212 } 213 214 static inline u32 XPU_REG_LBT_TH_read(void){ 215 return reg_read(XPU_REG_LBT_TH_ADDR); 216 } 217 218 static inline void XPU_REG_CSMA_DEBUG_write(u32 value){ 219 reg_write(XPU_REG_CSMA_DEBUG_ADDR, value); 220 } 221 222 static inline u32 XPU_REG_CSMA_DEBUG_read(void){ 223 return reg_read(XPU_REG_CSMA_DEBUG_ADDR); 224 } 225 226 static inline void XPU_REG_CSMA_CFG_write(u32 value){ 227 reg_write(XPU_REG_CSMA_CFG_ADDR, value); 228 } 229 230 static inline u32 XPU_REG_CSMA_CFG_read(void){ 231 return reg_read(XPU_REG_CSMA_CFG_ADDR); 232 } 233 234 static inline void XPU_REG_SLICE_COUNT_TOTAL_write(u32 value){ 235 reg_write(XPU_REG_SLICE_COUNT_TOTAL_ADDR, value); 236 } 237 static inline void XPU_REG_SLICE_COUNT_START_write(u32 value){ 238 reg_write(XPU_REG_SLICE_COUNT_START_ADDR, value); 239 } 240 static inline void XPU_REG_SLICE_COUNT_END_write(u32 value){ 241 reg_write(XPU_REG_SLICE_COUNT_END_ADDR, value); 242 } 243 244 245 static inline u32 XPU_REG_SLICE_COUNT_TOTAL_read(void){ 246 return reg_read(XPU_REG_SLICE_COUNT_TOTAL_ADDR); 247 } 248 static inline u32 XPU_REG_SLICE_COUNT_START_read(void){ 249 return reg_read(XPU_REG_SLICE_COUNT_START_ADDR); 250 } 251 static inline u32 XPU_REG_SLICE_COUNT_END_read(void){ 252 return reg_read(XPU_REG_SLICE_COUNT_END_ADDR); 253 } 254 255 256 static inline void XPU_REG_BB_RF_DELAY_write(u32 value){ 257 reg_write(XPU_REG_BB_RF_DELAY_ADDR, value); 258 } 259 260 static inline void XPU_REG_MAX_NUM_RETRANS_write(u32 value){ 261 reg_write(XPU_REG_MAX_NUM_RETRANS_ADDR, value); 262 } 263 264 static inline void XPU_REG_MAC_ADDR_write(u8 *mac_addr) {//, u32 en_flag){ 265 XPU_REG_MAC_ADDR_LOW_write( *( (u32*)(mac_addr) ) ); 266 XPU_REG_MAC_ADDR_HIGH_write( *( (u16*)(mac_addr + 4) ) ); 267 #if 0 268 if (en_flag) { 269 XPU_REG_MAC_ADDR_HIGH_write( (*( (u16*)(mac_addr + 4) )) | 0x80000000 ); // 0x80000000 by default we turn on mac addr filter 270 } else { 271 XPU_REG_MAC_ADDR_HIGH_write( (*( (u16*)(mac_addr + 4) )) & 0x7FFFFFFF ); 272 } 273 #endif 274 } 275 276 static const struct of_device_id dev_of_ids[] = { 277 { .compatible = "sdr,xpu", }, 278 {} 279 }; 280 MODULE_DEVICE_TABLE(of, dev_of_ids); 281 282 static struct xpu_driver_api xpu_driver_api_inst; 283 static struct xpu_driver_api *xpu_api = &xpu_driver_api_inst; 284 EXPORT_SYMBOL(xpu_api); 285 286 static inline u32 hw_init(enum xpu_mode mode){ 287 int err=0, i, rssi_half_db_th, rssi_half_db_offset, agc_gain_delay; 288 u32 filter_flag = 0; 289 290 printk("%s hw_init mode %d\n", xpu_compatible_str, mode); 291 292 //rst 293 for (i=0;i<8;i++) 294 xpu_api->XPU_REG_MULTI_RST_write(0); 295 for (i=0;i<32;i++) 296 xpu_api->XPU_REG_MULTI_RST_write(0xFFFFFFFF); 297 for (i=0;i<8;i++) 298 xpu_api->XPU_REG_MULTI_RST_write(0); 299 300 // http://www.studioreti.it/slide/802-11-Frame_E_C.pdf 301 // https://mrncciew.com/2014/10/14/cwap-802-11-phy-ppdu/ 302 // https://mrncciew.com/2014/09/27/cwap-mac-header-frame-control/ 303 // https://mrncciew.com/2014/10/25/cwap-mac-header-durationid/ 304 // https://mrncciew.com/2014/11/01/cwap-mac-header-sequence-control/ 305 // https://witestlab.poly.edu/blog/802-11-wireless-lan-2/ 306 // phy_rx byte idx: 307 // 5(3 sig + 2 service), -- PHY 308 // 2 frame control, 2 duration/conn ID, --MAC PDU 309 // 6 receiver address, 6 destination address, 6 transmitter address 310 // 2 sequence control 311 // 6 source address 312 // reg_val = 5 + 0; 313 // xpu_api->XPU_REG_PHY_RX_PKT_READ_OFFSET_write(reg_val); 314 // printk("%s hw_init XPU_REG_PHY_RX_PKT_READ_OFFSET_write %d\n", xpu_compatible_str, reg_val); 315 316 // by default turn off filter, because all register are zeros 317 // let's filter out packet according to: enum ieee80211_filter_flags at: https://www.kernel.org/doc/html/v4.9/80211/mac80211.html 318 #if 0 // define in FPGA 319 localparam [13:0] FIF_ALLMULTI = 14b00000000000010, //get all mac addr like 01:00:5E:xx:xx:xx and 33:33:xx:xx:xx:xx through to ARM 320 FIF_FCSFAIL = 14b00000000000100, //not support 321 FIF_PLCPFAIL = 14b00000000001000, //not support 322 FIF_BCN_PRBRESP_PROMISC= 14b00000000010000, 323 FIF_CONTROL = 14b00000000100000, 324 FIF_OTHER_BSS = 14b00000001000000, 325 FIF_PSPOLL = 14b00000010000000, 326 FIF_PROBE_REQ = 14b00000100000000, 327 UNICAST_FOR_US = 14b00001000000000, 328 BROADCAST_ALL_ONE = 14b00010000000000, 329 BROADCAST_ALL_ZERO = 14b00100000000000, 330 MY_BEACON = 14b01000000000000, 331 MONITOR_ALL = 14b10000000000000; 332 #endif 333 filter_flag = (FIF_ALLMULTI|FIF_FCSFAIL|FIF_PLCPFAIL|FIF_BCN_PRBRESP_PROMISC|FIF_CONTROL|FIF_OTHER_BSS|FIF_PSPOLL|FIF_PROBE_REQ|UNICAST_FOR_US|BROADCAST_ALL_ONE|BROADCAST_ALL_ZERO|MY_BEACON|MONITOR_ALL); 334 xpu_api->XPU_REG_FILTER_FLAG_write(filter_flag); 335 xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_write(0xB<<16);//6M 1011:0xB 336 337 // after send data frame wait for ACK, this will be set in real time in function ad9361_rf_set_channel 338 // xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2)*10)<<16) | 10 ); // high 16 bits to cover sig valid of ACK packet, low 16 bits is adjustment of fcs valid waiting time. let's add 2us for those device that is really "slow"! 339 // xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( 6*10 ); // +6 = 16us for 5GHz 340 341 //xpu_api->XPU_REG_MAX_NUM_RETRANS_write(3); // if this > 0, it will override mac80211 set value, and set static retransmission limit 342 343 // xpu_api->XPU_REG_BB_RF_DELAY_write((1<<8)|47); 344 xpu_api->XPU_REG_BB_RF_DELAY_write((10<<8)|40); // extended rf is ongoing for perfect muting. (10<<8)|40 is verified good for zcu102/zed 345 346 // setup time schedule of 4 slices 347 // slice 0 348 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write(50000-1); // total 50ms 349 xpu_api->XPU_REG_SLICE_COUNT_START_write(0); //start 0ms 350 xpu_api->XPU_REG_SLICE_COUNT_END_write(50000-1); //end 50ms 351 352 // slice 1 353 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((1<<20)|(50000-1)); // total 50ms 354 xpu_api->XPU_REG_SLICE_COUNT_START_write((1<<20)|(0)); //start 0ms 355 //xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(20000-1)); //end 20ms 356 xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(50000-1)); //end 20ms 357 358 // slice 2 359 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((2<<20)|(50000-1)); // total 50ms 360 //xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(20000)); //start 20ms 361 xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(0)); //start 20ms 362 //xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(40000-1)); //end 20ms 363 xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(50000-1)); //end 20ms 364 365 // slice 3 366 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((3<<20)|(50000-1)); // total 50ms 367 //xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(40000)); //start 40ms 368 xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(0)); //start 40ms 369 //xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms 370 xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms 371 372 // all slice sync rest 373 xpu_api->XPU_REG_MULTI_RST_write(1<<7); //bit7 reset the counter for all queues at the same time 374 xpu_api->XPU_REG_MULTI_RST_write(0<<7); 375 376 switch(mode) 377 { 378 case XPU_TEST: 379 printk("%s hw_init mode XPU_TEST\n", xpu_compatible_str); 380 break; 381 382 case XPU_NORMAL: 383 printk("%s hw_init mode XPU_NORMAL\n", xpu_compatible_str); 384 break; 385 386 default: 387 printk("%s hw_init mode %d is wrong!\n", xpu_compatible_str, mode); 388 err=1; 389 } 390 xpu_api->XPU_REG_BAND_CHANNEL_write((false<<24)|(BAND_5_8GHZ<<16)|44);//use_short_slot==false; 5.8GHz; channel 44 -- default setting to sync with priv->band/channel/use_short_slot 391 392 agc_gain_delay = 50; //samples 393 rssi_half_db_offset = 75<<1; 394 xpu_api->XPU_REG_RSSI_DB_CFG_write(0x80000000|((rssi_half_db_offset<<16)|agc_gain_delay) ); 395 xpu_api->XPU_REG_RSSI_DB_CFG_write((~0x80000000)&((rssi_half_db_offset<<16)|agc_gain_delay) ); 396 397 //rssi_half_db_th = 70<<1; // with splitter 398 rssi_half_db_th = 87<<1; // -62dBm 399 xpu_api->XPU_REG_LBT_TH_write(rssi_half_db_th); // set IQ rssi th step .5dB to xxx and enable it 400 401 //xpu_api->XPU_REG_CSMA_DEBUG_write((1<<31)|(20<<24)|(4<<19)|(3<<14)|(10<<7)|(5)); 402 xpu_api->XPU_REG_CSMA_DEBUG_write(0); 403 404 xpu_api->XPU_REG_CSMA_CFG_write(3); //normal CSMA 405 // xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); //high priority 406 407 xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((51)<<16)|0 );//now our tx send out I/Q immediately 408 409 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) 410 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) 411 412 xpu_api->XPU_REG_DIFS_ADVANCE_write(2); //us 413 414 printk("%s hw_init err %d\n", xpu_compatible_str, err); 415 return(err); 416 } 417 418 static int dev_probe(struct platform_device *pdev) 419 { 420 struct device_node *np = pdev->dev.of_node; 421 struct resource *io; 422 u32 test_us0, test_us1, test_us2; 423 int err=1; 424 425 printk("\n"); 426 427 if (np) { 428 const struct of_device_id *match; 429 430 match = of_match_node(dev_of_ids, np); 431 if (match) { 432 printk("%s dev_probe match!\n", xpu_compatible_str); 433 err = 0; 434 } 435 } 436 437 if (err) 438 return err; 439 440 xpu_api->hw_init=hw_init; 441 442 xpu_api->reg_read=reg_read; 443 xpu_api->reg_write=reg_write; 444 445 xpu_api->XPU_REG_MULTI_RST_write=XPU_REG_MULTI_RST_write; 446 xpu_api->XPU_REG_MULTI_RST_read=XPU_REG_MULTI_RST_read; 447 xpu_api->XPU_REG_SRC_SEL_write=XPU_REG_SRC_SEL_write; 448 xpu_api->XPU_REG_SRC_SEL_read=XPU_REG_SRC_SEL_read; 449 450 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write=XPU_REG_RECV_ACK_COUNT_TOP0_write; 451 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_read=XPU_REG_RECV_ACK_COUNT_TOP0_read; 452 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write=XPU_REG_RECV_ACK_COUNT_TOP1_write; 453 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_read=XPU_REG_RECV_ACK_COUNT_TOP1_read; 454 xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write=XPU_REG_SEND_ACK_WAIT_TOP_write; 455 xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_read=XPU_REG_SEND_ACK_WAIT_TOP_read; 456 xpu_api->XPU_REG_MAC_ADDR_LOW_write=XPU_REG_MAC_ADDR_LOW_write; 457 xpu_api->XPU_REG_MAC_ADDR_LOW_read=XPU_REG_MAC_ADDR_LOW_read; 458 xpu_api->XPU_REG_MAC_ADDR_HIGH_write=XPU_REG_MAC_ADDR_HIGH_write; 459 xpu_api->XPU_REG_MAC_ADDR_HIGH_read=XPU_REG_MAC_ADDR_HIGH_read; 460 461 xpu_api->XPU_REG_FILTER_FLAG_write=XPU_REG_FILTER_FLAG_write; 462 xpu_api->XPU_REG_FILTER_FLAG_read=XPU_REG_FILTER_FLAG_read; 463 xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_write=XPU_REG_CTS_TO_RTS_CONFIG_write; 464 xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_read=XPU_REG_CTS_TO_RTS_CONFIG_read; 465 xpu_api->XPU_REG_BSSID_FILTER_LOW_write=XPU_REG_BSSID_FILTER_LOW_write; 466 xpu_api->XPU_REG_BSSID_FILTER_LOW_read=XPU_REG_BSSID_FILTER_LOW_read; 467 xpu_api->XPU_REG_BSSID_FILTER_HIGH_write=XPU_REG_BSSID_FILTER_HIGH_write; 468 xpu_api->XPU_REG_BSSID_FILTER_HIGH_read=XPU_REG_BSSID_FILTER_HIGH_read; 469 470 xpu_api->XPU_REG_BAND_CHANNEL_write=XPU_REG_BAND_CHANNEL_write; 471 xpu_api->XPU_REG_BAND_CHANNEL_read=XPU_REG_BAND_CHANNEL_read; 472 473 xpu_api->XPU_REG_DIFS_ADVANCE_write=XPU_REG_DIFS_ADVANCE_write; 474 xpu_api->XPU_REG_DIFS_ADVANCE_read=XPU_REG_DIFS_ADVANCE_read; 475 476 xpu_api->XPU_REG_TRX_STATUS_read=XPU_REG_TRX_STATUS_read; 477 xpu_api->XPU_REG_TX_RESULT_read=XPU_REG_TX_RESULT_read; 478 479 xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read=XPU_REG_TSF_RUNTIME_VAL_LOW_read; 480 xpu_api->XPU_REG_TSF_RUNTIME_VAL_HIGH_read=XPU_REG_TSF_RUNTIME_VAL_HIGH_read; 481 xpu_api->XPU_REG_TSF_LOAD_VAL_LOW_write=XPU_REG_TSF_LOAD_VAL_LOW_write; 482 xpu_api->XPU_REG_TSF_LOAD_VAL_HIGH_write=XPU_REG_TSF_LOAD_VAL_HIGH_write; 483 xpu_api->XPU_REG_TSF_LOAD_VAL_write=XPU_REG_TSF_LOAD_VAL_write; 484 485 xpu_api->XPU_REG_FC_DI_read=XPU_REG_FC_DI_read; 486 xpu_api->XPU_REG_ADDR1_LOW_read=XPU_REG_ADDR1_LOW_read; 487 xpu_api->XPU_REG_ADDR1_HIGH_read=XPU_REG_ADDR1_HIGH_read; 488 xpu_api->XPU_REG_ADDR2_LOW_read=XPU_REG_ADDR2_LOW_read; 489 xpu_api->XPU_REG_ADDR2_HIGH_read=XPU_REG_ADDR2_HIGH_read; 490 491 xpu_api->XPU_REG_LBT_TH_write=XPU_REG_LBT_TH_write; 492 xpu_api->XPU_REG_LBT_TH_read=XPU_REG_LBT_TH_read; 493 494 xpu_api->XPU_REG_RSSI_DB_CFG_read=XPU_REG_RSSI_DB_CFG_read; 495 xpu_api->XPU_REG_RSSI_DB_CFG_write=XPU_REG_RSSI_DB_CFG_write; 496 497 xpu_api->XPU_REG_CSMA_DEBUG_write=XPU_REG_CSMA_DEBUG_write; 498 xpu_api->XPU_REG_CSMA_DEBUG_read=XPU_REG_CSMA_DEBUG_read; 499 500 xpu_api->XPU_REG_CSMA_CFG_write=XPU_REG_CSMA_CFG_write; 501 xpu_api->XPU_REG_CSMA_CFG_read=XPU_REG_CSMA_CFG_read; 502 503 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write=XPU_REG_SLICE_COUNT_TOTAL_write; 504 xpu_api->XPU_REG_SLICE_COUNT_START_write=XPU_REG_SLICE_COUNT_START_write; 505 xpu_api->XPU_REG_SLICE_COUNT_END_write=XPU_REG_SLICE_COUNT_END_write; 506 507 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_read=XPU_REG_SLICE_COUNT_TOTAL_read; 508 xpu_api->XPU_REG_SLICE_COUNT_START_read=XPU_REG_SLICE_COUNT_START_read; 509 xpu_api->XPU_REG_SLICE_COUNT_END_read=XPU_REG_SLICE_COUNT_END_read; 510 511 xpu_api->XPU_REG_BB_RF_DELAY_write=XPU_REG_BB_RF_DELAY_write; 512 xpu_api->XPU_REG_MAX_NUM_RETRANS_write=XPU_REG_MAX_NUM_RETRANS_write; 513 514 xpu_api->XPU_REG_MAC_ADDR_write=XPU_REG_MAC_ADDR_write; 515 516 /* Request and map I/O memory */ 517 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 518 base_addr = devm_ioremap_resource(&pdev->dev, io); 519 if (IS_ERR(base_addr)) 520 return PTR_ERR(base_addr); 521 522 printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", xpu_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); 523 printk("%s dev_probe base_addr 0x%08x\n", xpu_compatible_str,(u32)base_addr); 524 printk("%s dev_probe xpu_driver_api_inst 0x%08x\n", xpu_compatible_str, (u32)&xpu_driver_api_inst); 525 printk("%s dev_probe xpu_api 0x%08x\n", xpu_compatible_str, (u32)xpu_api); 526 527 printk("%s dev_probe reset tsf timer\n", xpu_compatible_str); 528 xpu_api->XPU_REG_TSF_LOAD_VAL_write(0,0); 529 test_us0 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read(); 530 mdelay(33); 531 test_us1 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read(); 532 mdelay(67); 533 test_us2 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read(); 534 printk("%s dev_probe XPU_REG_TSF_RUNTIME_VAL_LOW_read %d %d %dus\n", xpu_compatible_str, test_us0, test_us1, test_us2); 535 536 printk("%s dev_probe succeed!\n", xpu_compatible_str); 537 538 err = hw_init(XPU_NORMAL); 539 540 return err; 541 } 542 543 static int dev_remove(struct platform_device *pdev) 544 { 545 printk("\n"); 546 547 printk("%s dev_remove base_addr 0x%08x\n", xpu_compatible_str,(u32)base_addr); 548 printk("%s dev_remove xpu_driver_api_inst 0x%08x\n", xpu_compatible_str, (u32)&xpu_driver_api_inst); 549 printk("%s dev_remove xpu_api 0x%08x\n", xpu_compatible_str, (u32)xpu_api); 550 551 printk("%s dev_remove succeed!\n", xpu_compatible_str); 552 return 0; 553 } 554 555 static struct platform_driver dev_driver = { 556 .driver = { 557 .name = "sdr,xpu", 558 .owner = THIS_MODULE, 559 .of_match_table = dev_of_ids, 560 }, 561 .probe = dev_probe, 562 .remove = dev_remove, 563 }; 564 565 module_platform_driver(dev_driver); 566 567 MODULE_AUTHOR("Xianjun Jiao"); 568 MODULE_DESCRIPTION("sdr,xpu"); 569 MODULE_LICENSE("GPL v2"); 570