1 /* 2 * axi lite register access driver 3 * Xianjun jiao. [email protected]; [email protected] 4 */ 5 6 #include <linux/bitops.h> 7 #include <linux/dmapool.h> 8 #include <linux/dma/xilinx_dma.h> 9 #include <linux/init.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/module.h> 14 #include <linux/of_address.h> 15 #include <linux/of_dma.h> 16 #include <linux/of_platform.h> 17 #include <linux/of_irq.h> 18 #include <linux/slab.h> 19 #include <linux/clk.h> 20 #include <linux/io-64-nonatomic-lo-hi.h> 21 #include <linux/delay.h> 22 #include <net/mac80211.h> 23 24 #include "../hw_def.h" 25 26 static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design 27 28 /* IO accessors */ 29 static inline u32 reg_read(u32 reg) 30 { 31 return ioread32(base_addr + reg); 32 } 33 34 static inline void reg_write(u32 reg, u32 value) 35 { 36 iowrite32(value, base_addr + reg); 37 } 38 39 static inline void XPU_REG_MULTI_RST_write(u32 Data) { 40 reg_write(XPU_REG_MULTI_RST_ADDR, Data); 41 } 42 43 static inline u32 XPU_REG_MULTI_RST_read(void){ 44 return reg_read(XPU_REG_MULTI_RST_ADDR); 45 } 46 47 static inline void XPU_REG_SRC_SEL_write(u32 Data) { 48 reg_write(XPU_REG_SRC_SEL_ADDR, Data); 49 } 50 51 static inline u32 XPU_REG_SRC_SEL_read(void){ 52 return reg_read(XPU_REG_SRC_SEL_ADDR); 53 } 54 55 static inline void XPU_REG_RECV_ACK_COUNT_TOP0_write(u32 Data) { 56 reg_write(XPU_REG_RECV_ACK_COUNT_TOP0_ADDR, Data); 57 } 58 59 static inline u32 XPU_REG_RECV_ACK_COUNT_TOP0_read(void){ 60 return reg_read(XPU_REG_RECV_ACK_COUNT_TOP0_ADDR); 61 } 62 63 static inline void XPU_REG_RECV_ACK_COUNT_TOP1_write(u32 Data) { 64 reg_write(XPU_REG_RECV_ACK_COUNT_TOP1_ADDR, Data); 65 } 66 67 static inline u32 XPU_REG_RECV_ACK_COUNT_TOP1_read(void){ 68 return reg_read(XPU_REG_RECV_ACK_COUNT_TOP1_ADDR); 69 } 70 71 static inline void XPU_REG_SEND_ACK_WAIT_TOP_write(u32 Data) { 72 reg_write(XPU_REG_SEND_ACK_WAIT_TOP_ADDR, Data); 73 } 74 75 static inline u32 XPU_REG_SEND_ACK_WAIT_TOP_read(void){ 76 return reg_read(XPU_REG_SEND_ACK_WAIT_TOP_ADDR); 77 } 78 79 static inline void XPU_REG_FILTER_FLAG_write(u32 Data) { 80 reg_write(XPU_REG_FILTER_FLAG_ADDR, Data); 81 } 82 83 static inline u32 XPU_REG_FILTER_FLAG_read(void){ 84 return reg_read(XPU_REG_FILTER_FLAG_ADDR); 85 } 86 87 static inline void XPU_REG_CTS_TO_RTS_CONFIG_write(u32 Data) { 88 reg_write(XPU_REG_CTS_TO_RTS_CONFIG_ADDR, Data); 89 } 90 91 static inline u32 XPU_REG_CTS_TO_RTS_CONFIG_read(void){ 92 return reg_read(XPU_REG_CTS_TO_RTS_CONFIG_ADDR); 93 } 94 95 static inline void XPU_REG_MAC_ADDR_LOW_write(u32 Data) { 96 reg_write(XPU_REG_MAC_ADDR_LOW_ADDR, Data); 97 } 98 99 static inline u32 XPU_REG_MAC_ADDR_LOW_read(void){ 100 return reg_read(XPU_REG_MAC_ADDR_LOW_ADDR); 101 } 102 103 static inline void XPU_REG_MAC_ADDR_HIGH_write(u32 Data) { 104 reg_write(XPU_REG_MAC_ADDR_HIGH_ADDR, Data); 105 } 106 107 static inline u32 XPU_REG_MAC_ADDR_HIGH_read(void){ 108 return reg_read(XPU_REG_MAC_ADDR_HIGH_ADDR); 109 } 110 111 static inline void XPU_REG_BSSID_FILTER_LOW_write(u32 Data) { 112 reg_write(XPU_REG_BSSID_FILTER_LOW_ADDR, Data); 113 } 114 115 static inline u32 XPU_REG_BSSID_FILTER_LOW_read(void){ 116 return reg_read(XPU_REG_BSSID_FILTER_LOW_ADDR); 117 } 118 119 static inline void XPU_REG_BSSID_FILTER_HIGH_write(u32 Data) { 120 reg_write(XPU_REG_BSSID_FILTER_HIGH_ADDR, Data); 121 } 122 123 static inline u32 XPU_REG_BSSID_FILTER_HIGH_read(void){ 124 return reg_read(XPU_REG_BSSID_FILTER_HIGH_ADDR); 125 } 126 127 static inline void XPU_REG_BAND_CHANNEL_write(u32 Data) { 128 reg_write(XPU_REG_BAND_CHANNEL_ADDR, Data); 129 } 130 131 static inline u32 XPU_REG_BAND_CHANNEL_read(void){ 132 return reg_read(XPU_REG_BAND_CHANNEL_ADDR); 133 } 134 135 static inline u32 XPU_REG_TRX_STATUS_read(void){ 136 return reg_read(XPU_REG_TRX_STATUS_ADDR); 137 } 138 139 static inline u32 XPU_REG_TX_RESULT_read(void){ 140 return reg_read(XPU_REG_TX_RESULT_ADDR); 141 } 142 143 static inline u32 XPU_REG_TSF_RUNTIME_VAL_LOW_read(void){ 144 return reg_read(XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR); 145 } 146 147 static inline u32 XPU_REG_TSF_RUNTIME_VAL_HIGH_read(void){ 148 return reg_read(XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR); 149 } 150 151 static inline void XPU_REG_TSF_LOAD_VAL_LOW_write(u32 value){ 152 reg_write(XPU_REG_TSF_LOAD_VAL_LOW_ADDR, value); 153 } 154 155 static inline void XPU_REG_TSF_LOAD_VAL_HIGH_write(u32 value){ 156 reg_write(XPU_REG_TSF_LOAD_VAL_HIGH_ADDR, value); 157 } 158 159 static inline void XPU_REG_TSF_LOAD_VAL_write(u32 high_value, u32 low_value){ 160 XPU_REG_TSF_LOAD_VAL_LOW_write(low_value); 161 XPU_REG_TSF_LOAD_VAL_HIGH_write(high_value|0x80000000); // msb high 162 XPU_REG_TSF_LOAD_VAL_HIGH_write(high_value&(~0x80000000)); // msb low 163 } 164 165 static inline u32 XPU_REG_FC_DI_read(void){ 166 return reg_read(XPU_REG_FC_DI_ADDR); 167 } 168 169 static inline u32 XPU_REG_ADDR1_LOW_read(void){ 170 return reg_read(XPU_REG_ADDR1_LOW_ADDR); 171 } 172 173 static inline u32 XPU_REG_ADDR1_HIGH_read(void){ 174 return reg_read(XPU_REG_ADDR1_HIGH_ADDR); 175 } 176 177 static inline u32 XPU_REG_ADDR2_LOW_read(void){ 178 return reg_read(XPU_REG_ADDR2_LOW_ADDR); 179 } 180 181 static inline u32 XPU_REG_ADDR2_HIGH_read(void){ 182 return reg_read(XPU_REG_ADDR2_HIGH_ADDR); 183 } 184 185 // static inline void XPU_REG_LBT_TH_write(u32 value, u32 en_flag) { 186 // if (en_flag) { 187 // reg_write(XPU_REG_LBT_TH_ADDR, value&0x7FFFFFFF); 188 // } else { 189 // reg_write(XPU_REG_LBT_TH_ADDR, value|0x80000000); 190 // } 191 // } 192 193 static inline void XPU_REG_LBT_TH_write(u32 value) { 194 reg_write(XPU_REG_LBT_TH_ADDR, value); 195 } 196 197 static inline u32 XPU_REG_RSSI_DB_CFG_read(void){ 198 return reg_read(XPU_REG_RSSI_DB_CFG_ADDR); 199 } 200 201 static inline void XPU_REG_RSSI_DB_CFG_write(u32 Data) { 202 reg_write(XPU_REG_RSSI_DB_CFG_ADDR, Data); 203 } 204 205 static inline u32 XPU_REG_LBT_TH_read(void){ 206 return reg_read(XPU_REG_LBT_TH_ADDR); 207 } 208 209 static inline void XPU_REG_CSMA_DEBUG_write(u32 value){ 210 reg_write(XPU_REG_CSMA_DEBUG_ADDR, value); 211 } 212 213 static inline u32 XPU_REG_CSMA_DEBUG_read(void){ 214 return reg_read(XPU_REG_CSMA_DEBUG_ADDR); 215 } 216 217 static inline void XPU_REG_CSMA_CFG_write(u32 value){ 218 reg_write(XPU_REG_CSMA_CFG_ADDR, value); 219 } 220 221 static inline u32 XPU_REG_CSMA_CFG_read(void){ 222 return reg_read(XPU_REG_CSMA_CFG_ADDR); 223 } 224 225 static inline void XPU_REG_SLICE_COUNT_TOTAL_write(u32 value){ 226 reg_write(XPU_REG_SLICE_COUNT_TOTAL_ADDR, value); 227 } 228 static inline void XPU_REG_SLICE_COUNT_START_write(u32 value){ 229 reg_write(XPU_REG_SLICE_COUNT_START_ADDR, value); 230 } 231 static inline void XPU_REG_SLICE_COUNT_END_write(u32 value){ 232 reg_write(XPU_REG_SLICE_COUNT_END_ADDR, value); 233 } 234 235 236 static inline u32 XPU_REG_SLICE_COUNT_TOTAL_read(void){ 237 return reg_read(XPU_REG_SLICE_COUNT_TOTAL_ADDR); 238 } 239 static inline u32 XPU_REG_SLICE_COUNT_START_read(void){ 240 return reg_read(XPU_REG_SLICE_COUNT_START_ADDR); 241 } 242 static inline u32 XPU_REG_SLICE_COUNT_END_read(void){ 243 return reg_read(XPU_REG_SLICE_COUNT_END_ADDR); 244 } 245 246 247 static inline void XPU_REG_BB_RF_DELAY_write(u32 value){ 248 reg_write(XPU_REG_BB_RF_DELAY_ADDR, value); 249 } 250 251 static inline void XPU_REG_MAX_NUM_RETRANS_write(u32 value){ 252 reg_write(XPU_REG_MAX_NUM_RETRANS_ADDR, value); 253 } 254 255 static inline void XPU_REG_MAC_ADDR_write(u8 *mac_addr) {//, u32 en_flag){ 256 XPU_REG_MAC_ADDR_LOW_write( *( (u32*)(mac_addr) ) ); 257 XPU_REG_MAC_ADDR_HIGH_write( *( (u16*)(mac_addr + 4) ) ); 258 #if 0 259 if (en_flag) { 260 XPU_REG_MAC_ADDR_HIGH_write( (*( (u16*)(mac_addr + 4) )) | 0x80000000 ); // 0x80000000 by default we turn on mac addr filter 261 } else { 262 XPU_REG_MAC_ADDR_HIGH_write( (*( (u16*)(mac_addr + 4) )) & 0x7FFFFFFF ); 263 } 264 #endif 265 } 266 267 static const struct of_device_id dev_of_ids[] = { 268 { .compatible = "sdr,xpu", }, 269 {} 270 }; 271 MODULE_DEVICE_TABLE(of, dev_of_ids); 272 273 static struct xpu_driver_api xpu_driver_api_inst; 274 static struct xpu_driver_api *xpu_api = &xpu_driver_api_inst; 275 EXPORT_SYMBOL(xpu_api); 276 277 static inline u32 hw_init(enum xpu_mode mode){ 278 int err=0, i, rssi_half_db_th, rssi_half_db_offset, agc_gain_delay; 279 u32 filter_flag = 0; 280 281 printk("%s hw_init mode %d\n", xpu_compatible_str, mode); 282 283 //rst 284 for (i=0;i<8;i++) 285 xpu_api->XPU_REG_MULTI_RST_write(0); 286 for (i=0;i<32;i++) 287 xpu_api->XPU_REG_MULTI_RST_write(0xFFFFFFFF); 288 for (i=0;i<8;i++) 289 xpu_api->XPU_REG_MULTI_RST_write(0); 290 291 // http://www.studioreti.it/slide/802-11-Frame_E_C.pdf 292 // https://mrncciew.com/2014/10/14/cwap-802-11-phy-ppdu/ 293 // https://mrncciew.com/2014/09/27/cwap-mac-header-frame-control/ 294 // https://mrncciew.com/2014/10/25/cwap-mac-header-durationid/ 295 // https://mrncciew.com/2014/11/01/cwap-mac-header-sequence-control/ 296 // https://witestlab.poly.edu/blog/802-11-wireless-lan-2/ 297 // phy_rx byte idx: 298 // 5(3 sig + 2 service), -- PHY 299 // 2 frame control, 2 duration/conn ID, --MAC PDU 300 // 6 receiver address, 6 destination address, 6 transmitter address 301 // 2 sequence control 302 // 6 source address 303 // reg_val = 5 + 0; 304 // xpu_api->XPU_REG_PHY_RX_PKT_READ_OFFSET_write(reg_val); 305 // printk("%s hw_init XPU_REG_PHY_RX_PKT_READ_OFFSET_write %d\n", xpu_compatible_str, reg_val); 306 307 // by default turn off filter, because all register are zeros 308 // let's filter out packet according to: enum ieee80211_filter_flags at: https://www.kernel.org/doc/html/v4.9/80211/mac80211.html 309 #if 0 // define in FPGA 310 localparam [13:0] FIF_ALLMULTI = 14b00000000000010, //get all mac addr like 01:00:5E:xx:xx:xx and 33:33:xx:xx:xx:xx through to ARM 311 FIF_FCSFAIL = 14b00000000000100, //not support 312 FIF_PLCPFAIL = 14b00000000001000, //not support 313 FIF_BCN_PRBRESP_PROMISC= 14b00000000010000, 314 FIF_CONTROL = 14b00000000100000, 315 FIF_OTHER_BSS = 14b00000001000000, 316 FIF_PSPOLL = 14b00000010000000, 317 FIF_PROBE_REQ = 14b00000100000000, 318 UNICAST_FOR_US = 14b00001000000000, 319 BROADCAST_ALL_ONE = 14b00010000000000, 320 BROADCAST_ALL_ZERO = 14b00100000000000, 321 MY_BEACON = 14b01000000000000, 322 MONITOR_ALL = 14b10000000000000; 323 #endif 324 filter_flag = (FIF_ALLMULTI|FIF_FCSFAIL|FIF_PLCPFAIL|FIF_BCN_PRBRESP_PROMISC|FIF_CONTROL|FIF_OTHER_BSS|FIF_PSPOLL|FIF_PROBE_REQ|UNICAST_FOR_US|BROADCAST_ALL_ONE|BROADCAST_ALL_ZERO|MY_BEACON|MONITOR_ALL); 325 xpu_api->XPU_REG_FILTER_FLAG_write(filter_flag); 326 xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_write(0xB<<16);//6M 1011:0xB 327 328 // after send data frame wait for ACK, this will be set in real time in function ad9361_rf_set_channel 329 // xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2)*10)<<16) | 10 ); // high 16 bits to cover sig valid of ACK packet, low 16 bits is adjustment of fcs valid waiting time. let's add 2us for those device that is really "slow"! 330 // xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( 6*10 ); // +6 = 16us for 5GHz 331 332 //xpu_api->XPU_REG_MAX_NUM_RETRANS_write(3); // if this > 0, it will override mac80211 set value, and set static retransmission limit 333 334 xpu_api->XPU_REG_BB_RF_DELAY_write(49); 335 336 // setup time schedule of 4 slices 337 // slice 0 338 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write(50000-1); // total 50ms 339 xpu_api->XPU_REG_SLICE_COUNT_START_write(0); //start 0ms 340 xpu_api->XPU_REG_SLICE_COUNT_END_write(50000-1); //end 50ms 341 342 // slice 1 343 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((1<<20)|(50000-1)); // total 50ms 344 xpu_api->XPU_REG_SLICE_COUNT_START_write((1<<20)|(0)); //start 0ms 345 //xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(20000-1)); //end 20ms 346 xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(50000-1)); //end 20ms 347 348 // slice 2 349 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((2<<20)|(50000-1)); // total 50ms 350 //xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(20000)); //start 20ms 351 xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(0)); //start 20ms 352 //xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(40000-1)); //end 20ms 353 xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(50000-1)); //end 20ms 354 355 // slice 3 356 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((3<<20)|(50000-1)); // total 50ms 357 //xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(40000)); //start 40ms 358 xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(0)); //start 40ms 359 //xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms 360 xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms 361 362 // all slice sync rest 363 xpu_api->XPU_REG_MULTI_RST_write(1<<7); //bit7 reset the counter for all queues at the same time 364 xpu_api->XPU_REG_MULTI_RST_write(0<<7); 365 366 switch(mode) 367 { 368 case XPU_TEST: 369 printk("%s hw_init mode XPU_TEST\n", xpu_compatible_str); 370 break; 371 372 case XPU_NORMAL: 373 printk("%s hw_init mode XPU_NORMAL\n", xpu_compatible_str); 374 break; 375 376 default: 377 printk("%s hw_init mode %d is wrong!\n", xpu_compatible_str, mode); 378 err=1; 379 } 380 xpu_api->XPU_REG_BAND_CHANNEL_write((false<<24)|(BAND_5_8GHZ<<16)|44);//use_short_slot==false; 5.8GHz; channel 44 -- default setting to sync with priv->band/channel/use_short_slot 381 382 agc_gain_delay = 50; //samples 383 rssi_half_db_offset = 75<<1; 384 xpu_api->XPU_REG_RSSI_DB_CFG_write(0x80000000|((rssi_half_db_offset<<16)|agc_gain_delay) ); 385 xpu_api->XPU_REG_RSSI_DB_CFG_write((~0x80000000)&((rssi_half_db_offset<<16)|agc_gain_delay) ); 386 387 //rssi_half_db_th = 70<<1; // with splitter 388 rssi_half_db_th = 87<<1; // -62dBm 389 xpu_api->XPU_REG_LBT_TH_write(rssi_half_db_th); // set IQ rssi th step .5dB to xxx and enable it 390 391 //xpu_api->XPU_REG_CSMA_DEBUG_write((1<<31)|(20<<24)|(4<<19)|(3<<14)|(10<<7)|(5)); 392 xpu_api->XPU_REG_CSMA_DEBUG_write(0); 393 394 //xpu_api->XPU_REG_CSMA_CFG_write(3); //normal CSMA 395 xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); //high priority 396 397 xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((51)<<16)|0 );//now our tx send out I/Q immediately 398 399 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) 400 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) 401 402 printk("%s hw_init err %d\n", xpu_compatible_str, err); 403 return(err); 404 } 405 406 static int dev_probe(struct platform_device *pdev) 407 { 408 struct device_node *np = pdev->dev.of_node; 409 struct resource *io; 410 u32 test_us0, test_us1, test_us2; 411 int err=1; 412 413 printk("\n"); 414 415 if (np) { 416 const struct of_device_id *match; 417 418 match = of_match_node(dev_of_ids, np); 419 if (match) { 420 printk("%s dev_probe match!\n", xpu_compatible_str); 421 err = 0; 422 } 423 } 424 425 if (err) 426 return err; 427 428 xpu_api->hw_init=hw_init; 429 430 xpu_api->reg_read=reg_read; 431 xpu_api->reg_write=reg_write; 432 433 xpu_api->XPU_REG_MULTI_RST_write=XPU_REG_MULTI_RST_write; 434 xpu_api->XPU_REG_MULTI_RST_read=XPU_REG_MULTI_RST_read; 435 xpu_api->XPU_REG_SRC_SEL_write=XPU_REG_SRC_SEL_write; 436 xpu_api->XPU_REG_SRC_SEL_read=XPU_REG_SRC_SEL_read; 437 438 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write=XPU_REG_RECV_ACK_COUNT_TOP0_write; 439 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_read=XPU_REG_RECV_ACK_COUNT_TOP0_read; 440 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write=XPU_REG_RECV_ACK_COUNT_TOP1_write; 441 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_read=XPU_REG_RECV_ACK_COUNT_TOP1_read; 442 xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write=XPU_REG_SEND_ACK_WAIT_TOP_write; 443 xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_read=XPU_REG_SEND_ACK_WAIT_TOP_read; 444 xpu_api->XPU_REG_MAC_ADDR_LOW_write=XPU_REG_MAC_ADDR_LOW_write; 445 xpu_api->XPU_REG_MAC_ADDR_LOW_read=XPU_REG_MAC_ADDR_LOW_read; 446 xpu_api->XPU_REG_MAC_ADDR_HIGH_write=XPU_REG_MAC_ADDR_HIGH_write; 447 xpu_api->XPU_REG_MAC_ADDR_HIGH_read=XPU_REG_MAC_ADDR_HIGH_read; 448 449 xpu_api->XPU_REG_FILTER_FLAG_write=XPU_REG_FILTER_FLAG_write; 450 xpu_api->XPU_REG_FILTER_FLAG_read=XPU_REG_FILTER_FLAG_read; 451 xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_write=XPU_REG_CTS_TO_RTS_CONFIG_write; 452 xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_read=XPU_REG_CTS_TO_RTS_CONFIG_read; 453 xpu_api->XPU_REG_BSSID_FILTER_LOW_write=XPU_REG_BSSID_FILTER_LOW_write; 454 xpu_api->XPU_REG_BSSID_FILTER_LOW_read=XPU_REG_BSSID_FILTER_LOW_read; 455 xpu_api->XPU_REG_BSSID_FILTER_HIGH_write=XPU_REG_BSSID_FILTER_HIGH_write; 456 xpu_api->XPU_REG_BSSID_FILTER_HIGH_read=XPU_REG_BSSID_FILTER_HIGH_read; 457 458 xpu_api->XPU_REG_BAND_CHANNEL_write=XPU_REG_BAND_CHANNEL_write; 459 xpu_api->XPU_REG_BAND_CHANNEL_read=XPU_REG_BAND_CHANNEL_read; 460 461 xpu_api->XPU_REG_TRX_STATUS_read=XPU_REG_TRX_STATUS_read; 462 xpu_api->XPU_REG_TX_RESULT_read=XPU_REG_TX_RESULT_read; 463 464 xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read=XPU_REG_TSF_RUNTIME_VAL_LOW_read; 465 xpu_api->XPU_REG_TSF_RUNTIME_VAL_HIGH_read=XPU_REG_TSF_RUNTIME_VAL_HIGH_read; 466 xpu_api->XPU_REG_TSF_LOAD_VAL_LOW_write=XPU_REG_TSF_LOAD_VAL_LOW_write; 467 xpu_api->XPU_REG_TSF_LOAD_VAL_HIGH_write=XPU_REG_TSF_LOAD_VAL_HIGH_write; 468 xpu_api->XPU_REG_TSF_LOAD_VAL_write=XPU_REG_TSF_LOAD_VAL_write; 469 470 xpu_api->XPU_REG_FC_DI_read=XPU_REG_FC_DI_read; 471 xpu_api->XPU_REG_ADDR1_LOW_read=XPU_REG_ADDR1_LOW_read; 472 xpu_api->XPU_REG_ADDR1_HIGH_read=XPU_REG_ADDR1_HIGH_read; 473 xpu_api->XPU_REG_ADDR2_LOW_read=XPU_REG_ADDR2_LOW_read; 474 xpu_api->XPU_REG_ADDR2_HIGH_read=XPU_REG_ADDR2_HIGH_read; 475 476 xpu_api->XPU_REG_LBT_TH_write=XPU_REG_LBT_TH_write; 477 xpu_api->XPU_REG_LBT_TH_read=XPU_REG_LBT_TH_read; 478 479 xpu_api->XPU_REG_RSSI_DB_CFG_read=XPU_REG_RSSI_DB_CFG_read; 480 xpu_api->XPU_REG_RSSI_DB_CFG_write=XPU_REG_RSSI_DB_CFG_write; 481 482 xpu_api->XPU_REG_CSMA_DEBUG_write=XPU_REG_CSMA_DEBUG_write; 483 xpu_api->XPU_REG_CSMA_DEBUG_read=XPU_REG_CSMA_DEBUG_read; 484 485 xpu_api->XPU_REG_CSMA_CFG_write=XPU_REG_CSMA_CFG_write; 486 xpu_api->XPU_REG_CSMA_CFG_read=XPU_REG_CSMA_CFG_read; 487 488 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write=XPU_REG_SLICE_COUNT_TOTAL_write; 489 xpu_api->XPU_REG_SLICE_COUNT_START_write=XPU_REG_SLICE_COUNT_START_write; 490 xpu_api->XPU_REG_SLICE_COUNT_END_write=XPU_REG_SLICE_COUNT_END_write; 491 492 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_read=XPU_REG_SLICE_COUNT_TOTAL_read; 493 xpu_api->XPU_REG_SLICE_COUNT_START_read=XPU_REG_SLICE_COUNT_START_read; 494 xpu_api->XPU_REG_SLICE_COUNT_END_read=XPU_REG_SLICE_COUNT_END_read; 495 496 xpu_api->XPU_REG_BB_RF_DELAY_write=XPU_REG_BB_RF_DELAY_write; 497 xpu_api->XPU_REG_MAX_NUM_RETRANS_write=XPU_REG_MAX_NUM_RETRANS_write; 498 499 xpu_api->XPU_REG_MAC_ADDR_write=XPU_REG_MAC_ADDR_write; 500 501 /* Request and map I/O memory */ 502 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 503 base_addr = devm_ioremap_resource(&pdev->dev, io); 504 if (IS_ERR(base_addr)) 505 return PTR_ERR(base_addr); 506 507 printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", xpu_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); 508 printk("%s dev_probe base_addr 0x%08x\n", xpu_compatible_str,(u32)base_addr); 509 printk("%s dev_probe xpu_driver_api_inst 0x%08x\n", xpu_compatible_str, (u32)&xpu_driver_api_inst); 510 printk("%s dev_probe xpu_api 0x%08x\n", xpu_compatible_str, (u32)xpu_api); 511 512 printk("%s dev_probe reset tsf timer\n", xpu_compatible_str); 513 xpu_api->XPU_REG_TSF_LOAD_VAL_write(0,0); 514 test_us0 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read(); 515 mdelay(33); 516 test_us1 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read(); 517 mdelay(67); 518 test_us2 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read(); 519 printk("%s dev_probe XPU_REG_TSF_RUNTIME_VAL_LOW_read %d %d %dus\n", xpu_compatible_str, test_us0, test_us1, test_us2); 520 521 printk("%s dev_probe succeed!\n", xpu_compatible_str); 522 523 err = hw_init(XPU_NORMAL); 524 525 return err; 526 } 527 528 static int dev_remove(struct platform_device *pdev) 529 { 530 printk("\n"); 531 532 printk("%s dev_remove base_addr 0x%08x\n", xpu_compatible_str,(u32)base_addr); 533 printk("%s dev_remove xpu_driver_api_inst 0x%08x\n", xpu_compatible_str, (u32)&xpu_driver_api_inst); 534 printk("%s dev_remove xpu_api 0x%08x\n", xpu_compatible_str, (u32)xpu_api); 535 536 printk("%s dev_remove succeed!\n", xpu_compatible_str); 537 return 0; 538 } 539 540 static struct platform_driver dev_driver = { 541 .driver = { 542 .name = "sdr,xpu", 543 .owner = THIS_MODULE, 544 .of_match_table = dev_of_ids, 545 }, 546 .probe = dev_probe, 547 .remove = dev_remove, 548 }; 549 550 module_platform_driver(dev_driver); 551 552 MODULE_AUTHOR("Xianjun Jiao"); 553 MODULE_DESCRIPTION("sdr,xpu"); 554 MODULE_LICENSE("GPL v2"); 555