1 /* 2 * axi lite register access driver 3 * Author: Xianjun Jiao, Michael Mehari, Wei Liu 4 * SPDX-FileCopyrightText: 2019 UGent 5 * SPDX-License-Identifier: AGPL-3.0-or-later 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/dmapool.h> 10 #include <linux/dma/xilinx_dma.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/of_dma.h> 18 #include <linux/of_platform.h> 19 #include <linux/of_irq.h> 20 #include <linux/slab.h> 21 #include <linux/clk.h> 22 #include <linux/io-64-nonatomic-lo-hi.h> 23 #include <linux/delay.h> 24 #include <net/mac80211.h> 25 26 #include "../hw_def.h" 27 28 static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design 29 30 /* IO accessors */ 31 static inline u32 reg_read(u32 reg) 32 { 33 return ioread32(base_addr + reg); 34 } 35 36 static inline void reg_write(u32 reg, u32 value) 37 { 38 iowrite32(value, base_addr + reg); 39 } 40 41 static inline void XPU_REG_MULTI_RST_write(u32 Data) { 42 reg_write(XPU_REG_MULTI_RST_ADDR, Data); 43 } 44 45 static inline u32 XPU_REG_MULTI_RST_read(void){ 46 return reg_read(XPU_REG_MULTI_RST_ADDR); 47 } 48 49 static inline void XPU_REG_SRC_SEL_write(u32 Data) { 50 reg_write(XPU_REG_SRC_SEL_ADDR, Data); 51 } 52 53 static inline u32 XPU_REG_SRC_SEL_read(void){ 54 return reg_read(XPU_REG_SRC_SEL_ADDR); 55 } 56 57 static inline void XPU_REG_RECV_ACK_COUNT_TOP0_write(u32 Data) { 58 reg_write(XPU_REG_RECV_ACK_COUNT_TOP0_ADDR, Data); 59 } 60 61 static inline u32 XPU_REG_RECV_ACK_COUNT_TOP0_read(void){ 62 return reg_read(XPU_REG_RECV_ACK_COUNT_TOP0_ADDR); 63 } 64 65 static inline void XPU_REG_RECV_ACK_COUNT_TOP1_write(u32 Data) { 66 reg_write(XPU_REG_RECV_ACK_COUNT_TOP1_ADDR, Data); 67 } 68 69 static inline u32 XPU_REG_RECV_ACK_COUNT_TOP1_read(void){ 70 return reg_read(XPU_REG_RECV_ACK_COUNT_TOP1_ADDR); 71 } 72 73 static inline void XPU_REG_SEND_ACK_WAIT_TOP_write(u32 Data) { 74 reg_write(XPU_REG_SEND_ACK_WAIT_TOP_ADDR, Data); 75 } 76 77 static inline u32 XPU_REG_SEND_ACK_WAIT_TOP_read(void){ 78 return reg_read(XPU_REG_SEND_ACK_WAIT_TOP_ADDR); 79 } 80 81 static inline void XPU_REG_FILTER_FLAG_write(u32 Data) { 82 reg_write(XPU_REG_FILTER_FLAG_ADDR, Data); 83 } 84 85 static inline u32 XPU_REG_FILTER_FLAG_read(void){ 86 return reg_read(XPU_REG_FILTER_FLAG_ADDR); 87 } 88 89 static inline void XPU_REG_CTS_TO_RTS_CONFIG_write(u32 Data) { 90 reg_write(XPU_REG_CTS_TO_RTS_CONFIG_ADDR, Data); 91 } 92 93 static inline u32 XPU_REG_CTS_TO_RTS_CONFIG_read(void){ 94 return reg_read(XPU_REG_CTS_TO_RTS_CONFIG_ADDR); 95 } 96 97 static inline void XPU_REG_MAC_ADDR_LOW_write(u32 Data) { 98 reg_write(XPU_REG_MAC_ADDR_LOW_ADDR, Data); 99 } 100 101 static inline u32 XPU_REG_MAC_ADDR_LOW_read(void){ 102 return reg_read(XPU_REG_MAC_ADDR_LOW_ADDR); 103 } 104 105 static inline void XPU_REG_MAC_ADDR_HIGH_write(u32 Data) { 106 reg_write(XPU_REG_MAC_ADDR_HIGH_ADDR, Data); 107 } 108 109 static inline u32 XPU_REG_MAC_ADDR_HIGH_read(void){ 110 return reg_read(XPU_REG_MAC_ADDR_HIGH_ADDR); 111 } 112 113 static inline void XPU_REG_BSSID_FILTER_LOW_write(u32 Data) { 114 reg_write(XPU_REG_BSSID_FILTER_LOW_ADDR, Data); 115 } 116 117 static inline u32 XPU_REG_BSSID_FILTER_LOW_read(void){ 118 return reg_read(XPU_REG_BSSID_FILTER_LOW_ADDR); 119 } 120 121 static inline void XPU_REG_BSSID_FILTER_HIGH_write(u32 Data) { 122 reg_write(XPU_REG_BSSID_FILTER_HIGH_ADDR, Data); 123 } 124 125 static inline u32 XPU_REG_BSSID_FILTER_HIGH_read(void){ 126 return reg_read(XPU_REG_BSSID_FILTER_HIGH_ADDR); 127 } 128 129 static inline void XPU_REG_BAND_CHANNEL_write(u32 Data) { 130 reg_write(XPU_REG_BAND_CHANNEL_ADDR, Data); 131 } 132 133 static inline u32 XPU_REG_BAND_CHANNEL_read(void){ 134 return reg_read(XPU_REG_BAND_CHANNEL_ADDR); 135 } 136 137 static inline void XPU_REG_DIFS_ADVANCE_write(u32 Data) { 138 reg_write(XPU_REG_DIFS_ADVANCE_ADDR, Data); 139 } 140 141 static inline u32 XPU_REG_DIFS_ADVANCE_read(void){ 142 return reg_read(XPU_REG_DIFS_ADVANCE_ADDR); 143 } 144 145 static inline void XPU_REG_FORCE_IDLE_MISC_write(u32 Data) { 146 reg_write(XPU_REG_FORCE_IDLE_MISC_ADDR, Data); 147 } 148 149 static inline u32 XPU_REG_FORCE_IDLE_MISC_read(void){ 150 return reg_read(XPU_REG_FORCE_IDLE_MISC_ADDR); 151 } 152 153 static inline u32 XPU_REG_TRX_STATUS_read(void){ 154 return reg_read(XPU_REG_TRX_STATUS_ADDR); 155 } 156 157 static inline u32 XPU_REG_TX_RESULT_read(void){ 158 return reg_read(XPU_REG_TX_RESULT_ADDR); 159 } 160 161 static inline u32 XPU_REG_TSF_RUNTIME_VAL_LOW_read(void){ 162 return reg_read(XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR); 163 } 164 165 static inline u32 XPU_REG_TSF_RUNTIME_VAL_HIGH_read(void){ 166 return reg_read(XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR); 167 } 168 169 static inline void XPU_REG_TSF_LOAD_VAL_LOW_write(u32 value){ 170 reg_write(XPU_REG_TSF_LOAD_VAL_LOW_ADDR, value); 171 } 172 173 static inline void XPU_REG_TSF_LOAD_VAL_HIGH_write(u32 value){ 174 reg_write(XPU_REG_TSF_LOAD_VAL_HIGH_ADDR, value); 175 } 176 177 static inline void XPU_REG_TSF_LOAD_VAL_write(u32 high_value, u32 low_value){ 178 XPU_REG_TSF_LOAD_VAL_LOW_write(low_value); 179 XPU_REG_TSF_LOAD_VAL_HIGH_write(high_value|0x80000000); // msb high 180 XPU_REG_TSF_LOAD_VAL_HIGH_write(high_value&(~0x80000000)); // msb low 181 } 182 183 static inline u32 XPU_REG_FC_DI_read(void){ 184 return reg_read(XPU_REG_FC_DI_ADDR); 185 } 186 187 static inline u32 XPU_REG_ADDR1_LOW_read(void){ 188 return reg_read(XPU_REG_ADDR1_LOW_ADDR); 189 } 190 191 static inline u32 XPU_REG_ADDR1_HIGH_read(void){ 192 return reg_read(XPU_REG_ADDR1_HIGH_ADDR); 193 } 194 195 static inline u32 XPU_REG_ADDR2_LOW_read(void){ 196 return reg_read(XPU_REG_ADDR2_LOW_ADDR); 197 } 198 199 static inline u32 XPU_REG_ADDR2_HIGH_read(void){ 200 return reg_read(XPU_REG_ADDR2_HIGH_ADDR); 201 } 202 203 // static inline void XPU_REG_LBT_TH_write(u32 value, u32 en_flag) { 204 // if (en_flag) { 205 // reg_write(XPU_REG_LBT_TH_ADDR, value&0x7FFFFFFF); 206 // } else { 207 // reg_write(XPU_REG_LBT_TH_ADDR, value|0x80000000); 208 // } 209 // } 210 211 static inline void XPU_REG_LBT_TH_write(u32 value) { 212 reg_write(XPU_REG_LBT_TH_ADDR, value); 213 } 214 215 static inline u32 XPU_REG_RSSI_DB_CFG_read(void){ 216 return reg_read(XPU_REG_RSSI_DB_CFG_ADDR); 217 } 218 219 static inline void XPU_REG_RSSI_DB_CFG_write(u32 Data) { 220 reg_write(XPU_REG_RSSI_DB_CFG_ADDR, Data); 221 } 222 223 static inline u32 XPU_REG_LBT_TH_read(void){ 224 return reg_read(XPU_REG_LBT_TH_ADDR); 225 } 226 227 static inline void XPU_REG_CSMA_DEBUG_write(u32 value){ 228 reg_write(XPU_REG_CSMA_DEBUG_ADDR, value); 229 } 230 231 static inline u32 XPU_REG_CSMA_DEBUG_read(void){ 232 return reg_read(XPU_REG_CSMA_DEBUG_ADDR); 233 } 234 235 static inline void XPU_REG_CSMA_CFG_write(u32 value){ 236 reg_write(XPU_REG_CSMA_CFG_ADDR, value); 237 } 238 239 static inline u32 XPU_REG_CSMA_CFG_read(void){ 240 return reg_read(XPU_REG_CSMA_CFG_ADDR); 241 } 242 243 static inline void XPU_REG_SLICE_COUNT_TOTAL_write(u32 value){ 244 reg_write(XPU_REG_SLICE_COUNT_TOTAL_ADDR, value); 245 } 246 static inline void XPU_REG_SLICE_COUNT_START_write(u32 value){ 247 reg_write(XPU_REG_SLICE_COUNT_START_ADDR, value); 248 } 249 static inline void XPU_REG_SLICE_COUNT_END_write(u32 value){ 250 reg_write(XPU_REG_SLICE_COUNT_END_ADDR, value); 251 } 252 253 254 static inline u32 XPU_REG_SLICE_COUNT_TOTAL_read(void){ 255 return reg_read(XPU_REG_SLICE_COUNT_TOTAL_ADDR); 256 } 257 static inline u32 XPU_REG_SLICE_COUNT_START_read(void){ 258 return reg_read(XPU_REG_SLICE_COUNT_START_ADDR); 259 } 260 static inline u32 XPU_REG_SLICE_COUNT_END_read(void){ 261 return reg_read(XPU_REG_SLICE_COUNT_END_ADDR); 262 } 263 264 static inline void XPU_REG_BB_RF_DELAY_write(u32 value){ 265 reg_write(XPU_REG_BB_RF_DELAY_ADDR, value); 266 } 267 268 static inline void XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write(u32 value){ 269 reg_write(XPU_REG_ACK_CTL_MAX_NUM_RETRANS_ADDR, value); 270 } 271 static inline u32 XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read(void){ 272 return reg_read(XPU_REG_ACK_CTL_MAX_NUM_RETRANS_ADDR); 273 } 274 275 static inline void XPU_REG_AMPDU_ACTION_write(u32 Data) { 276 reg_write(XPU_REG_AMPDU_ACTION_ADDR, Data); 277 } 278 279 static inline u32 XPU_REG_AMPDU_ACTION_read(void){ 280 return reg_read(XPU_REG_AMPDU_ACTION_ADDR); 281 } 282 283 static inline void XPU_REG_MAC_ADDR_write(u8 *mac_addr) {//, u32 en_flag){ 284 XPU_REG_MAC_ADDR_LOW_write( *( (u32*)(mac_addr) ) ); 285 XPU_REG_MAC_ADDR_HIGH_write( *( (u16*)(mac_addr + 4) ) ); 286 #if 0 287 if (en_flag) { 288 XPU_REG_MAC_ADDR_HIGH_write( (*( (u16*)(mac_addr + 4) )) | 0x80000000 ); // 0x80000000 by default we turn on mac addr filter 289 } else { 290 XPU_REG_MAC_ADDR_HIGH_write( (*( (u16*)(mac_addr + 4) )) & 0x7FFFFFFF ); 291 } 292 #endif 293 } 294 295 static const struct of_device_id dev_of_ids[] = { 296 { .compatible = "sdr,xpu", }, 297 {} 298 }; 299 MODULE_DEVICE_TABLE(of, dev_of_ids); 300 301 static struct xpu_driver_api xpu_driver_api_inst; 302 static struct xpu_driver_api *xpu_api = &xpu_driver_api_inst; 303 EXPORT_SYMBOL(xpu_api); 304 305 static inline u32 hw_init(enum xpu_mode mode){ 306 int err=0, i, rssi_half_db_th, rssi_half_db_offset, agc_gain_delay; 307 u32 filter_flag = 0; 308 309 printk("%s hw_init mode %d\n", xpu_compatible_str, mode); 310 311 //rst 312 for (i=0;i<8;i++) 313 xpu_api->XPU_REG_MULTI_RST_write(0); 314 for (i=0;i<32;i++) 315 xpu_api->XPU_REG_MULTI_RST_write(0xFFFFFFFF); 316 for (i=0;i<8;i++) 317 xpu_api->XPU_REG_MULTI_RST_write(0); 318 319 // http://www.studioreti.it/slide/802-11-Frame_E_C.pdf 320 // https://mrncciew.com/2014/10/14/cwap-802-11-phy-ppdu/ 321 // https://mrncciew.com/2014/09/27/cwap-mac-header-frame-control/ 322 // https://mrncciew.com/2014/10/25/cwap-mac-header-durationid/ 323 // https://mrncciew.com/2014/11/01/cwap-mac-header-sequence-control/ 324 // https://witestlab.poly.edu/blog/802-11-wireless-lan-2/ 325 // phy_rx byte idx: 326 // 5(3 sig + 2 service), -- PHY 327 // 2 frame control, 2 duration/conn ID, --MAC PDU 328 // 6 receiver address, 6 destination address, 6 transmitter address 329 // 2 sequence control 330 // 6 source address 331 // reg_val = 5 + 0; 332 // xpu_api->XPU_REG_PHY_RX_PKT_READ_OFFSET_write(reg_val); 333 // printk("%s hw_init XPU_REG_PHY_RX_PKT_READ_OFFSET_write %d\n", xpu_compatible_str, reg_val); 334 335 // by default turn off filter, because all register are zeros 336 // let's filter out packet according to: enum ieee80211_filter_flags at: https://www.kernel.org/doc/html/v4.9/80211/mac80211.html 337 #if 0 // define in FPGA 338 localparam [13:0] FIF_ALLMULTI = 14b00000000000010, //get all mac addr like 01:00:5E:xx:xx:xx and 33:33:xx:xx:xx:xx through to ARM 339 FIF_FCSFAIL = 14b00000000000100, //not support 340 FIF_PLCPFAIL = 14b00000000001000, //not support 341 FIF_BCN_PRBRESP_PROMISC= 14b00000000010000, 342 FIF_CONTROL = 14b00000000100000, 343 FIF_OTHER_BSS = 14b00000001000000, 344 FIF_PSPOLL = 14b00000010000000, 345 FIF_PROBE_REQ = 14b00000100000000, 346 UNICAST_FOR_US = 14b00001000000000, 347 BROADCAST_ALL_ONE = 14b00010000000000, 348 BROADCAST_ALL_ZERO = 14b00100000000000, 349 MY_BEACON = 14b01000000000000, 350 MONITOR_ALL = 14b10000000000000; 351 #endif 352 filter_flag = (FIF_ALLMULTI|FIF_FCSFAIL|FIF_PLCPFAIL|FIF_BCN_PRBRESP_PROMISC|FIF_CONTROL|FIF_OTHER_BSS|FIF_PSPOLL|FIF_PROBE_REQ|UNICAST_FOR_US|BROADCAST_ALL_ONE|BROADCAST_ALL_ZERO|MY_BEACON|MONITOR_ALL); 353 xpu_api->XPU_REG_FILTER_FLAG_write(filter_flag); 354 xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_write(0xB<<16);//6M 1011:0xB 355 356 // after send data frame wait for ACK, this will be set in real time in function ad9361_rf_set_channel 357 // xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2)*10)<<16) | 10 ); // high 16 bits to cover sig valid of ACK packet, low 16 bits is adjustment of fcs valid waiting time. let's add 2us for those device that is really "slow"! 358 // xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( 6*10 ); // +6 = 16us for 5GHz 359 360 //xpu_api->XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write(3); // if this > 0, it will override mac80211 set value, and set static retransmission limit 361 362 // xpu_api->XPU_REG_BB_RF_DELAY_write((1<<8)|47); 363 xpu_api->XPU_REG_BB_RF_DELAY_write((10<<8)|40); // extended rf is ongoing for perfect muting. (10<<8)|40 is verified good for zcu102/zed 364 365 // setup time schedule of 4 slices 366 // slice 0 367 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write(50000-1); // total 50ms 368 xpu_api->XPU_REG_SLICE_COUNT_START_write(0); //start 0ms 369 xpu_api->XPU_REG_SLICE_COUNT_END_write(50000-1); //end 50ms 370 371 // slice 1 372 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((1<<20)|(50000-1)); // total 50ms 373 xpu_api->XPU_REG_SLICE_COUNT_START_write((1<<20)|(0)); //start 0ms 374 //xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(20000-1)); //end 20ms 375 xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(50000-1)); //end 20ms 376 377 // slice 2 378 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((2<<20)|(50000-1)); // total 50ms 379 //xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(20000)); //start 20ms 380 xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(0)); //start 20ms 381 //xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(40000-1)); //end 20ms 382 xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(50000-1)); //end 20ms 383 384 // slice 3 385 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((3<<20)|(50000-1)); // total 50ms 386 //xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(40000)); //start 40ms 387 xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(0)); //start 40ms 388 //xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms 389 xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms 390 391 // all slice sync rest 392 xpu_api->XPU_REG_MULTI_RST_write(1<<7); //bit7 reset the counter for all queues at the same time 393 xpu_api->XPU_REG_MULTI_RST_write(0<<7); 394 395 switch(mode) 396 { 397 case XPU_TEST: 398 printk("%s hw_init mode XPU_TEST\n", xpu_compatible_str); 399 break; 400 401 case XPU_NORMAL: 402 printk("%s hw_init mode XPU_NORMAL\n", xpu_compatible_str); 403 break; 404 405 default: 406 printk("%s hw_init mode %d is wrong!\n", xpu_compatible_str, mode); 407 err=1; 408 } 409 xpu_api->XPU_REG_BAND_CHANNEL_write((false<<24)|(BAND_5_8GHZ<<16)|44);//use_short_slot==false; 5.8GHz; channel 44 -- default setting to sync with priv->band/channel/use_short_slot 410 411 agc_gain_delay = 50; //samples 412 rssi_half_db_offset = 75<<1; 413 xpu_api->XPU_REG_RSSI_DB_CFG_write(0x80000000|((rssi_half_db_offset<<16)|agc_gain_delay) ); 414 xpu_api->XPU_REG_RSSI_DB_CFG_write((~0x80000000)&((rssi_half_db_offset<<16)|agc_gain_delay) ); 415 416 //rssi_half_db_th = 70<<1; // with splitter 417 rssi_half_db_th = 87<<1; // -62dBm 418 xpu_api->XPU_REG_LBT_TH_write(rssi_half_db_th); // set IQ rssi th step .5dB to xxx and enable it 419 420 xpu_api->XPU_REG_FORCE_IDLE_MISC_write(75); //control the duration to force ch_idle after decoding a packet due to imperfection of agc and signals 421 422 //xpu_api->XPU_REG_CSMA_DEBUG_write((1<<31)|(20<<24)|(4<<19)|(3<<14)|(10<<7)|(5)); 423 xpu_api->XPU_REG_CSMA_DEBUG_write(0); 424 425 // xpu_api->XPU_REG_CSMA_CFG_write(268435459); // Linux will do config for each queue via openwifi_conf_tx 426 // xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); // Linux will do config for each queue via openwifi_conf_tx 427 428 xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((51)<<16)|0 );//now our tx send out I/Q immediately 429 430 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) 431 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) 432 433 xpu_api->XPU_REG_DIFS_ADVANCE_write(2); //us 434 435 printk("%s hw_init err %d\n", xpu_compatible_str, err); 436 return(err); 437 } 438 439 static int dev_probe(struct platform_device *pdev) 440 { 441 struct device_node *np = pdev->dev.of_node; 442 struct resource *io; 443 u32 test_us0, test_us1, test_us2; 444 int err=1; 445 446 printk("\n"); 447 448 if (np) { 449 const struct of_device_id *match; 450 451 match = of_match_node(dev_of_ids, np); 452 if (match) { 453 printk("%s dev_probe match!\n", xpu_compatible_str); 454 err = 0; 455 } 456 } 457 458 if (err) 459 return err; 460 461 xpu_api->hw_init=hw_init; 462 463 xpu_api->reg_read=reg_read; 464 xpu_api->reg_write=reg_write; 465 466 xpu_api->XPU_REG_MULTI_RST_write=XPU_REG_MULTI_RST_write; 467 xpu_api->XPU_REG_MULTI_RST_read=XPU_REG_MULTI_RST_read; 468 xpu_api->XPU_REG_SRC_SEL_write=XPU_REG_SRC_SEL_write; 469 xpu_api->XPU_REG_SRC_SEL_read=XPU_REG_SRC_SEL_read; 470 471 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write=XPU_REG_RECV_ACK_COUNT_TOP0_write; 472 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_read=XPU_REG_RECV_ACK_COUNT_TOP0_read; 473 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write=XPU_REG_RECV_ACK_COUNT_TOP1_write; 474 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_read=XPU_REG_RECV_ACK_COUNT_TOP1_read; 475 xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write=XPU_REG_SEND_ACK_WAIT_TOP_write; 476 xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_read=XPU_REG_SEND_ACK_WAIT_TOP_read; 477 xpu_api->XPU_REG_MAC_ADDR_LOW_write=XPU_REG_MAC_ADDR_LOW_write; 478 xpu_api->XPU_REG_MAC_ADDR_LOW_read=XPU_REG_MAC_ADDR_LOW_read; 479 xpu_api->XPU_REG_MAC_ADDR_HIGH_write=XPU_REG_MAC_ADDR_HIGH_write; 480 xpu_api->XPU_REG_MAC_ADDR_HIGH_read=XPU_REG_MAC_ADDR_HIGH_read; 481 482 xpu_api->XPU_REG_FILTER_FLAG_write=XPU_REG_FILTER_FLAG_write; 483 xpu_api->XPU_REG_FILTER_FLAG_read=XPU_REG_FILTER_FLAG_read; 484 xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_write=XPU_REG_CTS_TO_RTS_CONFIG_write; 485 xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_read=XPU_REG_CTS_TO_RTS_CONFIG_read; 486 xpu_api->XPU_REG_BSSID_FILTER_LOW_write=XPU_REG_BSSID_FILTER_LOW_write; 487 xpu_api->XPU_REG_BSSID_FILTER_LOW_read=XPU_REG_BSSID_FILTER_LOW_read; 488 xpu_api->XPU_REG_BSSID_FILTER_HIGH_write=XPU_REG_BSSID_FILTER_HIGH_write; 489 xpu_api->XPU_REG_BSSID_FILTER_HIGH_read=XPU_REG_BSSID_FILTER_HIGH_read; 490 491 xpu_api->XPU_REG_BAND_CHANNEL_write=XPU_REG_BAND_CHANNEL_write; 492 xpu_api->XPU_REG_BAND_CHANNEL_read=XPU_REG_BAND_CHANNEL_read; 493 494 xpu_api->XPU_REG_DIFS_ADVANCE_write=XPU_REG_DIFS_ADVANCE_write; 495 xpu_api->XPU_REG_DIFS_ADVANCE_read=XPU_REG_DIFS_ADVANCE_read; 496 497 xpu_api->XPU_REG_FORCE_IDLE_MISC_write=XPU_REG_FORCE_IDLE_MISC_write; 498 xpu_api->XPU_REG_FORCE_IDLE_MISC_read=XPU_REG_FORCE_IDLE_MISC_read; 499 500 xpu_api->XPU_REG_TRX_STATUS_read=XPU_REG_TRX_STATUS_read; 501 xpu_api->XPU_REG_TX_RESULT_read=XPU_REG_TX_RESULT_read; 502 503 xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read=XPU_REG_TSF_RUNTIME_VAL_LOW_read; 504 xpu_api->XPU_REG_TSF_RUNTIME_VAL_HIGH_read=XPU_REG_TSF_RUNTIME_VAL_HIGH_read; 505 xpu_api->XPU_REG_TSF_LOAD_VAL_LOW_write=XPU_REG_TSF_LOAD_VAL_LOW_write; 506 xpu_api->XPU_REG_TSF_LOAD_VAL_HIGH_write=XPU_REG_TSF_LOAD_VAL_HIGH_write; 507 xpu_api->XPU_REG_TSF_LOAD_VAL_write=XPU_REG_TSF_LOAD_VAL_write; 508 509 xpu_api->XPU_REG_FC_DI_read=XPU_REG_FC_DI_read; 510 xpu_api->XPU_REG_ADDR1_LOW_read=XPU_REG_ADDR1_LOW_read; 511 xpu_api->XPU_REG_ADDR1_HIGH_read=XPU_REG_ADDR1_HIGH_read; 512 xpu_api->XPU_REG_ADDR2_LOW_read=XPU_REG_ADDR2_LOW_read; 513 xpu_api->XPU_REG_ADDR2_HIGH_read=XPU_REG_ADDR2_HIGH_read; 514 515 xpu_api->XPU_REG_LBT_TH_write=XPU_REG_LBT_TH_write; 516 xpu_api->XPU_REG_LBT_TH_read=XPU_REG_LBT_TH_read; 517 518 xpu_api->XPU_REG_RSSI_DB_CFG_read=XPU_REG_RSSI_DB_CFG_read; 519 xpu_api->XPU_REG_RSSI_DB_CFG_write=XPU_REG_RSSI_DB_CFG_write; 520 521 xpu_api->XPU_REG_CSMA_DEBUG_write=XPU_REG_CSMA_DEBUG_write; 522 xpu_api->XPU_REG_CSMA_DEBUG_read=XPU_REG_CSMA_DEBUG_read; 523 524 xpu_api->XPU_REG_CSMA_CFG_write=XPU_REG_CSMA_CFG_write; 525 xpu_api->XPU_REG_CSMA_CFG_read=XPU_REG_CSMA_CFG_read; 526 527 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write=XPU_REG_SLICE_COUNT_TOTAL_write; 528 xpu_api->XPU_REG_SLICE_COUNT_START_write=XPU_REG_SLICE_COUNT_START_write; 529 xpu_api->XPU_REG_SLICE_COUNT_END_write=XPU_REG_SLICE_COUNT_END_write; 530 531 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_read=XPU_REG_SLICE_COUNT_TOTAL_read; 532 xpu_api->XPU_REG_SLICE_COUNT_START_read=XPU_REG_SLICE_COUNT_START_read; 533 xpu_api->XPU_REG_SLICE_COUNT_END_read=XPU_REG_SLICE_COUNT_END_read; 534 535 xpu_api->XPU_REG_BB_RF_DELAY_write=XPU_REG_BB_RF_DELAY_write; 536 537 xpu_api->XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write=XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write; 538 xpu_api->XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read=XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read; 539 540 xpu_api->XPU_REG_AMPDU_ACTION_write=XPU_REG_AMPDU_ACTION_write; 541 xpu_api->XPU_REG_AMPDU_ACTION_read=XPU_REG_AMPDU_ACTION_read; 542 543 xpu_api->XPU_REG_MAC_ADDR_write=XPU_REG_MAC_ADDR_write; 544 545 /* Request and map I/O memory */ 546 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 547 base_addr = devm_ioremap_resource(&pdev->dev, io); 548 if (IS_ERR(base_addr)) 549 return PTR_ERR(base_addr); 550 551 printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", xpu_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); 552 printk("%s dev_probe base_addr 0x%08x\n", xpu_compatible_str,(u32)base_addr); 553 printk("%s dev_probe xpu_driver_api_inst 0x%08x\n", xpu_compatible_str, (u32)&xpu_driver_api_inst); 554 printk("%s dev_probe xpu_api 0x%08x\n", xpu_compatible_str, (u32)xpu_api); 555 556 printk("%s dev_probe reset tsf timer\n", xpu_compatible_str); 557 xpu_api->XPU_REG_TSF_LOAD_VAL_write(0,0); 558 test_us0 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read(); 559 mdelay(33); 560 test_us1 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read(); 561 mdelay(67); 562 test_us2 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read(); 563 printk("%s dev_probe XPU_REG_TSF_RUNTIME_VAL_LOW_read %d %d %dus\n", xpu_compatible_str, test_us0, test_us1, test_us2); 564 565 printk("%s dev_probe succeed!\n", xpu_compatible_str); 566 567 err = hw_init(XPU_NORMAL); 568 569 return err; 570 } 571 572 static int dev_remove(struct platform_device *pdev) 573 { 574 printk("\n"); 575 576 printk("%s dev_remove base_addr 0x%08x\n", xpu_compatible_str,(u32)base_addr); 577 printk("%s dev_remove xpu_driver_api_inst 0x%08x\n", xpu_compatible_str, (u32)&xpu_driver_api_inst); 578 printk("%s dev_remove xpu_api 0x%08x\n", xpu_compatible_str, (u32)xpu_api); 579 580 printk("%s dev_remove succeed!\n", xpu_compatible_str); 581 return 0; 582 } 583 584 static struct platform_driver dev_driver = { 585 .driver = { 586 .name = "sdr,xpu", 587 .owner = THIS_MODULE, 588 .of_match_table = dev_of_ids, 589 }, 590 .probe = dev_probe, 591 .remove = dev_remove, 592 }; 593 594 module_platform_driver(dev_driver); 595 596 MODULE_AUTHOR("Xianjun Jiao"); 597 MODULE_DESCRIPTION("sdr,xpu"); 598 MODULE_LICENSE("GPL v2"); 599