1 /* 2 * axi lite register access driver 3 * Xianjun jiao. [email protected]; [email protected] 4 */ 5 6 #include <linux/bitops.h> 7 #include <linux/dmapool.h> 8 #include <linux/dma/xilinx_dma.h> 9 #include <linux/init.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/module.h> 14 #include <linux/of_address.h> 15 #include <linux/of_dma.h> 16 #include <linux/of_platform.h> 17 #include <linux/of_irq.h> 18 #include <linux/slab.h> 19 #include <linux/clk.h> 20 #include <linux/io-64-nonatomic-lo-hi.h> 21 #include <linux/delay.h> 22 #include <net/mac80211.h> 23 24 #include "../hw_def.h" 25 26 static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design 27 28 /* IO accessors */ 29 static inline u32 reg_read(u32 reg) 30 { 31 return ioread32(base_addr + reg); 32 } 33 34 static inline void reg_write(u32 reg, u32 value) 35 { 36 iowrite32(value, base_addr + reg); 37 } 38 39 static inline void XPU_REG_MULTI_RST_write(u32 Data) { 40 reg_write(XPU_REG_MULTI_RST_ADDR, Data); 41 } 42 43 static inline u32 XPU_REG_MULTI_RST_read(void){ 44 return reg_read(XPU_REG_MULTI_RST_ADDR); 45 } 46 47 static inline void XPU_REG_SRC_SEL_write(u32 Data) { 48 reg_write(XPU_REG_SRC_SEL_ADDR, Data); 49 } 50 51 static inline u32 XPU_REG_SRC_SEL_read(void){ 52 return reg_read(XPU_REG_SRC_SEL_ADDR); 53 } 54 55 static inline void XPU_REG_RECV_ACK_COUNT_TOP0_write(u32 Data) { 56 reg_write(XPU_REG_RECV_ACK_COUNT_TOP0_ADDR, Data); 57 } 58 59 static inline u32 XPU_REG_RECV_ACK_COUNT_TOP0_read(void){ 60 return reg_read(XPU_REG_RECV_ACK_COUNT_TOP0_ADDR); 61 } 62 63 static inline void XPU_REG_RECV_ACK_COUNT_TOP1_write(u32 Data) { 64 reg_write(XPU_REG_RECV_ACK_COUNT_TOP1_ADDR, Data); 65 } 66 67 static inline u32 XPU_REG_RECV_ACK_COUNT_TOP1_read(void){ 68 return reg_read(XPU_REG_RECV_ACK_COUNT_TOP1_ADDR); 69 } 70 71 static inline void XPU_REG_SEND_ACK_WAIT_TOP_write(u32 Data) { 72 reg_write(XPU_REG_SEND_ACK_WAIT_TOP_ADDR, Data); 73 } 74 75 static inline u32 XPU_REG_SEND_ACK_WAIT_TOP_read(void){ 76 return reg_read(XPU_REG_SEND_ACK_WAIT_TOP_ADDR); 77 } 78 79 static inline void XPU_REG_FILTER_FLAG_write(u32 Data) { 80 reg_write(XPU_REG_FILTER_FLAG_ADDR, Data); 81 } 82 83 static inline u32 XPU_REG_FILTER_FLAG_read(void){ 84 return reg_read(XPU_REG_FILTER_FLAG_ADDR); 85 } 86 87 static inline void XPU_REG_CTS_TO_RTS_CONFIG_write(u32 Data) { 88 reg_write(XPU_REG_CTS_TO_RTS_CONFIG_ADDR, Data); 89 } 90 91 static inline u32 XPU_REG_CTS_TO_RTS_CONFIG_read(void){ 92 return reg_read(XPU_REG_CTS_TO_RTS_CONFIG_ADDR); 93 } 94 95 static inline void XPU_REG_MAC_ADDR_LOW_write(u32 Data) { 96 reg_write(XPU_REG_MAC_ADDR_LOW_ADDR, Data); 97 } 98 99 static inline u32 XPU_REG_MAC_ADDR_LOW_read(void){ 100 return reg_read(XPU_REG_MAC_ADDR_LOW_ADDR); 101 } 102 103 static inline void XPU_REG_MAC_ADDR_HIGH_write(u32 Data) { 104 reg_write(XPU_REG_MAC_ADDR_HIGH_ADDR, Data); 105 } 106 107 static inline u32 XPU_REG_MAC_ADDR_HIGH_read(void){ 108 return reg_read(XPU_REG_MAC_ADDR_HIGH_ADDR); 109 } 110 111 static inline void XPU_REG_BSSID_FILTER_LOW_write(u32 Data) { 112 reg_write(XPU_REG_BSSID_FILTER_LOW_ADDR, Data); 113 } 114 115 static inline u32 XPU_REG_BSSID_FILTER_LOW_read(void){ 116 return reg_read(XPU_REG_BSSID_FILTER_LOW_ADDR); 117 } 118 119 static inline void XPU_REG_BSSID_FILTER_HIGH_write(u32 Data) { 120 reg_write(XPU_REG_BSSID_FILTER_HIGH_ADDR, Data); 121 } 122 123 static inline u32 XPU_REG_BSSID_FILTER_HIGH_read(void){ 124 return reg_read(XPU_REG_BSSID_FILTER_HIGH_ADDR); 125 } 126 127 static inline void XPU_REG_BAND_CHANNEL_write(u32 Data) { 128 reg_write(XPU_REG_BAND_CHANNEL_ADDR, Data); 129 } 130 131 static inline u32 XPU_REG_BAND_CHANNEL_read(void){ 132 return reg_read(XPU_REG_BAND_CHANNEL_ADDR); 133 } 134 135 static inline void XPU_REG_DIFS_ADVANCE_write(u32 Data) { 136 reg_write(XPU_REG_DIFS_ADVANCE_ADDR, Data); 137 } 138 139 static inline u32 XPU_REG_DIFS_ADVANCE_read(void){ 140 return reg_read(XPU_REG_DIFS_ADVANCE_ADDR); 141 } 142 143 static inline u32 XPU_REG_TRX_STATUS_read(void){ 144 return reg_read(XPU_REG_TRX_STATUS_ADDR); 145 } 146 147 static inline u32 XPU_REG_TX_RESULT_read(void){ 148 return reg_read(XPU_REG_TX_RESULT_ADDR); 149 } 150 151 static inline u32 XPU_REG_TSF_RUNTIME_VAL_LOW_read(void){ 152 return reg_read(XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR); 153 } 154 155 static inline u32 XPU_REG_TSF_RUNTIME_VAL_HIGH_read(void){ 156 return reg_read(XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR); 157 } 158 159 static inline void XPU_REG_TSF_LOAD_VAL_LOW_write(u32 value){ 160 reg_write(XPU_REG_TSF_LOAD_VAL_LOW_ADDR, value); 161 } 162 163 static inline void XPU_REG_TSF_LOAD_VAL_HIGH_write(u32 value){ 164 reg_write(XPU_REG_TSF_LOAD_VAL_HIGH_ADDR, value); 165 } 166 167 static inline void XPU_REG_TSF_LOAD_VAL_write(u32 high_value, u32 low_value){ 168 XPU_REG_TSF_LOAD_VAL_LOW_write(low_value); 169 XPU_REG_TSF_LOAD_VAL_HIGH_write(high_value|0x80000000); // msb high 170 XPU_REG_TSF_LOAD_VAL_HIGH_write(high_value&(~0x80000000)); // msb low 171 } 172 173 static inline u32 XPU_REG_FC_DI_read(void){ 174 return reg_read(XPU_REG_FC_DI_ADDR); 175 } 176 177 static inline u32 XPU_REG_ADDR1_LOW_read(void){ 178 return reg_read(XPU_REG_ADDR1_LOW_ADDR); 179 } 180 181 static inline u32 XPU_REG_ADDR1_HIGH_read(void){ 182 return reg_read(XPU_REG_ADDR1_HIGH_ADDR); 183 } 184 185 static inline u32 XPU_REG_ADDR2_LOW_read(void){ 186 return reg_read(XPU_REG_ADDR2_LOW_ADDR); 187 } 188 189 static inline u32 XPU_REG_ADDR2_HIGH_read(void){ 190 return reg_read(XPU_REG_ADDR2_HIGH_ADDR); 191 } 192 193 // static inline void XPU_REG_LBT_TH_write(u32 value, u32 en_flag) { 194 // if (en_flag) { 195 // reg_write(XPU_REG_LBT_TH_ADDR, value&0x7FFFFFFF); 196 // } else { 197 // reg_write(XPU_REG_LBT_TH_ADDR, value|0x80000000); 198 // } 199 // } 200 201 static inline void XPU_REG_LBT_TH_write(u32 value) { 202 reg_write(XPU_REG_LBT_TH_ADDR, value); 203 } 204 205 static inline u32 XPU_REG_RSSI_DB_CFG_read(void){ 206 return reg_read(XPU_REG_RSSI_DB_CFG_ADDR); 207 } 208 209 static inline void XPU_REG_RSSI_DB_CFG_write(u32 Data) { 210 reg_write(XPU_REG_RSSI_DB_CFG_ADDR, Data); 211 } 212 213 static inline u32 XPU_REG_LBT_TH_read(void){ 214 return reg_read(XPU_REG_LBT_TH_ADDR); 215 } 216 217 static inline void XPU_REG_CSMA_DEBUG_write(u32 value){ 218 reg_write(XPU_REG_CSMA_DEBUG_ADDR, value); 219 } 220 221 static inline u32 XPU_REG_CSMA_DEBUG_read(void){ 222 return reg_read(XPU_REG_CSMA_DEBUG_ADDR); 223 } 224 225 static inline void XPU_REG_CSMA_CFG_write(u32 value){ 226 reg_write(XPU_REG_CSMA_CFG_ADDR, value); 227 } 228 229 static inline u32 XPU_REG_CSMA_CFG_read(void){ 230 return reg_read(XPU_REG_CSMA_CFG_ADDR); 231 } 232 233 static inline void XPU_REG_SLICE_COUNT_TOTAL_write(u32 value){ 234 reg_write(XPU_REG_SLICE_COUNT_TOTAL_ADDR, value); 235 } 236 static inline void XPU_REG_SLICE_COUNT_START_write(u32 value){ 237 reg_write(XPU_REG_SLICE_COUNT_START_ADDR, value); 238 } 239 static inline void XPU_REG_SLICE_COUNT_END_write(u32 value){ 240 reg_write(XPU_REG_SLICE_COUNT_END_ADDR, value); 241 } 242 243 244 static inline u32 XPU_REG_SLICE_COUNT_TOTAL_read(void){ 245 return reg_read(XPU_REG_SLICE_COUNT_TOTAL_ADDR); 246 } 247 static inline u32 XPU_REG_SLICE_COUNT_START_read(void){ 248 return reg_read(XPU_REG_SLICE_COUNT_START_ADDR); 249 } 250 static inline u32 XPU_REG_SLICE_COUNT_END_read(void){ 251 return reg_read(XPU_REG_SLICE_COUNT_END_ADDR); 252 } 253 254 255 static inline void XPU_REG_BB_RF_DELAY_write(u32 value){ 256 reg_write(XPU_REG_BB_RF_DELAY_ADDR, value); 257 } 258 259 static inline void XPU_REG_MAX_NUM_RETRANS_write(u32 value){ 260 reg_write(XPU_REG_MAX_NUM_RETRANS_ADDR, value); 261 } 262 263 static inline void XPU_REG_MAC_ADDR_write(u8 *mac_addr) {//, u32 en_flag){ 264 XPU_REG_MAC_ADDR_LOW_write( *( (u32*)(mac_addr) ) ); 265 XPU_REG_MAC_ADDR_HIGH_write( *( (u16*)(mac_addr + 4) ) ); 266 #if 0 267 if (en_flag) { 268 XPU_REG_MAC_ADDR_HIGH_write( (*( (u16*)(mac_addr + 4) )) | 0x80000000 ); // 0x80000000 by default we turn on mac addr filter 269 } else { 270 XPU_REG_MAC_ADDR_HIGH_write( (*( (u16*)(mac_addr + 4) )) & 0x7FFFFFFF ); 271 } 272 #endif 273 } 274 275 static const struct of_device_id dev_of_ids[] = { 276 { .compatible = "sdr,xpu", }, 277 {} 278 }; 279 MODULE_DEVICE_TABLE(of, dev_of_ids); 280 281 static struct xpu_driver_api xpu_driver_api_inst; 282 static struct xpu_driver_api *xpu_api = &xpu_driver_api_inst; 283 EXPORT_SYMBOL(xpu_api); 284 285 static inline u32 hw_init(enum xpu_mode mode){ 286 int err=0, i, rssi_half_db_th, rssi_half_db_offset, agc_gain_delay; 287 u32 filter_flag = 0, reg_val; 288 289 printk("%s hw_init mode %d\n", xpu_compatible_str, mode); 290 291 //rst 292 for (i=0;i<8;i++) 293 xpu_api->XPU_REG_MULTI_RST_write(0); 294 for (i=0;i<32;i++) 295 xpu_api->XPU_REG_MULTI_RST_write(0xFFFFFFFF); 296 for (i=0;i<8;i++) 297 xpu_api->XPU_REG_MULTI_RST_write(0); 298 299 // http://www.studioreti.it/slide/802-11-Frame_E_C.pdf 300 // https://mrncciew.com/2014/10/14/cwap-802-11-phy-ppdu/ 301 // https://mrncciew.com/2014/09/27/cwap-mac-header-frame-control/ 302 // https://mrncciew.com/2014/10/25/cwap-mac-header-durationid/ 303 // https://mrncciew.com/2014/11/01/cwap-mac-header-sequence-control/ 304 // https://witestlab.poly.edu/blog/802-11-wireless-lan-2/ 305 // phy_rx byte idx: 306 // 5(3 sig + 2 service), -- PHY 307 // 2 frame control, 2 duration/conn ID, --MAC PDU 308 // 6 receiver address, 6 destination address, 6 transmitter address 309 // 2 sequence control 310 // 6 source address 311 // reg_val = 5 + 0; 312 // xpu_api->XPU_REG_PHY_RX_PKT_READ_OFFSET_write(reg_val); 313 // printk("%s hw_init XPU_REG_PHY_RX_PKT_READ_OFFSET_write %d\n", xpu_compatible_str, reg_val); 314 315 // by default turn off filter, because all register are zeros 316 // let's filter out packet according to: enum ieee80211_filter_flags at: https://www.kernel.org/doc/html/v4.9/80211/mac80211.html 317 #if 0 // define in FPGA 318 localparam [13:0] FIF_ALLMULTI = 14b00000000000010, //get all mac addr like 01:00:5E:xx:xx:xx and 33:33:xx:xx:xx:xx through to ARM 319 FIF_FCSFAIL = 14b00000000000100, //not support 320 FIF_PLCPFAIL = 14b00000000001000, //not support 321 FIF_BCN_PRBRESP_PROMISC= 14b00000000010000, 322 FIF_CONTROL = 14b00000000100000, 323 FIF_OTHER_BSS = 14b00000001000000, 324 FIF_PSPOLL = 14b00000010000000, 325 FIF_PROBE_REQ = 14b00000100000000, 326 UNICAST_FOR_US = 14b00001000000000, 327 BROADCAST_ALL_ONE = 14b00010000000000, 328 BROADCAST_ALL_ZERO = 14b00100000000000, 329 MY_BEACON = 14b01000000000000, 330 MONITOR_ALL = 14b10000000000000; 331 #endif 332 filter_flag = (FIF_ALLMULTI|FIF_FCSFAIL|FIF_PLCPFAIL|FIF_BCN_PRBRESP_PROMISC|FIF_CONTROL|FIF_OTHER_BSS|FIF_PSPOLL|FIF_PROBE_REQ|UNICAST_FOR_US|BROADCAST_ALL_ONE|BROADCAST_ALL_ZERO|MY_BEACON|MONITOR_ALL); 333 xpu_api->XPU_REG_FILTER_FLAG_write(filter_flag); 334 xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_write(0xB<<16);//6M 1011:0xB 335 336 // after send data frame wait for ACK, this will be set in real time in function ad9361_rf_set_channel 337 // xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2)*10)<<16) | 10 ); // high 16 bits to cover sig valid of ACK packet, low 16 bits is adjustment of fcs valid waiting time. let's add 2us for those device that is really "slow"! 338 // xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( 6*10 ); // +6 = 16us for 5GHz 339 340 //xpu_api->XPU_REG_MAX_NUM_RETRANS_write(3); // if this > 0, it will override mac80211 set value, and set static retransmission limit 341 342 // xpu_api->XPU_REG_BB_RF_DELAY_write((1<<8)|47); 343 xpu_api->XPU_REG_BB_RF_DELAY_write((10<<8)|40); // extended rf is ongoing for perfect muting. (10<<8)|40 is verified good for zcu102/zed 344 345 // setup time schedule of 4 slices 346 // slice 0 347 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write(50000-1); // total 50ms 348 xpu_api->XPU_REG_SLICE_COUNT_START_write(0); //start 0ms 349 xpu_api->XPU_REG_SLICE_COUNT_END_write(50000-1); //end 50ms 350 351 // slice 1 352 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((1<<20)|(50000-1)); // total 50ms 353 xpu_api->XPU_REG_SLICE_COUNT_START_write((1<<20)|(0)); //start 0ms 354 //xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(20000-1)); //end 20ms 355 xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(50000-1)); //end 20ms 356 357 // slice 2 358 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((2<<20)|(50000-1)); // total 50ms 359 //xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(20000)); //start 20ms 360 xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(0)); //start 20ms 361 //xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(40000-1)); //end 20ms 362 xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(50000-1)); //end 20ms 363 364 // slice 3 365 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((3<<20)|(50000-1)); // total 50ms 366 //xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(40000)); //start 40ms 367 xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(0)); //start 40ms 368 //xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms 369 xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms 370 371 // all slice sync rest 372 xpu_api->XPU_REG_MULTI_RST_write(1<<7); //bit7 reset the counter for all queues at the same time 373 xpu_api->XPU_REG_MULTI_RST_write(0<<7); 374 375 switch(mode) 376 { 377 case XPU_TEST: 378 printk("%s hw_init mode XPU_TEST\n", xpu_compatible_str); 379 break; 380 381 case XPU_NORMAL: 382 printk("%s hw_init mode XPU_NORMAL\n", xpu_compatible_str); 383 break; 384 385 default: 386 printk("%s hw_init mode %d is wrong!\n", xpu_compatible_str, mode); 387 err=1; 388 } 389 xpu_api->XPU_REG_BAND_CHANNEL_write((false<<24)|(BAND_5_8GHZ<<16)|44);//use_short_slot==false; 5.8GHz; channel 44 -- default setting to sync with priv->band/channel/use_short_slot 390 391 agc_gain_delay = 50; //samples 392 rssi_half_db_offset = 75<<1; 393 xpu_api->XPU_REG_RSSI_DB_CFG_write(0x80000000|((rssi_half_db_offset<<16)|agc_gain_delay) ); 394 xpu_api->XPU_REG_RSSI_DB_CFG_write((~0x80000000)&((rssi_half_db_offset<<16)|agc_gain_delay) ); 395 396 //rssi_half_db_th = 70<<1; // with splitter 397 rssi_half_db_th = 87<<1; // -62dBm 398 reg_val=xpu_api->XPU_REG_LBT_TH_read(); 399 xpu_api->XPU_REG_LBT_TH_write((reg_val & 0xFFFF0000) | rssi_half_db_th); // set IQ rssi th step .5dB to xxx and enable it 400 401 //xpu_api->XPU_REG_CSMA_DEBUG_write((1<<31)|(20<<24)|(4<<19)|(3<<14)|(10<<7)|(5)); 402 xpu_api->XPU_REG_CSMA_DEBUG_write(0); 403 404 xpu_api->XPU_REG_CSMA_CFG_write(268435459); // 0x10000003, min CSMA cw exp = 3, set bit 28 high for dynamic CW 405 // xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); //high priority 406 407 xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((51)<<16)|0 );//now our tx send out I/Q immediately 408 409 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) 410 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) 411 412 xpu_api->XPU_REG_DIFS_ADVANCE_write(2); //us 413 414 printk("%s hw_init err %d\n", xpu_compatible_str, err); 415 return(err); 416 } 417 418 static int dev_probe(struct platform_device *pdev) 419 { 420 struct device_node *np = pdev->dev.of_node; 421 struct resource *io; 422 u32 test_us0, test_us1, test_us2; 423 int err=1; 424 425 printk("\n"); 426 427 if (np) { 428 const struct of_device_id *match; 429 430 match = of_match_node(dev_of_ids, np); 431 if (match) { 432 printk("%s dev_probe match!\n", xpu_compatible_str); 433 err = 0; 434 } 435 } 436 437 if (err) 438 return err; 439 440 xpu_api->hw_init=hw_init; 441 442 xpu_api->reg_read=reg_read; 443 xpu_api->reg_write=reg_write; 444 445 xpu_api->XPU_REG_MULTI_RST_write=XPU_REG_MULTI_RST_write; 446 xpu_api->XPU_REG_MULTI_RST_read=XPU_REG_MULTI_RST_read; 447 xpu_api->XPU_REG_SRC_SEL_write=XPU_REG_SRC_SEL_write; 448 xpu_api->XPU_REG_SRC_SEL_read=XPU_REG_SRC_SEL_read; 449 450 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write=XPU_REG_RECV_ACK_COUNT_TOP0_write; 451 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_read=XPU_REG_RECV_ACK_COUNT_TOP0_read; 452 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write=XPU_REG_RECV_ACK_COUNT_TOP1_write; 453 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_read=XPU_REG_RECV_ACK_COUNT_TOP1_read; 454 xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write=XPU_REG_SEND_ACK_WAIT_TOP_write; 455 xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_read=XPU_REG_SEND_ACK_WAIT_TOP_read; 456 xpu_api->XPU_REG_MAC_ADDR_LOW_write=XPU_REG_MAC_ADDR_LOW_write; 457 xpu_api->XPU_REG_MAC_ADDR_LOW_read=XPU_REG_MAC_ADDR_LOW_read; 458 xpu_api->XPU_REG_MAC_ADDR_HIGH_write=XPU_REG_MAC_ADDR_HIGH_write; 459 xpu_api->XPU_REG_MAC_ADDR_HIGH_read=XPU_REG_MAC_ADDR_HIGH_read; 460 461 xpu_api->XPU_REG_FILTER_FLAG_write=XPU_REG_FILTER_FLAG_write; 462 xpu_api->XPU_REG_FILTER_FLAG_read=XPU_REG_FILTER_FLAG_read; 463 xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_write=XPU_REG_CTS_TO_RTS_CONFIG_write; 464 xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_read=XPU_REG_CTS_TO_RTS_CONFIG_read; 465 xpu_api->XPU_REG_BSSID_FILTER_LOW_write=XPU_REG_BSSID_FILTER_LOW_write; 466 xpu_api->XPU_REG_BSSID_FILTER_LOW_read=XPU_REG_BSSID_FILTER_LOW_read; 467 xpu_api->XPU_REG_BSSID_FILTER_HIGH_write=XPU_REG_BSSID_FILTER_HIGH_write; 468 xpu_api->XPU_REG_BSSID_FILTER_HIGH_read=XPU_REG_BSSID_FILTER_HIGH_read; 469 470 xpu_api->XPU_REG_BAND_CHANNEL_write=XPU_REG_BAND_CHANNEL_write; 471 xpu_api->XPU_REG_BAND_CHANNEL_read=XPU_REG_BAND_CHANNEL_read; 472 473 xpu_api->XPU_REG_DIFS_ADVANCE_write=XPU_REG_DIFS_ADVANCE_write; 474 xpu_api->XPU_REG_DIFS_ADVANCE_read=XPU_REG_DIFS_ADVANCE_read; 475 476 xpu_api->XPU_REG_TRX_STATUS_read=XPU_REG_TRX_STATUS_read; 477 xpu_api->XPU_REG_TX_RESULT_read=XPU_REG_TX_RESULT_read; 478 479 xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read=XPU_REG_TSF_RUNTIME_VAL_LOW_read; 480 xpu_api->XPU_REG_TSF_RUNTIME_VAL_HIGH_read=XPU_REG_TSF_RUNTIME_VAL_HIGH_read; 481 xpu_api->XPU_REG_TSF_LOAD_VAL_LOW_write=XPU_REG_TSF_LOAD_VAL_LOW_write; 482 xpu_api->XPU_REG_TSF_LOAD_VAL_HIGH_write=XPU_REG_TSF_LOAD_VAL_HIGH_write; 483 xpu_api->XPU_REG_TSF_LOAD_VAL_write=XPU_REG_TSF_LOAD_VAL_write; 484 485 xpu_api->XPU_REG_FC_DI_read=XPU_REG_FC_DI_read; 486 xpu_api->XPU_REG_ADDR1_LOW_read=XPU_REG_ADDR1_LOW_read; 487 xpu_api->XPU_REG_ADDR1_HIGH_read=XPU_REG_ADDR1_HIGH_read; 488 xpu_api->XPU_REG_ADDR2_LOW_read=XPU_REG_ADDR2_LOW_read; 489 xpu_api->XPU_REG_ADDR2_HIGH_read=XPU_REG_ADDR2_HIGH_read; 490 491 xpu_api->XPU_REG_LBT_TH_write=XPU_REG_LBT_TH_write; 492 xpu_api->XPU_REG_LBT_TH_read=XPU_REG_LBT_TH_read; 493 494 xpu_api->XPU_REG_RSSI_DB_CFG_read=XPU_REG_RSSI_DB_CFG_read; 495 xpu_api->XPU_REG_RSSI_DB_CFG_write=XPU_REG_RSSI_DB_CFG_write; 496 497 xpu_api->XPU_REG_CSMA_DEBUG_write=XPU_REG_CSMA_DEBUG_write; 498 xpu_api->XPU_REG_CSMA_DEBUG_read=XPU_REG_CSMA_DEBUG_read; 499 500 xpu_api->XPU_REG_CSMA_CFG_write=XPU_REG_CSMA_CFG_write; 501 xpu_api->XPU_REG_CSMA_CFG_read=XPU_REG_CSMA_CFG_read; 502 503 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write=XPU_REG_SLICE_COUNT_TOTAL_write; 504 xpu_api->XPU_REG_SLICE_COUNT_START_write=XPU_REG_SLICE_COUNT_START_write; 505 xpu_api->XPU_REG_SLICE_COUNT_END_write=XPU_REG_SLICE_COUNT_END_write; 506 507 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_read=XPU_REG_SLICE_COUNT_TOTAL_read; 508 xpu_api->XPU_REG_SLICE_COUNT_START_read=XPU_REG_SLICE_COUNT_START_read; 509 xpu_api->XPU_REG_SLICE_COUNT_END_read=XPU_REG_SLICE_COUNT_END_read; 510 511 xpu_api->XPU_REG_BB_RF_DELAY_write=XPU_REG_BB_RF_DELAY_write; 512 xpu_api->XPU_REG_MAX_NUM_RETRANS_write=XPU_REG_MAX_NUM_RETRANS_write; 513 514 xpu_api->XPU_REG_MAC_ADDR_write=XPU_REG_MAC_ADDR_write; 515 516 /* Request and map I/O memory */ 517 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 518 base_addr = devm_ioremap_resource(&pdev->dev, io); 519 if (IS_ERR(base_addr)) 520 return PTR_ERR(base_addr); 521 522 printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", xpu_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); 523 printk("%s dev_probe base_addr 0x%08x\n", xpu_compatible_str,(u32)base_addr); 524 printk("%s dev_probe xpu_driver_api_inst 0x%08x\n", xpu_compatible_str, (u32)&xpu_driver_api_inst); 525 printk("%s dev_probe xpu_api 0x%08x\n", xpu_compatible_str, (u32)xpu_api); 526 527 printk("%s dev_probe reset tsf timer\n", xpu_compatible_str); 528 xpu_api->XPU_REG_TSF_LOAD_VAL_write(0,0); 529 test_us0 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read(); 530 mdelay(33); 531 test_us1 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read(); 532 mdelay(67); 533 test_us2 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read(); 534 printk("%s dev_probe XPU_REG_TSF_RUNTIME_VAL_LOW_read %d %d %dus\n", xpu_compatible_str, test_us0, test_us1, test_us2); 535 536 printk("%s dev_probe succeed!\n", xpu_compatible_str); 537 538 err = hw_init(XPU_NORMAL); 539 540 return err; 541 } 542 543 static int dev_remove(struct platform_device *pdev) 544 { 545 printk("\n"); 546 547 printk("%s dev_remove base_addr 0x%08x\n", xpu_compatible_str,(u32)base_addr); 548 printk("%s dev_remove xpu_driver_api_inst 0x%08x\n", xpu_compatible_str, (u32)&xpu_driver_api_inst); 549 printk("%s dev_remove xpu_api 0x%08x\n", xpu_compatible_str, (u32)xpu_api); 550 551 printk("%s dev_remove succeed!\n", xpu_compatible_str); 552 return 0; 553 } 554 555 static struct platform_driver dev_driver = { 556 .driver = { 557 .name = "sdr,xpu", 558 .owner = THIS_MODULE, 559 .of_match_table = dev_of_ids, 560 }, 561 .probe = dev_probe, 562 .remove = dev_remove, 563 }; 564 565 module_platform_driver(dev_driver); 566 567 MODULE_AUTHOR("Xianjun Jiao"); 568 MODULE_DESCRIPTION("sdr,xpu"); 569 MODULE_LICENSE("GPL v2"); 570