1 /* 2 * axi lite register access driver 3 * Author: Xianjun Jiao, Michael Mehari, Wei Liu 4 * SPDX-FileCopyrightText: 2019 UGent 5 * SPDX-License-Identifier: AGPL-3.0-or-later 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/dmapool.h> 10 #include <linux/dma/xilinx_dma.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/of_dma.h> 18 #include <linux/of_platform.h> 19 #include <linux/of_irq.h> 20 #include <linux/slab.h> 21 #include <linux/clk.h> 22 #include <linux/io-64-nonatomic-lo-hi.h> 23 24 #include "../hw_def.h" 25 26 static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design 27 28 /* IO accessors */ 29 static inline u32 reg_read(u32 reg) 30 { 31 return ioread32(base_addr + reg); 32 } 33 34 static inline void reg_write(u32 reg, u32 value) 35 { 36 iowrite32(value, base_addr + reg); 37 } 38 39 static inline u32 TX_INTF_REG_MULTI_RST_read(void){ 40 return reg_read(TX_INTF_REG_MULTI_RST_ADDR); 41 } 42 43 static inline u32 TX_INTF_REG_ARBITRARY_IQ_read(void){ 44 return reg_read(TX_INTF_REG_ARBITRARY_IQ_ADDR); 45 } 46 47 static inline u32 TX_INTF_REG_WIFI_TX_MODE_read(void){ 48 return reg_read(TX_INTF_REG_WIFI_TX_MODE_ADDR); 49 } 50 51 static inline u32 TX_INTF_REG_CTS_TOSELF_CONFIG_read(void){ 52 return reg_read(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR); 53 } 54 55 static inline u32 TX_INTF_REG_CSI_FUZZER_read(void){ 56 return reg_read(TX_INTF_REG_CSI_FUZZER_ADDR); 57 } 58 59 static inline u32 TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read(void){ 60 return reg_read(TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR); 61 } 62 63 static inline u32 TX_INTF_REG_ARBITRARY_IQ_CTL_read(void){ 64 return reg_read(TX_INTF_REG_ARBITRARY_IQ_CTL_ADDR); 65 } 66 67 static inline u32 TX_INTF_REG_TX_CONFIG_read(void){ 68 return reg_read(TX_INTF_REG_TX_CONFIG_ADDR); 69 } 70 71 static inline u32 TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read(void){ 72 return reg_read(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR); 73 } 74 75 static inline u32 TX_INTF_REG_CFG_DATA_TO_ANT_read(void){ 76 return reg_read(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR); 77 } 78 79 static inline u32 TX_INTF_REG_S_AXIS_FIFO_TH_read(void){ 80 return reg_read(TX_INTF_REG_S_AXIS_FIFO_TH_ADDR); 81 } 82 83 static inline u32 TX_INTF_REG_TX_HOLD_THRESHOLD_read(void){ 84 return reg_read(TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR); 85 } 86 87 static inline u32 TX_INTF_REG_INTERRUPT_SEL_read(void){ 88 return reg_read(TX_INTF_REG_INTERRUPT_SEL_ADDR); 89 } 90 91 static inline u32 TX_INTF_REG_AMPDU_ACTION_CONFIG_read(void){ 92 return reg_read(TX_INTF_REG_AMPDU_ACTION_CONFIG_ADDR); 93 } 94 95 static inline u32 TX_INTF_REG_BB_GAIN_read(void){ 96 return reg_read(TX_INTF_REG_BB_GAIN_ADDR); 97 } 98 99 static inline u32 TX_INTF_REG_ANT_SEL_read(void){ 100 return reg_read(TX_INTF_REG_ANT_SEL_ADDR); 101 } 102 103 static inline u32 TX_INTF_REG_PHY_HDR_CONFIG_read(void){ 104 return reg_read(TX_INTF_REG_PHY_HDR_CONFIG_ADDR); 105 } 106 107 static inline u32 TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read(void){ 108 return reg_read(TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR); 109 } 110 111 static inline u32 TX_INTF_REG_PKT_INFO1_read(void){ 112 return reg_read(TX_INTF_REG_PKT_INFO1_ADDR); 113 } 114 115 static inline u32 TX_INTF_REG_PKT_INFO2_read(void){ 116 return reg_read(TX_INTF_REG_PKT_INFO2_ADDR); 117 } 118 119 static inline u32 TX_INTF_REG_PKT_INFO3_read(void){ 120 return reg_read(TX_INTF_REG_PKT_INFO3_ADDR); 121 } 122 123 static inline u32 TX_INTF_REG_PKT_INFO4_read(void){ 124 return reg_read(TX_INTF_REG_PKT_INFO4_ADDR); 125 } 126 127 static inline u32 TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read(void){ 128 return reg_read(TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_ADDR); 129 } 130 131 //-------------------------------------------------------- 132 133 static inline void TX_INTF_REG_MULTI_RST_write(u32 value){ 134 reg_write(TX_INTF_REG_MULTI_RST_ADDR, value); 135 } 136 137 static inline void TX_INTF_REG_ARBITRARY_IQ_write(u32 value){ 138 reg_write(TX_INTF_REG_ARBITRARY_IQ_ADDR, value); 139 } 140 141 static inline void TX_INTF_REG_WIFI_TX_MODE_write(u32 value){ 142 reg_write(TX_INTF_REG_WIFI_TX_MODE_ADDR, value); 143 } 144 145 static inline void TX_INTF_REG_CTS_TOSELF_CONFIG_write(u32 value){ 146 reg_write(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR, value); 147 } 148 149 static inline void TX_INTF_REG_CSI_FUZZER_write(u32 value){ 150 reg_write(TX_INTF_REG_CSI_FUZZER_ADDR, value); 151 } 152 153 static inline void TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write(u32 value){ 154 reg_write(TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR, value); 155 } 156 157 static inline void TX_INTF_REG_ARBITRARY_IQ_CTL_write(u32 value){ 158 reg_write(TX_INTF_REG_ARBITRARY_IQ_CTL_ADDR, value); 159 } 160 161 static inline void TX_INTF_REG_TX_CONFIG_write(u32 value){ 162 reg_write(TX_INTF_REG_TX_CONFIG_ADDR, value); 163 } 164 165 static inline void TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(u32 value){ 166 reg_write(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR, value); 167 } 168 169 static inline void TX_INTF_REG_CFG_DATA_TO_ANT_write(u32 value){ 170 reg_write(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR, value); 171 } 172 173 static inline void TX_INTF_REG_S_AXIS_FIFO_TH_write(u32 value){ 174 reg_write(TX_INTF_REG_S_AXIS_FIFO_TH_ADDR, value); 175 } 176 177 static inline void TX_INTF_REG_TX_HOLD_THRESHOLD_write(u32 value){ 178 reg_write(TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR, value); 179 } 180 181 static inline void TX_INTF_REG_INTERRUPT_SEL_write(u32 value){ 182 reg_write(TX_INTF_REG_INTERRUPT_SEL_ADDR, value); 183 } 184 185 static inline void TX_INTF_REG_AMPDU_ACTION_CONFIG_write(u32 value){ 186 reg_write(TX_INTF_REG_AMPDU_ACTION_CONFIG_ADDR, value); 187 } 188 189 static inline void TX_INTF_REG_BB_GAIN_write(u32 value){ 190 reg_write(TX_INTF_REG_BB_GAIN_ADDR, value); 191 } 192 193 static inline void TX_INTF_REG_ANT_SEL_write(u32 value){ 194 reg_write(TX_INTF_REG_ANT_SEL_ADDR, value); 195 } 196 197 static inline void TX_INTF_REG_PHY_HDR_CONFIG_write(u32 value){ 198 reg_write(TX_INTF_REG_PHY_HDR_CONFIG_ADDR, value); 199 } 200 201 static inline void TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write(u32 value){ 202 reg_write(TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR, value); 203 } 204 205 static inline void TX_INTF_REG_PKT_INFO1_write(u32 value){ 206 reg_write(TX_INTF_REG_PKT_INFO1_ADDR,value); 207 } 208 209 static inline void TX_INTF_REG_PKT_INFO2_write(u32 value){ 210 reg_write(TX_INTF_REG_PKT_INFO2_ADDR,value); 211 } 212 213 static inline void TX_INTF_REG_PKT_INFO3_write(u32 value){ 214 reg_write(TX_INTF_REG_PKT_INFO3_ADDR,value); 215 } 216 217 static inline void TX_INTF_REG_PKT_INFO4_write(u32 value){ 218 reg_write(TX_INTF_REG_PKT_INFO4_ADDR,value); 219 } 220 221 static const struct of_device_id dev_of_ids[] = { 222 { .compatible = "sdr,tx_intf", }, 223 {} 224 }; 225 MODULE_DEVICE_TABLE(of, dev_of_ids); 226 227 static struct tx_intf_driver_api tx_intf_driver_api_inst; 228 static struct tx_intf_driver_api *tx_intf_api = &tx_intf_driver_api_inst; 229 EXPORT_SYMBOL(tx_intf_api); 230 231 static inline u32 hw_init(enum tx_intf_mode mode, u32 tx_config, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type){ 232 int err=0, i; 233 u32 mixer_cfg=0, ant_sel=0; 234 235 printk("%s hw_init mode %d\n", tx_intf_compatible_str, mode); 236 237 //rst 238 for (i=0;i<8;i++) 239 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 240 for (i=0;i<32;i++) 241 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0xFFFFFFFF); 242 for (i=0;i<8;i++) 243 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 244 245 if(fpga_type == LARGE_FPGA) // LARGE FPGA: MAX_NUM_DMA_SYMBOL = 8192 246 // tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(8192-(210*5)); // threshold is for room to hold the last 4 packets from 4 queue before stop 247 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(8192-(210*2)); 248 else if(fpga_type == SMALL_FPGA) // SMALL FPGA: MAX_NUM_DMA_SYMBOL = 4096 249 // tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(4096-(210*5)); // threshold is for room to hold the last 4 packets from 4 queue before stop 250 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(4096-(210*2)); 251 252 switch(mode) 253 { 254 case TX_INTF_AXIS_LOOP_BACK: 255 printk("%s hw_init mode TX_INTF_AXIS_LOOP_BACK\n", tx_intf_compatible_str); 256 break; 257 258 case TX_INTF_BW_20MHZ_AT_0MHZ_ANT0: 259 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT0\n", tx_intf_compatible_str); 260 mixer_cfg = 0x2001F400; 261 ant_sel=1; 262 break; 263 264 case TX_INTF_BW_20MHZ_AT_0MHZ_ANT_BOTH: 265 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT0\n", tx_intf_compatible_str); 266 mixer_cfg = 0x2001F400; 267 ant_sel=0x11; 268 break; 269 270 case TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0: 271 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0\n", tx_intf_compatible_str); 272 mixer_cfg = 0x2001F602; 273 ant_sel=1; 274 break; 275 276 case TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0: 277 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0\n", tx_intf_compatible_str); 278 mixer_cfg = 0x200202F6; 279 ant_sel=1; 280 break; 281 282 case TX_INTF_BW_20MHZ_AT_0MHZ_ANT1: 283 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT1\n", tx_intf_compatible_str); 284 mixer_cfg = 0x2001F400; 285 ant_sel=2; 286 break; 287 288 case TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1: 289 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1\n", tx_intf_compatible_str); 290 mixer_cfg = 0x2001F602; 291 ant_sel=2; 292 break; 293 294 case TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1: 295 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1\n", tx_intf_compatible_str); 296 mixer_cfg = 0x200202F6; 297 ant_sel=2; 298 break; 299 300 case TX_INTF_BYPASS: 301 printk("%s hw_init mode TX_INTF_BYPASS\n", tx_intf_compatible_str); 302 mixer_cfg = 0x200202F6; 303 ant_sel=2; 304 break; 305 306 default: 307 printk("%s hw_init mode %d is wrong!\n", tx_intf_compatible_str, mode); 308 err=1; 309 } 310 311 if (mode!=TX_INTF_AXIS_LOOP_BACK) { 312 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 313 tx_intf_api->TX_INTF_REG_CSI_FUZZER_write(0); 314 tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*10)<<16)|(16*10) );//high 16bit 5GHz; low 16 bit 2.4GHz. counter speed 10MHz is assumed 315 316 tx_intf_api->TX_INTF_REG_TX_CONFIG_write(tx_config); 317 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps); 318 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0); 319 tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_write(420); 320 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x4); //.src_sel(slv_reg14[2:0]), 0-s00_axis_tlast,1-ap_start,2-tx_start_from_acc,3-tx_end_from_acc,4-tx_try_complete from xpu 321 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x30004); //disable interrupt 322 323 // tx_intf_api->TX_INTF_REG_BB_GAIN_write(100); // value for old design with DUC (FIR + MIXER) -- obsolete due to DUC removal 324 // New test on new design (unified RF BB clock; No DUC) 325 // 5220MHz bb_gain power EVM 326 // 400 -6dBm -34/35 327 // 350 -7.2dBm -34/35/36 328 // 300 -8.5dBm -35/36/37 EVM 329 330 // 2437MHz bb_gain power EVM 331 // 400 -3.2dBm -36/37 332 // 350 -4.4dBm -37/38/39 333 // 300 -5.7dBm -39/40 334 // less less -40/41/42! 335 336 // According to above and more detailed test: 337 // Need to be 290. Otherwise some ofdm symbol's EVM jump high, when there are lots of ofdm symbols in one WiFi packet 338 339 // 2022-03-04 detailed test result: 340 // bb_gain 290 work for 11a/g all mcs 341 // bb_gain 290 work for 11n mcs 1~7 (aggr and non aggr) 342 // bb_gain 290 destroy 11n mcs 0 long (MTU 1500) tx pkt due to high PAPR (Peak to Average Power Ratio)! 343 // bb_gain 250 work for 11n mcs 0 344 // So, a conservative bb_gain 250 should be used 345 tx_intf_api->TX_INTF_REG_BB_GAIN_write(250); 346 347 tx_intf_api->TX_INTF_REG_ANT_SEL_write(ant_sel); 348 tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write((1<<3)|(2<<4)); 349 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0x434); 350 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 351 } 352 353 // if (mode == TX_INTF_BYPASS) { 354 // tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0x100); //slv_reg10[8] -- bit 8 not used anymore. only bit0/1 are still reserved. 355 // } 356 357 printk("%s hw_init err %d\n", tx_intf_compatible_str, err); 358 return(err); 359 } 360 361 static int dev_probe(struct platform_device *pdev) 362 { 363 struct device_node *np = pdev->dev.of_node; 364 struct resource *io; 365 int err=1; 366 367 printk("\n"); 368 369 if (np) { 370 const struct of_device_id *match; 371 372 match = of_match_node(dev_of_ids, np); 373 if (match) { 374 printk("%s dev_probe match!\n", tx_intf_compatible_str); 375 err = 0; 376 } 377 } 378 379 if (err) 380 return err; 381 382 tx_intf_api->hw_init=hw_init; 383 384 tx_intf_api->reg_read=reg_read; 385 tx_intf_api->reg_write=reg_write; 386 387 tx_intf_api->TX_INTF_REG_MULTI_RST_read=TX_INTF_REG_MULTI_RST_read; 388 tx_intf_api->TX_INTF_REG_ARBITRARY_IQ_read=TX_INTF_REG_ARBITRARY_IQ_read; 389 tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_read=TX_INTF_REG_WIFI_TX_MODE_read; 390 tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_read=TX_INTF_REG_CTS_TOSELF_CONFIG_read; 391 tx_intf_api->TX_INTF_REG_CSI_FUZZER_read=TX_INTF_REG_CSI_FUZZER_read; 392 tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read; 393 tx_intf_api->TX_INTF_REG_ARBITRARY_IQ_CTL_read=TX_INTF_REG_ARBITRARY_IQ_CTL_read; 394 tx_intf_api->TX_INTF_REG_TX_CONFIG_read=TX_INTF_REG_TX_CONFIG_read; 395 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read; 396 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_read=TX_INTF_REG_CFG_DATA_TO_ANT_read; 397 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_read=TX_INTF_REG_S_AXIS_FIFO_TH_read; 398 tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_read=TX_INTF_REG_TX_HOLD_THRESHOLD_read; 399 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_read=TX_INTF_REG_INTERRUPT_SEL_read; 400 tx_intf_api->TX_INTF_REG_AMPDU_ACTION_CONFIG_read=TX_INTF_REG_AMPDU_ACTION_CONFIG_read; 401 tx_intf_api->TX_INTF_REG_BB_GAIN_read=TX_INTF_REG_BB_GAIN_read; 402 tx_intf_api->TX_INTF_REG_ANT_SEL_read=TX_INTF_REG_ANT_SEL_read; 403 tx_intf_api->TX_INTF_REG_PHY_HDR_CONFIG_read=TX_INTF_REG_PHY_HDR_CONFIG_read; 404 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read=TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read; 405 tx_intf_api->TX_INTF_REG_PKT_INFO1_read=TX_INTF_REG_PKT_INFO1_read; 406 tx_intf_api->TX_INTF_REG_PKT_INFO2_read=TX_INTF_REG_PKT_INFO2_read; 407 tx_intf_api->TX_INTF_REG_PKT_INFO3_read=TX_INTF_REG_PKT_INFO3_read; 408 tx_intf_api->TX_INTF_REG_PKT_INFO4_read=TX_INTF_REG_PKT_INFO4_read; 409 tx_intf_api->TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read=TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read; 410 411 tx_intf_api->TX_INTF_REG_MULTI_RST_write=TX_INTF_REG_MULTI_RST_write; 412 tx_intf_api->TX_INTF_REG_ARBITRARY_IQ_write=TX_INTF_REG_ARBITRARY_IQ_write; 413 tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write=TX_INTF_REG_WIFI_TX_MODE_write; 414 tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_write=TX_INTF_REG_CTS_TOSELF_CONFIG_write; 415 tx_intf_api->TX_INTF_REG_CSI_FUZZER_write=TX_INTF_REG_CSI_FUZZER_write; 416 tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write; 417 tx_intf_api->TX_INTF_REG_ARBITRARY_IQ_CTL_write=TX_INTF_REG_ARBITRARY_IQ_CTL_write; 418 tx_intf_api->TX_INTF_REG_TX_CONFIG_write=TX_INTF_REG_TX_CONFIG_write; 419 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write; 420 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write=TX_INTF_REG_CFG_DATA_TO_ANT_write; 421 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write=TX_INTF_REG_S_AXIS_FIFO_TH_write; 422 tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_write=TX_INTF_REG_TX_HOLD_THRESHOLD_write; 423 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write=TX_INTF_REG_INTERRUPT_SEL_write; 424 tx_intf_api->TX_INTF_REG_AMPDU_ACTION_CONFIG_write=TX_INTF_REG_AMPDU_ACTION_CONFIG_write; 425 tx_intf_api->TX_INTF_REG_BB_GAIN_write=TX_INTF_REG_BB_GAIN_write; 426 tx_intf_api->TX_INTF_REG_ANT_SEL_write=TX_INTF_REG_ANT_SEL_write; 427 tx_intf_api->TX_INTF_REG_PHY_HDR_CONFIG_write=TX_INTF_REG_PHY_HDR_CONFIG_write; 428 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write=TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write; 429 tx_intf_api->TX_INTF_REG_PKT_INFO1_write=TX_INTF_REG_PKT_INFO1_write; 430 tx_intf_api->TX_INTF_REG_PKT_INFO2_write=TX_INTF_REG_PKT_INFO2_write; 431 tx_intf_api->TX_INTF_REG_PKT_INFO3_write=TX_INTF_REG_PKT_INFO3_write; 432 tx_intf_api->TX_INTF_REG_PKT_INFO4_write=TX_INTF_REG_PKT_INFO4_write; 433 434 /* Request and map I/O memory */ 435 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 436 base_addr = devm_ioremap_resource(&pdev->dev, io); 437 if (IS_ERR(base_addr)) 438 return PTR_ERR(base_addr); 439 440 printk("%s dev_probe io start 0x%08llx end 0x%08llx name %s flags 0x%08x desc 0x%08x\n", tx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); 441 printk("%s dev_probe base_addr 0x%p\n", tx_intf_compatible_str,(void*)base_addr); 442 printk("%s dev_probe tx_intf_driver_api_inst 0x%p\n", tx_intf_compatible_str, (void*)(&tx_intf_driver_api_inst) ); 443 printk("%s dev_probe tx_intf_api 0x%p\n", tx_intf_compatible_str, (void*)tx_intf_api); 444 445 printk("%s dev_probe succeed!\n", tx_intf_compatible_str); 446 447 //err = hw_init(TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 8, 8, SMALL_FPGA); 448 //err = hw_init(TX_INTF_BYPASS, 8, 8, SMALL_FPGA); 449 err = hw_init(TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 8, 8, SMALL_FPGA); // make sure dac is connected to original ad9361 dma 450 451 return err; 452 } 453 454 static int dev_remove(struct platform_device *pdev) 455 { 456 printk("\n"); 457 458 printk("%s dev_remove base_addr 0x%p\n", tx_intf_compatible_str,(void*)base_addr); 459 printk("%s dev_remove tx_intf_driver_api_inst 0x%p\n", tx_intf_compatible_str, (void*)(&tx_intf_driver_api_inst) ); 460 printk("%s dev_remove tx_intf_api 0x%p\n", tx_intf_compatible_str, (void*)tx_intf_api); 461 462 printk("%s dev_remove succeed!\n", tx_intf_compatible_str); 463 return 0; 464 } 465 466 static struct platform_driver dev_driver = { 467 .driver = { 468 .name = "sdr,tx_intf", 469 .owner = THIS_MODULE, 470 .of_match_table = dev_of_ids, 471 }, 472 .probe = dev_probe, 473 .remove = dev_remove, 474 }; 475 476 module_platform_driver(dev_driver); 477 478 MODULE_AUTHOR("Xianjun Jiao"); 479 MODULE_DESCRIPTION("sdr,tx_intf"); 480 MODULE_LICENSE("GPL v2"); 481