1 /* 2 * axi lite register access driver 3 * Xianjun jiao. [email protected]; [email protected] 4 */ 5 6 #include <linux/bitops.h> 7 #include <linux/dmapool.h> 8 #include <linux/dma/xilinx_dma.h> 9 #include <linux/init.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/module.h> 14 #include <linux/of_address.h> 15 #include <linux/of_dma.h> 16 #include <linux/of_platform.h> 17 #include <linux/of_irq.h> 18 #include <linux/slab.h> 19 #include <linux/clk.h> 20 #include <linux/io-64-nonatomic-lo-hi.h> 21 22 #include "../hw_def.h" 23 24 static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design 25 26 /* IO accessors */ 27 static inline u32 reg_read(u32 reg) 28 { 29 return ioread32(base_addr + reg); 30 } 31 32 static inline void reg_write(u32 reg, u32 value) 33 { 34 iowrite32(value, base_addr + reg); 35 } 36 37 static inline u32 TX_INTF_REG_MULTI_RST_read(void){ 38 return reg_read(TX_INTF_REG_MULTI_RST_ADDR); 39 } 40 41 static inline u32 TX_INTF_REG_MIXER_CFG_read(void){ 42 return reg_read(TX_INTF_REG_MIXER_CFG_ADDR); 43 } 44 45 static inline u32 TX_INTF_REG_WIFI_TX_MODE_read(void){ 46 return reg_read(TX_INTF_REG_WIFI_TX_MODE_ADDR); 47 } 48 49 static inline u32 TX_INTF_REG_IQ_SRC_SEL_read(void){ 50 return reg_read(TX_INTF_REG_IQ_SRC_SEL_ADDR); 51 } 52 53 static inline u32 TX_INTF_REG_CTS_TOSELF_CONFIG_read(void){ 54 return reg_read(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR); 55 } 56 57 static inline u32 TX_INTF_REG_START_TRANS_TO_PS_MODE_read(void){ 58 return reg_read(TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR); 59 } 60 61 static inline u32 TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read(void){ 62 return reg_read(TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR); 63 } 64 65 static inline u32 TX_INTF_REG_MISC_SEL_read(void){ 66 return reg_read(TX_INTF_REG_MISC_SEL_ADDR); 67 } 68 69 static inline u32 TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read(void){ 70 return reg_read(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR); 71 } 72 73 static inline u32 TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read(void){ 74 return reg_read(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR); 75 } 76 77 static inline u32 TX_INTF_REG_CFG_DATA_TO_ANT_read(void){ 78 return reg_read(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR); 79 } 80 81 static inline u32 TX_INTF_REG_INTERRUPT_SEL_read(void){ 82 return reg_read(TX_INTF_REG_INTERRUPT_SEL_ADDR); 83 } 84 85 static inline u32 TX_INTF_REG_BB_GAIN_read(void){ 86 return reg_read(TX_INTF_REG_BB_GAIN_ADDR); 87 } 88 89 static inline u32 TX_INTF_REG_ANT_SEL_read(void){ 90 return reg_read(TX_INTF_REG_ANT_SEL_ADDR); 91 } 92 93 static inline u32 TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_read(void){ 94 return reg_read(TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_ADDR); 95 } 96 97 static inline u32 TX_INTF_REG_PKT_INFO_read(void){ 98 return reg_read(TX_INTF_REG_PKT_INFO_ADDR); 99 } 100 101 static inline u32 TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read(void){ 102 return reg_read(TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_ADDR); 103 } 104 105 //-------------------------------------------------------- 106 107 static inline void TX_INTF_REG_MULTI_RST_write(u32 value){ 108 reg_write(TX_INTF_REG_MULTI_RST_ADDR, value); 109 } 110 111 static inline void TX_INTF_REG_MIXER_CFG_write(u32 value){ 112 reg_write(TX_INTF_REG_MIXER_CFG_ADDR, value); 113 } 114 115 static inline void TX_INTF_REG_WIFI_TX_MODE_write(u32 value){ 116 reg_write(TX_INTF_REG_WIFI_TX_MODE_ADDR, value); 117 } 118 119 static inline void TX_INTF_REG_IQ_SRC_SEL_write(u32 value){ 120 reg_write(TX_INTF_REG_IQ_SRC_SEL_ADDR, value); 121 } 122 123 static inline void TX_INTF_REG_CTS_TOSELF_CONFIG_write(u32 value){ 124 reg_write(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR, value); 125 } 126 127 static inline void TX_INTF_REG_START_TRANS_TO_PS_MODE_write(u32 value){ 128 reg_write(TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR, value); 129 } 130 131 static inline void TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write(u32 value){ 132 reg_write(TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR, value); 133 } 134 135 static inline void TX_INTF_REG_MISC_SEL_write(u32 value){ 136 reg_write(TX_INTF_REG_MISC_SEL_ADDR, value); 137 } 138 139 static inline void TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(u32 value){ 140 reg_write(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR, value); 141 } 142 143 static inline void TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(u32 value){ 144 reg_write(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR, value); 145 } 146 147 static inline void TX_INTF_REG_CFG_DATA_TO_ANT_write(u32 value){ 148 reg_write(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR, value); 149 } 150 151 static inline void TX_INTF_REG_INTERRUPT_SEL_write(u32 value){ 152 reg_write(TX_INTF_REG_INTERRUPT_SEL_ADDR, value); 153 } 154 155 static inline void TX_INTF_REG_BB_GAIN_write(u32 value){ 156 reg_write(TX_INTF_REG_BB_GAIN_ADDR, value); 157 } 158 159 static inline void TX_INTF_REG_ANT_SEL_write(u32 value){ 160 reg_write(TX_INTF_REG_ANT_SEL_ADDR, value); 161 } 162 163 static inline void TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_write(u32 value){ 164 reg_write(TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_ADDR, value); 165 } 166 167 static inline void TX_INTF_REG_PKT_INFO_write(u32 value){ 168 reg_write(TX_INTF_REG_PKT_INFO_ADDR,value); 169 } 170 171 static const struct of_device_id dev_of_ids[] = { 172 { .compatible = "sdr,tx_intf", }, 173 {} 174 }; 175 MODULE_DEVICE_TABLE(of, dev_of_ids); 176 177 static struct tx_intf_driver_api tx_intf_driver_api_inst; 178 static struct tx_intf_driver_api *tx_intf_api = &tx_intf_driver_api_inst; 179 EXPORT_SYMBOL(tx_intf_api); 180 181 static inline u32 hw_init(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps){ 182 int err=0; 183 u32 reg_val, mixer_cfg=0, duc_input_ch_sel = 0, ant_sel=0; 184 185 printk("%s hw_init mode %d\n", tx_intf_compatible_str, mode); 186 187 //rst duc internal module 188 for (reg_val=0;reg_val<32;reg_val++) 189 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0xFFFFFFFF); 190 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 191 192 switch(mode) 193 { 194 case TX_INTF_AXIS_LOOP_BACK: 195 tx_intf_api->TX_INTF_REG_MISC_SEL_write(0<<1);// bit1: 0-connect dac to ADI dma; 1-connect dac to our intf 196 printk("%s hw_init mode TX_INTF_AXIS_LOOP_BACK\n", tx_intf_compatible_str); 197 break; 198 199 case TX_INTF_BW_20MHZ_AT_0MHZ_ANT0: 200 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT0\n", tx_intf_compatible_str); 201 mixer_cfg = 0x2001F400; 202 duc_input_ch_sel = 0; 203 ant_sel=1; 204 break; 205 206 case TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0: 207 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0\n", tx_intf_compatible_str); 208 mixer_cfg = 0x2001F602; 209 duc_input_ch_sel = 0; 210 ant_sel=1; 211 break; 212 213 case TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0: 214 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0\n", tx_intf_compatible_str); 215 mixer_cfg = 0x200202F6; 216 duc_input_ch_sel = 0; 217 ant_sel=1; 218 break; 219 220 case TX_INTF_BW_20MHZ_AT_0MHZ_ANT1: 221 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT1\n", tx_intf_compatible_str); 222 mixer_cfg = 0x2001F400; 223 duc_input_ch_sel = 0; 224 ant_sel=2; 225 break; 226 227 case TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1: 228 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1\n", tx_intf_compatible_str); 229 mixer_cfg = 0x2001F602; 230 duc_input_ch_sel = 0; 231 ant_sel=2; 232 break; 233 234 case TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1: 235 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1\n", tx_intf_compatible_str); 236 mixer_cfg = 0x200202F6; 237 duc_input_ch_sel = 0; 238 ant_sel=2; 239 break; 240 241 case TX_INTF_BYPASS: 242 printk("%s hw_init mode TX_INTF_BYPASS\n", tx_intf_compatible_str); 243 mixer_cfg = 0x200202F6; 244 duc_input_ch_sel = 0; 245 ant_sel=2; 246 break; 247 248 default: 249 printk("%s hw_init mode %d is wrong!\n", tx_intf_compatible_str, mode); 250 err=1; 251 } 252 253 if (mode!=TX_INTF_AXIS_LOOP_BACK) { 254 tx_intf_api->TX_INTF_REG_MISC_SEL_write(1<<1);// bit1: 0-connect dac to ADI dma; 1-connect dac to our intf 255 256 tx_intf_api->TX_INTF_REG_MIXER_CFG_write(mixer_cfg); 257 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 258 tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_write(duc_input_ch_sel); 259 tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_write(2); 260 tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*200)<<16)|(10*200) );//high 16bit 5GHz; low 16 bit 2.4GHz 261 262 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(num_dma_symbol_to_pl); 263 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps); 264 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0); 265 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x40); //.src_sel0(slv_reg14[2:0]), .src_sel1(slv_reg14[6:4]), 0-s00_axis_tlast,1-ap_start,2-tx_start_from_acc,3-tx_end_from_acc,4-xpu signal 266 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x30040); //disable interrupt 267 tx_intf_api->TX_INTF_REG_BB_GAIN_write(100); 268 tx_intf_api->TX_INTF_REG_ANT_SEL_write(ant_sel); 269 tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write((1<<3)|(2<<4)); 270 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0x434); 271 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 272 } 273 274 if (mode == TX_INTF_BYPASS) { 275 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0x100); //slv_reg10[8] 276 } 277 278 printk("%s hw_init err %d\n", tx_intf_compatible_str, err); 279 return(err); 280 } 281 282 static int dev_probe(struct platform_device *pdev) 283 { 284 struct device_node *np = pdev->dev.of_node; 285 struct resource *io; 286 int err=1; 287 288 printk("\n"); 289 290 if (np) { 291 const struct of_device_id *match; 292 293 match = of_match_node(dev_of_ids, np); 294 if (match) { 295 printk("%s dev_probe match!\n", tx_intf_compatible_str); 296 err = 0; 297 } 298 } 299 300 if (err) 301 return err; 302 303 tx_intf_api->hw_init=hw_init; 304 305 tx_intf_api->reg_read=reg_read; 306 tx_intf_api->reg_write=reg_write; 307 308 tx_intf_api->TX_INTF_REG_MULTI_RST_read=TX_INTF_REG_MULTI_RST_read; 309 tx_intf_api->TX_INTF_REG_MIXER_CFG_read=TX_INTF_REG_MIXER_CFG_read; 310 tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_read=TX_INTF_REG_WIFI_TX_MODE_read; 311 tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_read=TX_INTF_REG_IQ_SRC_SEL_read; 312 tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_read=TX_INTF_REG_CTS_TOSELF_CONFIG_read; 313 tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_read=TX_INTF_REG_START_TRANS_TO_PS_MODE_read; 314 tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read; 315 tx_intf_api->TX_INTF_REG_MISC_SEL_read=TX_INTF_REG_MISC_SEL_read; 316 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read; 317 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read; 318 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_read=TX_INTF_REG_CFG_DATA_TO_ANT_read; 319 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_read=TX_INTF_REG_INTERRUPT_SEL_read; 320 tx_intf_api->TX_INTF_REG_BB_GAIN_read=TX_INTF_REG_BB_GAIN_read; 321 tx_intf_api->TX_INTF_REG_ANT_SEL_read=TX_INTF_REG_ANT_SEL_read; 322 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_read=TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_read; 323 tx_intf_api->TX_INTF_REG_PKT_INFO_read=TX_INTF_REG_PKT_INFO_read; 324 tx_intf_api->TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read=TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read; 325 326 tx_intf_api->TX_INTF_REG_MULTI_RST_write=TX_INTF_REG_MULTI_RST_write; 327 tx_intf_api->TX_INTF_REG_MIXER_CFG_write=TX_INTF_REG_MIXER_CFG_write; 328 tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write=TX_INTF_REG_WIFI_TX_MODE_write; 329 tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_write=TX_INTF_REG_IQ_SRC_SEL_write; 330 tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_write=TX_INTF_REG_CTS_TOSELF_CONFIG_write; 331 tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_write=TX_INTF_REG_START_TRANS_TO_PS_MODE_write; 332 tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write; 333 tx_intf_api->TX_INTF_REG_MISC_SEL_write=TX_INTF_REG_MISC_SEL_write; 334 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write; 335 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write; 336 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write=TX_INTF_REG_CFG_DATA_TO_ANT_write; 337 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write=TX_INTF_REG_INTERRUPT_SEL_write; 338 tx_intf_api->TX_INTF_REG_BB_GAIN_write=TX_INTF_REG_BB_GAIN_write; 339 tx_intf_api->TX_INTF_REG_ANT_SEL_write=TX_INTF_REG_ANT_SEL_write; 340 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_write=TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_write; 341 tx_intf_api->TX_INTF_REG_PKT_INFO_write=TX_INTF_REG_PKT_INFO_write; 342 343 /* Request and map I/O memory */ 344 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 345 base_addr = devm_ioremap_resource(&pdev->dev, io); 346 if (IS_ERR(base_addr)) 347 return PTR_ERR(base_addr); 348 349 printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", tx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); 350 printk("%s dev_probe base_addr 0x%08x\n", tx_intf_compatible_str,(u32)base_addr); 351 printk("%s dev_probe tx_intf_driver_api_inst 0x%08x\n", tx_intf_compatible_str, (u32)(&tx_intf_driver_api_inst) ); 352 printk("%s dev_probe tx_intf_api 0x%08x\n", tx_intf_compatible_str, (u32)tx_intf_api); 353 354 printk("%s dev_probe succeed!\n", tx_intf_compatible_str); 355 356 //err = hw_init(TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 8, 8); 357 //err = hw_init(TX_INTF_BYPASS, 8, 8); 358 err = hw_init(TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 8, 8); // make sure dac is connected to original ad9361 dma 359 360 return err; 361 } 362 363 static int dev_remove(struct platform_device *pdev) 364 { 365 printk("\n"); 366 367 printk("%s dev_remove base_addr 0x%08x\n", tx_intf_compatible_str,(u32)base_addr); 368 printk("%s dev_remove tx_intf_driver_api_inst 0x%08x\n", tx_intf_compatible_str, (u32)(&tx_intf_driver_api_inst) ); 369 printk("%s dev_remove tx_intf_api 0x%08x\n", tx_intf_compatible_str, (u32)tx_intf_api); 370 371 printk("%s dev_remove succeed!\n", tx_intf_compatible_str); 372 return 0; 373 } 374 375 static struct platform_driver dev_driver = { 376 .driver = { 377 .name = "sdr,tx_intf", 378 .owner = THIS_MODULE, 379 .of_match_table = dev_of_ids, 380 }, 381 .probe = dev_probe, 382 .remove = dev_remove, 383 }; 384 385 module_platform_driver(dev_driver); 386 387 MODULE_AUTHOR("Xianjun Jiao"); 388 MODULE_DESCRIPTION("sdr,tx_intf"); 389 MODULE_LICENSE("GPL v2"); 390