1 /* 2 * axi lite register access driver 3 * SPDX-FileCopyrightText: 2019 Jiao Xianjun <[email protected]> 4 * SPDX-License-Identifier: AGPL-3.0-or-later 5 */ 6 7 #include <linux/bitops.h> 8 #include <linux/dmapool.h> 9 #include <linux/dma/xilinx_dma.h> 10 #include <linux/init.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/module.h> 15 #include <linux/of_address.h> 16 #include <linux/of_dma.h> 17 #include <linux/of_platform.h> 18 #include <linux/of_irq.h> 19 #include <linux/slab.h> 20 #include <linux/clk.h> 21 #include <linux/io-64-nonatomic-lo-hi.h> 22 23 #include "../hw_def.h" 24 25 static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design 26 27 /* IO accessors */ 28 static inline u32 reg_read(u32 reg) 29 { 30 return ioread32(base_addr + reg); 31 } 32 33 static inline void reg_write(u32 reg, u32 value) 34 { 35 iowrite32(value, base_addr + reg); 36 } 37 38 static inline u32 TX_INTF_REG_MULTI_RST_read(void){ 39 return reg_read(TX_INTF_REG_MULTI_RST_ADDR); 40 } 41 42 static inline u32 TX_INTF_REG_MIXER_CFG_read(void){ 43 return reg_read(TX_INTF_REG_MIXER_CFG_ADDR); 44 } 45 46 static inline u32 TX_INTF_REG_WIFI_TX_MODE_read(void){ 47 return reg_read(TX_INTF_REG_WIFI_TX_MODE_ADDR); 48 } 49 50 static inline u32 TX_INTF_REG_IQ_SRC_SEL_read(void){ 51 return reg_read(TX_INTF_REG_IQ_SRC_SEL_ADDR); 52 } 53 54 static inline u32 TX_INTF_REG_CTS_TOSELF_CONFIG_read(void){ 55 return reg_read(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR); 56 } 57 58 static inline u32 TX_INTF_REG_START_TRANS_TO_PS_MODE_read(void){ 59 return reg_read(TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR); 60 } 61 62 static inline u32 TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read(void){ 63 return reg_read(TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR); 64 } 65 66 static inline u32 TX_INTF_REG_MISC_SEL_read(void){ 67 return reg_read(TX_INTF_REG_MISC_SEL_ADDR); 68 } 69 70 static inline u32 TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read(void){ 71 return reg_read(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR); 72 } 73 74 static inline u32 TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read(void){ 75 return reg_read(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR); 76 } 77 78 static inline u32 TX_INTF_REG_CFG_DATA_TO_ANT_read(void){ 79 return reg_read(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR); 80 } 81 82 static inline u32 TX_INTF_REG_S_AXIS_FIFO_TH_read(void){ 83 return reg_read(TX_INTF_REG_S_AXIS_FIFO_TH_ADDR); 84 } 85 86 static inline u32 TX_INTF_REG_TX_HOLD_THRESHOLD_read(void){ 87 return reg_read(TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR); 88 } 89 90 static inline u32 TX_INTF_REG_INTERRUPT_SEL_read(void){ 91 return reg_read(TX_INTF_REG_INTERRUPT_SEL_ADDR); 92 } 93 94 static inline u32 TX_INTF_REG_BB_GAIN_read(void){ 95 return reg_read(TX_INTF_REG_BB_GAIN_ADDR); 96 } 97 98 static inline u32 TX_INTF_REG_ANT_SEL_read(void){ 99 return reg_read(TX_INTF_REG_ANT_SEL_ADDR); 100 } 101 102 static inline u32 TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read(void){ 103 return reg_read(TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR); 104 } 105 106 static inline u32 TX_INTF_REG_PKT_INFO_read(void){ 107 return reg_read(TX_INTF_REG_PKT_INFO_ADDR); 108 } 109 110 static inline u32 TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read(void){ 111 return reg_read(TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_ADDR); 112 } 113 114 //-------------------------------------------------------- 115 116 static inline void TX_INTF_REG_MULTI_RST_write(u32 value){ 117 reg_write(TX_INTF_REG_MULTI_RST_ADDR, value); 118 } 119 120 static inline void TX_INTF_REG_MIXER_CFG_write(u32 value){ 121 reg_write(TX_INTF_REG_MIXER_CFG_ADDR, value); 122 } 123 124 static inline void TX_INTF_REG_WIFI_TX_MODE_write(u32 value){ 125 reg_write(TX_INTF_REG_WIFI_TX_MODE_ADDR, value); 126 } 127 128 static inline void TX_INTF_REG_IQ_SRC_SEL_write(u32 value){ 129 reg_write(TX_INTF_REG_IQ_SRC_SEL_ADDR, value); 130 } 131 132 static inline void TX_INTF_REG_CTS_TOSELF_CONFIG_write(u32 value){ 133 reg_write(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR, value); 134 } 135 136 static inline void TX_INTF_REG_START_TRANS_TO_PS_MODE_write(u32 value){ 137 reg_write(TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR, value); 138 } 139 140 static inline void TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write(u32 value){ 141 reg_write(TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR, value); 142 } 143 144 static inline void TX_INTF_REG_MISC_SEL_write(u32 value){ 145 reg_write(TX_INTF_REG_MISC_SEL_ADDR, value); 146 } 147 148 static inline void TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(u32 value){ 149 reg_write(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR, value); 150 } 151 152 static inline void TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(u32 value){ 153 reg_write(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR, value); 154 } 155 156 static inline void TX_INTF_REG_CFG_DATA_TO_ANT_write(u32 value){ 157 reg_write(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR, value); 158 } 159 160 static inline void TX_INTF_REG_S_AXIS_FIFO_TH_write(u32 value){ 161 reg_write(TX_INTF_REG_S_AXIS_FIFO_TH_ADDR, value); 162 } 163 164 static inline void TX_INTF_REG_TX_HOLD_THRESHOLD_write(u32 value){ 165 reg_write(TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR, value); 166 } 167 168 static inline void TX_INTF_REG_INTERRUPT_SEL_write(u32 value){ 169 reg_write(TX_INTF_REG_INTERRUPT_SEL_ADDR, value); 170 } 171 172 static inline void TX_INTF_REG_BB_GAIN_write(u32 value){ 173 reg_write(TX_INTF_REG_BB_GAIN_ADDR, value); 174 } 175 176 static inline void TX_INTF_REG_ANT_SEL_write(u32 value){ 177 reg_write(TX_INTF_REG_ANT_SEL_ADDR, value); 178 } 179 180 static inline void TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write(u32 value){ 181 reg_write(TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR, value); 182 } 183 184 static inline void TX_INTF_REG_PKT_INFO_write(u32 value){ 185 reg_write(TX_INTF_REG_PKT_INFO_ADDR,value); 186 } 187 188 static const struct of_device_id dev_of_ids[] = { 189 { .compatible = "sdr,tx_intf", }, 190 {} 191 }; 192 MODULE_DEVICE_TABLE(of, dev_of_ids); 193 194 static struct tx_intf_driver_api tx_intf_driver_api_inst; 195 static struct tx_intf_driver_api *tx_intf_api = &tx_intf_driver_api_inst; 196 EXPORT_SYMBOL(tx_intf_api); 197 198 static inline u32 hw_init(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps){ 199 int err=0, i; 200 u32 mixer_cfg=0, duc_input_ch_sel = 0, ant_sel=0; 201 202 printk("%s hw_init mode %d\n", tx_intf_compatible_str, mode); 203 204 //rst 205 for (i=0;i<8;i++) 206 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 207 for (i=0;i<32;i++) 208 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0xFFFFFFFF); 209 for (i=0;i<8;i++) 210 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 211 212 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(4096-200); // when only 200 DMA symbol room left in fifo, stop Linux queue 213 switch(mode) 214 { 215 case TX_INTF_AXIS_LOOP_BACK: 216 tx_intf_api->TX_INTF_REG_MISC_SEL_write(0<<1);// bit1: 0-connect dac to ADI dma; 1-connect dac to our intf 217 printk("%s hw_init mode TX_INTF_AXIS_LOOP_BACK\n", tx_intf_compatible_str); 218 break; 219 220 case TX_INTF_BW_20MHZ_AT_0MHZ_ANT0: 221 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT0\n", tx_intf_compatible_str); 222 mixer_cfg = 0x2001F400; 223 duc_input_ch_sel = 0; 224 ant_sel=1; 225 break; 226 227 case TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0: 228 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0\n", tx_intf_compatible_str); 229 mixer_cfg = 0x2001F602; 230 duc_input_ch_sel = 0; 231 ant_sel=1; 232 break; 233 234 case TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0: 235 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0\n", tx_intf_compatible_str); 236 mixer_cfg = 0x200202F6; 237 duc_input_ch_sel = 0; 238 ant_sel=1; 239 break; 240 241 case TX_INTF_BW_20MHZ_AT_0MHZ_ANT1: 242 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT1\n", tx_intf_compatible_str); 243 mixer_cfg = 0x2001F400; 244 duc_input_ch_sel = 0; 245 ant_sel=2; 246 break; 247 248 case TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1: 249 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1\n", tx_intf_compatible_str); 250 mixer_cfg = 0x2001F602; 251 duc_input_ch_sel = 0; 252 ant_sel=2; 253 break; 254 255 case TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1: 256 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1\n", tx_intf_compatible_str); 257 mixer_cfg = 0x200202F6; 258 duc_input_ch_sel = 0; 259 ant_sel=2; 260 break; 261 262 case TX_INTF_BYPASS: 263 printk("%s hw_init mode TX_INTF_BYPASS\n", tx_intf_compatible_str); 264 mixer_cfg = 0x200202F6; 265 duc_input_ch_sel = 0; 266 ant_sel=2; 267 break; 268 269 default: 270 printk("%s hw_init mode %d is wrong!\n", tx_intf_compatible_str, mode); 271 err=1; 272 } 273 274 if (mode!=TX_INTF_AXIS_LOOP_BACK) { 275 tx_intf_api->TX_INTF_REG_MISC_SEL_write(1<<1);// bit1: 0-connect dac to ADI dma; 1-connect dac to our intf 276 277 tx_intf_api->TX_INTF_REG_MIXER_CFG_write(mixer_cfg); 278 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 279 tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_write(duc_input_ch_sel); 280 tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_write(2); 281 tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*10)<<16)|(10*10) );//high 16bit 5GHz; low 16 bit 2.4GHz. counter speed 10MHz is assumed 282 283 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(num_dma_symbol_to_pl); 284 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps); 285 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0); 286 tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_write(420); 287 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x4); //.src_sel(slv_reg14[2:0]), 0-s00_axis_tlast,1-ap_start,2-tx_start_from_acc,3-tx_end_from_acc,4-tx_try_complete from xpu 288 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x30004); //disable interrupt 289 tx_intf_api->TX_INTF_REG_BB_GAIN_write(100); 290 tx_intf_api->TX_INTF_REG_ANT_SEL_write(ant_sel); 291 tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write((1<<3)|(2<<4)); 292 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0x434); 293 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 294 } 295 296 if (mode == TX_INTF_BYPASS) { 297 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0x100); //slv_reg10[8] 298 } 299 300 printk("%s hw_init err %d\n", tx_intf_compatible_str, err); 301 return(err); 302 } 303 304 static int dev_probe(struct platform_device *pdev) 305 { 306 struct device_node *np = pdev->dev.of_node; 307 struct resource *io; 308 int err=1; 309 310 printk("\n"); 311 312 if (np) { 313 const struct of_device_id *match; 314 315 match = of_match_node(dev_of_ids, np); 316 if (match) { 317 printk("%s dev_probe match!\n", tx_intf_compatible_str); 318 err = 0; 319 } 320 } 321 322 if (err) 323 return err; 324 325 tx_intf_api->hw_init=hw_init; 326 327 tx_intf_api->reg_read=reg_read; 328 tx_intf_api->reg_write=reg_write; 329 330 tx_intf_api->TX_INTF_REG_MULTI_RST_read=TX_INTF_REG_MULTI_RST_read; 331 tx_intf_api->TX_INTF_REG_MIXER_CFG_read=TX_INTF_REG_MIXER_CFG_read; 332 tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_read=TX_INTF_REG_WIFI_TX_MODE_read; 333 tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_read=TX_INTF_REG_IQ_SRC_SEL_read; 334 tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_read=TX_INTF_REG_CTS_TOSELF_CONFIG_read; 335 tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_read=TX_INTF_REG_START_TRANS_TO_PS_MODE_read; 336 tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read; 337 tx_intf_api->TX_INTF_REG_MISC_SEL_read=TX_INTF_REG_MISC_SEL_read; 338 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read; 339 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read; 340 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_read=TX_INTF_REG_CFG_DATA_TO_ANT_read; 341 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_read=TX_INTF_REG_S_AXIS_FIFO_TH_read; 342 tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_read=TX_INTF_REG_TX_HOLD_THRESHOLD_read; 343 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_read=TX_INTF_REG_INTERRUPT_SEL_read; 344 tx_intf_api->TX_INTF_REG_BB_GAIN_read=TX_INTF_REG_BB_GAIN_read; 345 tx_intf_api->TX_INTF_REG_ANT_SEL_read=TX_INTF_REG_ANT_SEL_read; 346 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read=TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read; 347 tx_intf_api->TX_INTF_REG_PKT_INFO_read=TX_INTF_REG_PKT_INFO_read; 348 tx_intf_api->TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read=TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read; 349 350 tx_intf_api->TX_INTF_REG_MULTI_RST_write=TX_INTF_REG_MULTI_RST_write; 351 tx_intf_api->TX_INTF_REG_MIXER_CFG_write=TX_INTF_REG_MIXER_CFG_write; 352 tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write=TX_INTF_REG_WIFI_TX_MODE_write; 353 tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_write=TX_INTF_REG_IQ_SRC_SEL_write; 354 tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_write=TX_INTF_REG_CTS_TOSELF_CONFIG_write; 355 tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_write=TX_INTF_REG_START_TRANS_TO_PS_MODE_write; 356 tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write; 357 tx_intf_api->TX_INTF_REG_MISC_SEL_write=TX_INTF_REG_MISC_SEL_write; 358 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write; 359 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write; 360 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write=TX_INTF_REG_CFG_DATA_TO_ANT_write; 361 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write=TX_INTF_REG_S_AXIS_FIFO_TH_write; 362 tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_write=TX_INTF_REG_TX_HOLD_THRESHOLD_write; 363 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write=TX_INTF_REG_INTERRUPT_SEL_write; 364 tx_intf_api->TX_INTF_REG_BB_GAIN_write=TX_INTF_REG_BB_GAIN_write; 365 tx_intf_api->TX_INTF_REG_ANT_SEL_write=TX_INTF_REG_ANT_SEL_write; 366 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write=TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write; 367 tx_intf_api->TX_INTF_REG_PKT_INFO_write=TX_INTF_REG_PKT_INFO_write; 368 369 /* Request and map I/O memory */ 370 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 371 base_addr = devm_ioremap_resource(&pdev->dev, io); 372 if (IS_ERR(base_addr)) 373 return PTR_ERR(base_addr); 374 375 printk("%s dev_probe io start 0x%08llx end 0x%08llx name %s flags 0x%08x desc 0x%08x\n", tx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); 376 printk("%s dev_probe base_addr 0x%p\n", tx_intf_compatible_str,(void*)base_addr); 377 printk("%s dev_probe tx_intf_driver_api_inst 0x%p\n", tx_intf_compatible_str, (void*)(&tx_intf_driver_api_inst) ); 378 printk("%s dev_probe tx_intf_api 0x%p\n", tx_intf_compatible_str, (void*)tx_intf_api); 379 380 printk("%s dev_probe succeed!\n", tx_intf_compatible_str); 381 382 //err = hw_init(TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 8, 8); 383 //err = hw_init(TX_INTF_BYPASS, 8, 8); 384 err = hw_init(TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 8, 8); // make sure dac is connected to original ad9361 dma 385 386 return err; 387 } 388 389 static int dev_remove(struct platform_device *pdev) 390 { 391 printk("\n"); 392 393 printk("%s dev_remove base_addr 0x%p\n", tx_intf_compatible_str,(void*)base_addr); 394 printk("%s dev_remove tx_intf_driver_api_inst 0x%p\n", tx_intf_compatible_str, (void*)(&tx_intf_driver_api_inst) ); 395 printk("%s dev_remove tx_intf_api 0x%p\n", tx_intf_compatible_str, (void*)tx_intf_api); 396 397 printk("%s dev_remove succeed!\n", tx_intf_compatible_str); 398 return 0; 399 } 400 401 static struct platform_driver dev_driver = { 402 .driver = { 403 .name = "sdr,tx_intf", 404 .owner = THIS_MODULE, 405 .of_match_table = dev_of_ids, 406 }, 407 .probe = dev_probe, 408 .remove = dev_remove, 409 }; 410 411 module_platform_driver(dev_driver); 412 413 MODULE_AUTHOR("Xianjun Jiao"); 414 MODULE_DESCRIPTION("sdr,tx_intf"); 415 MODULE_LICENSE("GPL v2"); 416