1 /* 2 * axi lite register access driver 3 * Author: Xianjun Jiao, Michael Mehari, Wei Liu 4 * SPDX-FileCopyrightText: 2019 UGent 5 * SPDX-License-Identifier: AGPL-3.0-or-later 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/dmapool.h> 10 #include <linux/dma/xilinx_dma.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/of_dma.h> 18 #include <linux/of_platform.h> 19 #include <linux/of_irq.h> 20 #include <linux/slab.h> 21 #include <linux/clk.h> 22 #include <linux/io-64-nonatomic-lo-hi.h> 23 24 #include "../hw_def.h" 25 26 static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design 27 28 /* IO accessors */ 29 static inline u32 reg_read(u32 reg) 30 { 31 return ioread32(base_addr + reg); 32 } 33 34 static inline void reg_write(u32 reg, u32 value) 35 { 36 iowrite32(value, base_addr + reg); 37 } 38 39 static inline u32 TX_INTF_REG_MULTI_RST_read(void){ 40 return reg_read(TX_INTF_REG_MULTI_RST_ADDR); 41 } 42 43 static inline u32 TX_INTF_REG_MIXER_CFG_read(void){ 44 return reg_read(TX_INTF_REG_MIXER_CFG_ADDR); 45 } 46 47 static inline u32 TX_INTF_REG_WIFI_TX_MODE_read(void){ 48 return reg_read(TX_INTF_REG_WIFI_TX_MODE_ADDR); 49 } 50 51 static inline u32 TX_INTF_REG_IQ_SRC_SEL_read(void){ 52 return reg_read(TX_INTF_REG_IQ_SRC_SEL_ADDR); 53 } 54 55 static inline u32 TX_INTF_REG_CTS_TOSELF_CONFIG_read(void){ 56 return reg_read(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR); 57 } 58 59 static inline u32 TX_INTF_REG_CSI_FUZZER_read(void){ 60 return reg_read(TX_INTF_REG_CSI_FUZZER_ADDR); 61 } 62 63 static inline u32 TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read(void){ 64 return reg_read(TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR); 65 } 66 67 static inline u32 TX_INTF_REG_MISC_SEL_read(void){ 68 return reg_read(TX_INTF_REG_MISC_SEL_ADDR); 69 } 70 71 static inline u32 TX_INTF_REG_TX_CONFIG_read(void){ 72 return reg_read(TX_INTF_REG_TX_CONFIG_ADDR); 73 } 74 75 static inline u32 TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read(void){ 76 return reg_read(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR); 77 } 78 79 static inline u32 TX_INTF_REG_CFG_DATA_TO_ANT_read(void){ 80 return reg_read(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR); 81 } 82 83 static inline u32 TX_INTF_REG_S_AXIS_FIFO_TH_read(void){ 84 return reg_read(TX_INTF_REG_S_AXIS_FIFO_TH_ADDR); 85 } 86 87 static inline u32 TX_INTF_REG_TX_HOLD_THRESHOLD_read(void){ 88 return reg_read(TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR); 89 } 90 91 static inline u32 TX_INTF_REG_INTERRUPT_SEL_read(void){ 92 return reg_read(TX_INTF_REG_INTERRUPT_SEL_ADDR); 93 } 94 95 static inline u32 TX_INTF_REG_AMPDU_ACTION_CONFIG_read(void){ 96 return reg_read(TX_INTF_REG_AMPDU_ACTION_CONFIG_ADDR); 97 } 98 99 static inline u32 TX_INTF_REG_BB_GAIN_read(void){ 100 return reg_read(TX_INTF_REG_BB_GAIN_ADDR); 101 } 102 103 static inline u32 TX_INTF_REG_ANT_SEL_read(void){ 104 return reg_read(TX_INTF_REG_ANT_SEL_ADDR); 105 } 106 107 static inline u32 TX_INTF_REG_PHY_HDR_CONFIG_read(void){ 108 return reg_read(TX_INTF_REG_PHY_HDR_CONFIG_ADDR); 109 } 110 111 static inline u32 TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read(void){ 112 return reg_read(TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR); 113 } 114 115 static inline u32 TX_INTF_REG_PKT_INFO1_read(void){ 116 return reg_read(TX_INTF_REG_PKT_INFO1_ADDR); 117 } 118 119 static inline u32 TX_INTF_REG_PKT_INFO2_read(void){ 120 return reg_read(TX_INTF_REG_PKT_INFO2_ADDR); 121 } 122 123 static inline u32 TX_INTF_REG_PKT_INFO3_read(void){ 124 return reg_read(TX_INTF_REG_PKT_INFO3_ADDR); 125 } 126 127 static inline u32 TX_INTF_REG_PKT_INFO4_read(void){ 128 return reg_read(TX_INTF_REG_PKT_INFO4_ADDR); 129 } 130 131 static inline u32 TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read(void){ 132 return reg_read(TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_ADDR); 133 } 134 135 //-------------------------------------------------------- 136 137 static inline void TX_INTF_REG_MULTI_RST_write(u32 value){ 138 reg_write(TX_INTF_REG_MULTI_RST_ADDR, value); 139 } 140 141 static inline void TX_INTF_REG_MIXER_CFG_write(u32 value){ 142 reg_write(TX_INTF_REG_MIXER_CFG_ADDR, value); 143 } 144 145 static inline void TX_INTF_REG_WIFI_TX_MODE_write(u32 value){ 146 reg_write(TX_INTF_REG_WIFI_TX_MODE_ADDR, value); 147 } 148 149 static inline void TX_INTF_REG_IQ_SRC_SEL_write(u32 value){ 150 reg_write(TX_INTF_REG_IQ_SRC_SEL_ADDR, value); 151 } 152 153 static inline void TX_INTF_REG_CTS_TOSELF_CONFIG_write(u32 value){ 154 reg_write(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR, value); 155 } 156 157 static inline void TX_INTF_REG_CSI_FUZZER_write(u32 value){ 158 reg_write(TX_INTF_REG_CSI_FUZZER_ADDR, value); 159 } 160 161 static inline void TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write(u32 value){ 162 reg_write(TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR, value); 163 } 164 165 static inline void TX_INTF_REG_MISC_SEL_write(u32 value){ 166 reg_write(TX_INTF_REG_MISC_SEL_ADDR, value); 167 } 168 169 static inline void TX_INTF_REG_TX_CONFIG_write(u32 value){ 170 reg_write(TX_INTF_REG_TX_CONFIG_ADDR, value); 171 } 172 173 static inline void TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(u32 value){ 174 reg_write(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR, value); 175 } 176 177 static inline void TX_INTF_REG_CFG_DATA_TO_ANT_write(u32 value){ 178 reg_write(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR, value); 179 } 180 181 static inline void TX_INTF_REG_S_AXIS_FIFO_TH_write(u32 value){ 182 reg_write(TX_INTF_REG_S_AXIS_FIFO_TH_ADDR, value); 183 } 184 185 static inline void TX_INTF_REG_TX_HOLD_THRESHOLD_write(u32 value){ 186 reg_write(TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR, value); 187 } 188 189 static inline void TX_INTF_REG_INTERRUPT_SEL_write(u32 value){ 190 reg_write(TX_INTF_REG_INTERRUPT_SEL_ADDR, value); 191 } 192 193 static inline void TX_INTF_REG_AMPDU_ACTION_CONFIG_write(u32 value){ 194 reg_write(TX_INTF_REG_AMPDU_ACTION_CONFIG_ADDR, value); 195 } 196 197 static inline void TX_INTF_REG_BB_GAIN_write(u32 value){ 198 reg_write(TX_INTF_REG_BB_GAIN_ADDR, value); 199 } 200 201 static inline void TX_INTF_REG_ANT_SEL_write(u32 value){ 202 reg_write(TX_INTF_REG_ANT_SEL_ADDR, value); 203 } 204 205 static inline void TX_INTF_REG_PHY_HDR_CONFIG_write(u32 value){ 206 reg_write(TX_INTF_REG_PHY_HDR_CONFIG_ADDR, value); 207 } 208 209 static inline void TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write(u32 value){ 210 reg_write(TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR, value); 211 } 212 213 static inline void TX_INTF_REG_PKT_INFO1_write(u32 value){ 214 reg_write(TX_INTF_REG_PKT_INFO1_ADDR,value); 215 } 216 217 static inline void TX_INTF_REG_PKT_INFO2_write(u32 value){ 218 reg_write(TX_INTF_REG_PKT_INFO2_ADDR,value); 219 } 220 221 static inline void TX_INTF_REG_PKT_INFO3_write(u32 value){ 222 reg_write(TX_INTF_REG_PKT_INFO3_ADDR,value); 223 } 224 225 static inline void TX_INTF_REG_PKT_INFO4_write(u32 value){ 226 reg_write(TX_INTF_REG_PKT_INFO4_ADDR,value); 227 } 228 229 static const struct of_device_id dev_of_ids[] = { 230 { .compatible = "sdr,tx_intf", }, 231 {} 232 }; 233 MODULE_DEVICE_TABLE(of, dev_of_ids); 234 235 static struct tx_intf_driver_api tx_intf_driver_api_inst; 236 static struct tx_intf_driver_api *tx_intf_api = &tx_intf_driver_api_inst; 237 EXPORT_SYMBOL(tx_intf_api); 238 239 static inline u32 hw_init(enum tx_intf_mode mode, u32 tx_config, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type){ 240 int err=0, i; 241 u32 mixer_cfg=0, duc_input_ch_sel = 0, ant_sel=0; 242 243 printk("%s hw_init mode %d\n", tx_intf_compatible_str, mode); 244 245 //rst 246 for (i=0;i<8;i++) 247 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 248 for (i=0;i<32;i++) 249 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0xFFFFFFFF); 250 for (i=0;i<8;i++) 251 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 252 253 254 if(fpga_type == LARGE_FPGA) // LARGE FPGA: MAX_NUM_DMA_SYMBOL = 8192 255 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(8192-200); // when only 200 DMA symbol room left in fifo, stop Linux queue 256 else if(fpga_type == SMALL_FPGA) // SMALL FPGA: MAX_NUM_DMA_SYMBOL = 4096 257 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(4096-200); // when only 200 DMA symbol room left in fifo, stop Linux queue 258 259 switch(mode) 260 { 261 case TX_INTF_AXIS_LOOP_BACK: 262 tx_intf_api->TX_INTF_REG_MISC_SEL_write(0<<1);// bit1: 0-connect dac to ADI dma; 1-connect dac to our intf 263 printk("%s hw_init mode TX_INTF_AXIS_LOOP_BACK\n", tx_intf_compatible_str); 264 break; 265 266 case TX_INTF_BW_20MHZ_AT_0MHZ_ANT0: 267 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT0\n", tx_intf_compatible_str); 268 mixer_cfg = 0x2001F400; 269 duc_input_ch_sel = 0; 270 ant_sel=1; 271 break; 272 273 case TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0: 274 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0\n", tx_intf_compatible_str); 275 mixer_cfg = 0x2001F602; 276 duc_input_ch_sel = 0; 277 ant_sel=1; 278 break; 279 280 case TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0: 281 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0\n", tx_intf_compatible_str); 282 mixer_cfg = 0x200202F6; 283 duc_input_ch_sel = 0; 284 ant_sel=1; 285 break; 286 287 case TX_INTF_BW_20MHZ_AT_0MHZ_ANT1: 288 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT1\n", tx_intf_compatible_str); 289 mixer_cfg = 0x2001F400; 290 duc_input_ch_sel = 0; 291 ant_sel=2; 292 break; 293 294 case TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1: 295 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1\n", tx_intf_compatible_str); 296 mixer_cfg = 0x2001F602; 297 duc_input_ch_sel = 0; 298 ant_sel=2; 299 break; 300 301 case TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1: 302 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1\n", tx_intf_compatible_str); 303 mixer_cfg = 0x200202F6; 304 duc_input_ch_sel = 0; 305 ant_sel=2; 306 break; 307 308 case TX_INTF_BYPASS: 309 printk("%s hw_init mode TX_INTF_BYPASS\n", tx_intf_compatible_str); 310 mixer_cfg = 0x200202F6; 311 duc_input_ch_sel = 0; 312 ant_sel=2; 313 break; 314 315 default: 316 printk("%s hw_init mode %d is wrong!\n", tx_intf_compatible_str, mode); 317 err=1; 318 } 319 320 if (mode!=TX_INTF_AXIS_LOOP_BACK) { 321 tx_intf_api->TX_INTF_REG_MISC_SEL_write(1<<1);// bit1: 0-connect dac to ADI dma; 1-connect dac to our intf 322 323 tx_intf_api->TX_INTF_REG_MIXER_CFG_write(mixer_cfg); 324 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 325 tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_write(duc_input_ch_sel); 326 tx_intf_api->TX_INTF_REG_CSI_FUZZER_write(0); 327 tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*10)<<16)|(10*10) );//high 16bit 5GHz; low 16 bit 2.4GHz. counter speed 10MHz is assumed 328 329 tx_intf_api->TX_INTF_REG_TX_CONFIG_write(tx_config); 330 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps); 331 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0); 332 tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_write(420); 333 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x4); //.src_sel(slv_reg14[2:0]), 0-s00_axis_tlast,1-ap_start,2-tx_start_from_acc,3-tx_end_from_acc,4-tx_try_complete from xpu 334 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x30004); //disable interrupt 335 tx_intf_api->TX_INTF_REG_BB_GAIN_write(100); 336 tx_intf_api->TX_INTF_REG_ANT_SEL_write(ant_sel); 337 tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write((1<<3)|(2<<4)); 338 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0x434); 339 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 340 } 341 342 if (mode == TX_INTF_BYPASS) { 343 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0x100); //slv_reg10[8] 344 } 345 346 printk("%s hw_init err %d\n", tx_intf_compatible_str, err); 347 return(err); 348 } 349 350 static int dev_probe(struct platform_device *pdev) 351 { 352 struct device_node *np = pdev->dev.of_node; 353 struct resource *io; 354 int err=1; 355 356 printk("\n"); 357 358 if (np) { 359 const struct of_device_id *match; 360 361 match = of_match_node(dev_of_ids, np); 362 if (match) { 363 printk("%s dev_probe match!\n", tx_intf_compatible_str); 364 err = 0; 365 } 366 } 367 368 if (err) 369 return err; 370 371 tx_intf_api->hw_init=hw_init; 372 373 tx_intf_api->reg_read=reg_read; 374 tx_intf_api->reg_write=reg_write; 375 376 tx_intf_api->TX_INTF_REG_MULTI_RST_read=TX_INTF_REG_MULTI_RST_read; 377 tx_intf_api->TX_INTF_REG_MIXER_CFG_read=TX_INTF_REG_MIXER_CFG_read; 378 tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_read=TX_INTF_REG_WIFI_TX_MODE_read; 379 tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_read=TX_INTF_REG_IQ_SRC_SEL_read; 380 tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_read=TX_INTF_REG_CTS_TOSELF_CONFIG_read; 381 tx_intf_api->TX_INTF_REG_CSI_FUZZER_read=TX_INTF_REG_CSI_FUZZER_read; 382 tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read; 383 tx_intf_api->TX_INTF_REG_MISC_SEL_read=TX_INTF_REG_MISC_SEL_read; 384 tx_intf_api->TX_INTF_REG_TX_CONFIG_read=TX_INTF_REG_TX_CONFIG_read; 385 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read; 386 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_read=TX_INTF_REG_CFG_DATA_TO_ANT_read; 387 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_read=TX_INTF_REG_S_AXIS_FIFO_TH_read; 388 tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_read=TX_INTF_REG_TX_HOLD_THRESHOLD_read; 389 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_read=TX_INTF_REG_INTERRUPT_SEL_read; 390 tx_intf_api->TX_INTF_REG_AMPDU_ACTION_CONFIG_read=TX_INTF_REG_AMPDU_ACTION_CONFIG_read; 391 tx_intf_api->TX_INTF_REG_BB_GAIN_read=TX_INTF_REG_BB_GAIN_read; 392 tx_intf_api->TX_INTF_REG_ANT_SEL_read=TX_INTF_REG_ANT_SEL_read; 393 tx_intf_api->TX_INTF_REG_PHY_HDR_CONFIG_read=TX_INTF_REG_PHY_HDR_CONFIG_read; 394 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read=TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read; 395 tx_intf_api->TX_INTF_REG_PKT_INFO1_read=TX_INTF_REG_PKT_INFO1_read; 396 tx_intf_api->TX_INTF_REG_PKT_INFO2_read=TX_INTF_REG_PKT_INFO2_read; 397 tx_intf_api->TX_INTF_REG_PKT_INFO3_read=TX_INTF_REG_PKT_INFO3_read; 398 tx_intf_api->TX_INTF_REG_PKT_INFO4_read=TX_INTF_REG_PKT_INFO4_read; 399 tx_intf_api->TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read=TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read; 400 401 tx_intf_api->TX_INTF_REG_MULTI_RST_write=TX_INTF_REG_MULTI_RST_write; 402 tx_intf_api->TX_INTF_REG_MIXER_CFG_write=TX_INTF_REG_MIXER_CFG_write; 403 tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write=TX_INTF_REG_WIFI_TX_MODE_write; 404 tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_write=TX_INTF_REG_IQ_SRC_SEL_write; 405 tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_write=TX_INTF_REG_CTS_TOSELF_CONFIG_write; 406 tx_intf_api->TX_INTF_REG_CSI_FUZZER_write=TX_INTF_REG_CSI_FUZZER_write; 407 tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write; 408 tx_intf_api->TX_INTF_REG_MISC_SEL_write=TX_INTF_REG_MISC_SEL_write; 409 tx_intf_api->TX_INTF_REG_TX_CONFIG_write=TX_INTF_REG_TX_CONFIG_write; 410 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write; 411 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write=TX_INTF_REG_CFG_DATA_TO_ANT_write; 412 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write=TX_INTF_REG_S_AXIS_FIFO_TH_write; 413 tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_write=TX_INTF_REG_TX_HOLD_THRESHOLD_write; 414 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write=TX_INTF_REG_INTERRUPT_SEL_write; 415 tx_intf_api->TX_INTF_REG_AMPDU_ACTION_CONFIG_write=TX_INTF_REG_AMPDU_ACTION_CONFIG_write; 416 tx_intf_api->TX_INTF_REG_BB_GAIN_write=TX_INTF_REG_BB_GAIN_write; 417 tx_intf_api->TX_INTF_REG_ANT_SEL_write=TX_INTF_REG_ANT_SEL_write; 418 tx_intf_api->TX_INTF_REG_PHY_HDR_CONFIG_write=TX_INTF_REG_PHY_HDR_CONFIG_write; 419 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write=TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write; 420 tx_intf_api->TX_INTF_REG_PKT_INFO1_write=TX_INTF_REG_PKT_INFO1_write; 421 tx_intf_api->TX_INTF_REG_PKT_INFO2_write=TX_INTF_REG_PKT_INFO2_write; 422 tx_intf_api->TX_INTF_REG_PKT_INFO3_write=TX_INTF_REG_PKT_INFO3_write; 423 tx_intf_api->TX_INTF_REG_PKT_INFO4_write=TX_INTF_REG_PKT_INFO4_write; 424 425 /* Request and map I/O memory */ 426 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 427 base_addr = devm_ioremap_resource(&pdev->dev, io); 428 if (IS_ERR(base_addr)) 429 return PTR_ERR(base_addr); 430 431 printk("%s dev_probe io start 0x%08llx end 0x%08llx name %s flags 0x%08x desc 0x%08x\n", tx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); 432 printk("%s dev_probe base_addr 0x%p\n", tx_intf_compatible_str,(void*)base_addr); 433 printk("%s dev_probe tx_intf_driver_api_inst 0x%p\n", tx_intf_compatible_str, (void*)(&tx_intf_driver_api_inst) ); 434 printk("%s dev_probe tx_intf_api 0x%p\n", tx_intf_compatible_str, (void*)tx_intf_api); 435 436 printk("%s dev_probe succeed!\n", tx_intf_compatible_str); 437 438 //err = hw_init(TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 8, 8, SMALL_FPGA); 439 //err = hw_init(TX_INTF_BYPASS, 8, 8, SMALL_FPGA); 440 err = hw_init(TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 8, 8, SMALL_FPGA); // make sure dac is connected to original ad9361 dma 441 442 return err; 443 } 444 445 static int dev_remove(struct platform_device *pdev) 446 { 447 printk("\n"); 448 449 printk("%s dev_remove base_addr 0x%p\n", tx_intf_compatible_str,(void*)base_addr); 450 printk("%s dev_remove tx_intf_driver_api_inst 0x%p\n", tx_intf_compatible_str, (void*)(&tx_intf_driver_api_inst) ); 451 printk("%s dev_remove tx_intf_api 0x%p\n", tx_intf_compatible_str, (void*)tx_intf_api); 452 453 printk("%s dev_remove succeed!\n", tx_intf_compatible_str); 454 return 0; 455 } 456 457 static struct platform_driver dev_driver = { 458 .driver = { 459 .name = "sdr,tx_intf", 460 .owner = THIS_MODULE, 461 .of_match_table = dev_of_ids, 462 }, 463 .probe = dev_probe, 464 .remove = dev_remove, 465 }; 466 467 module_platform_driver(dev_driver); 468 469 MODULE_AUTHOR("Xianjun Jiao"); 470 MODULE_DESCRIPTION("sdr,tx_intf"); 471 MODULE_LICENSE("GPL v2"); 472