1 /* 2 * axi lite register access driver 3 * Xianjun jiao. [email protected]; [email protected] 4 */ 5 6 #include <linux/bitops.h> 7 #include <linux/dmapool.h> 8 #include <linux/dma/xilinx_dma.h> 9 #include <linux/init.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/module.h> 14 #include <linux/of_address.h> 15 #include <linux/of_dma.h> 16 #include <linux/of_platform.h> 17 #include <linux/of_irq.h> 18 #include <linux/slab.h> 19 #include <linux/clk.h> 20 #include <linux/io-64-nonatomic-lo-hi.h> 21 22 #include "../hw_def.h" 23 24 static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design 25 26 /* IO accessors */ 27 static inline u32 reg_read(u32 reg) 28 { 29 return ioread32(base_addr + reg); 30 } 31 32 static inline void reg_write(u32 reg, u32 value) 33 { 34 iowrite32(value, base_addr + reg); 35 } 36 37 static inline u32 TX_INTF_REG_MULTI_RST_read(void){ 38 return reg_read(TX_INTF_REG_MULTI_RST_ADDR); 39 } 40 41 static inline u32 TX_INTF_REG_MIXER_CFG_read(void){ 42 return reg_read(TX_INTF_REG_MIXER_CFG_ADDR); 43 } 44 45 static inline u32 TX_INTF_REG_WIFI_TX_MODE_read(void){ 46 return reg_read(TX_INTF_REG_WIFI_TX_MODE_ADDR); 47 } 48 49 static inline u32 TX_INTF_REG_IQ_SRC_SEL_read(void){ 50 return reg_read(TX_INTF_REG_IQ_SRC_SEL_ADDR); 51 } 52 53 static inline u32 TX_INTF_REG_CTS_TOSELF_CONFIG_read(void){ 54 return reg_read(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR); 55 } 56 57 static inline u32 TX_INTF_REG_START_TRANS_TO_PS_MODE_read(void){ 58 return reg_read(TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR); 59 } 60 61 static inline u32 TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read(void){ 62 return reg_read(TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR); 63 } 64 65 static inline u32 TX_INTF_REG_MISC_SEL_read(void){ 66 return reg_read(TX_INTF_REG_MISC_SEL_ADDR); 67 } 68 69 static inline u32 TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read(void){ 70 return reg_read(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR); 71 } 72 73 static inline u32 TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read(void){ 74 return reg_read(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR); 75 } 76 77 static inline u32 TX_INTF_REG_CFG_DATA_TO_ANT_read(void){ 78 return reg_read(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR); 79 } 80 81 static inline u32 TX_INTF_REG_S_AXIS_FIFO_TH_read(void){ 82 return reg_read(TX_INTF_REG_S_AXIS_FIFO_TH_ADDR); 83 } 84 85 static inline u32 TX_INTF_REG_TX_HOLD_THRESHOLD_read(void){ 86 return reg_read(TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR); 87 } 88 89 static inline u32 TX_INTF_REG_INTERRUPT_SEL_read(void){ 90 return reg_read(TX_INTF_REG_INTERRUPT_SEL_ADDR); 91 } 92 93 static inline u32 TX_INTF_REG_BB_GAIN_read(void){ 94 return reg_read(TX_INTF_REG_BB_GAIN_ADDR); 95 } 96 97 static inline u32 TX_INTF_REG_ANT_SEL_read(void){ 98 return reg_read(TX_INTF_REG_ANT_SEL_ADDR); 99 } 100 101 static inline u32 TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read(void){ 102 return reg_read(TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR); 103 } 104 105 static inline u32 TX_INTF_REG_PKT_INFO_read(void){ 106 return reg_read(TX_INTF_REG_PKT_INFO_ADDR); 107 } 108 109 static inline u32 TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read(void){ 110 return reg_read(TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_ADDR); 111 } 112 113 //-------------------------------------------------------- 114 115 static inline void TX_INTF_REG_MULTI_RST_write(u32 value){ 116 reg_write(TX_INTF_REG_MULTI_RST_ADDR, value); 117 } 118 119 static inline void TX_INTF_REG_MIXER_CFG_write(u32 value){ 120 reg_write(TX_INTF_REG_MIXER_CFG_ADDR, value); 121 } 122 123 static inline void TX_INTF_REG_WIFI_TX_MODE_write(u32 value){ 124 reg_write(TX_INTF_REG_WIFI_TX_MODE_ADDR, value); 125 } 126 127 static inline void TX_INTF_REG_IQ_SRC_SEL_write(u32 value){ 128 reg_write(TX_INTF_REG_IQ_SRC_SEL_ADDR, value); 129 } 130 131 static inline void TX_INTF_REG_CTS_TOSELF_CONFIG_write(u32 value){ 132 reg_write(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR, value); 133 } 134 135 static inline void TX_INTF_REG_START_TRANS_TO_PS_MODE_write(u32 value){ 136 reg_write(TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR, value); 137 } 138 139 static inline void TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write(u32 value){ 140 reg_write(TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR, value); 141 } 142 143 static inline void TX_INTF_REG_MISC_SEL_write(u32 value){ 144 reg_write(TX_INTF_REG_MISC_SEL_ADDR, value); 145 } 146 147 static inline void TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(u32 value){ 148 reg_write(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR, value); 149 } 150 151 static inline void TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(u32 value){ 152 reg_write(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR, value); 153 } 154 155 static inline void TX_INTF_REG_CFG_DATA_TO_ANT_write(u32 value){ 156 reg_write(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR, value); 157 } 158 159 static inline void TX_INTF_REG_S_AXIS_FIFO_TH_write(u32 value){ 160 reg_write(TX_INTF_REG_S_AXIS_FIFO_TH_ADDR, value); 161 } 162 163 static inline void TX_INTF_REG_TX_HOLD_THRESHOLD_write(u32 value){ 164 reg_write(TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR, value); 165 } 166 167 static inline void TX_INTF_REG_INTERRUPT_SEL_write(u32 value){ 168 reg_write(TX_INTF_REG_INTERRUPT_SEL_ADDR, value); 169 } 170 171 static inline void TX_INTF_REG_BB_GAIN_write(u32 value){ 172 reg_write(TX_INTF_REG_BB_GAIN_ADDR, value); 173 } 174 175 static inline void TX_INTF_REG_ANT_SEL_write(u32 value){ 176 reg_write(TX_INTF_REG_ANT_SEL_ADDR, value); 177 } 178 179 static inline void TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write(u32 value){ 180 reg_write(TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR, value); 181 } 182 183 static inline void TX_INTF_REG_PKT_INFO_write(u32 value){ 184 reg_write(TX_INTF_REG_PKT_INFO_ADDR,value); 185 } 186 187 static const struct of_device_id dev_of_ids[] = { 188 { .compatible = "sdr,tx_intf", }, 189 {} 190 }; 191 MODULE_DEVICE_TABLE(of, dev_of_ids); 192 193 static struct tx_intf_driver_api tx_intf_driver_api_inst; 194 static struct tx_intf_driver_api *tx_intf_api = &tx_intf_driver_api_inst; 195 EXPORT_SYMBOL(tx_intf_api); 196 197 static inline u32 hw_init(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type){ 198 int err=0, i; 199 u32 mixer_cfg=0, duc_input_ch_sel = 0, ant_sel=0; 200 201 printk("%s hw_init mode %d\n", tx_intf_compatible_str, mode); 202 203 //rst 204 for (i=0;i<8;i++) 205 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 206 for (i=0;i<32;i++) 207 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0xFFFFFFFF); 208 for (i=0;i<8;i++) 209 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 210 211 212 if(fpga_type == LARGE_FPGA) // LARGE FPGA: MAX_NUM_DMA_SYMBOL = 8192 213 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(8192-200); // when only 200 DMA symbol room left in fifo, stop Linux queue 214 else if(fpga_type == SMALL_FPGA) // SMALL FPGA: MAX_NUM_DMA_SYMBOL = 4096 215 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(4096-200); // when only 200 DMA symbol room left in fifo, stop Linux queue 216 217 switch(mode) 218 { 219 case TX_INTF_AXIS_LOOP_BACK: 220 tx_intf_api->TX_INTF_REG_MISC_SEL_write(0<<1);// bit1: 0-connect dac to ADI dma; 1-connect dac to our intf 221 printk("%s hw_init mode TX_INTF_AXIS_LOOP_BACK\n", tx_intf_compatible_str); 222 break; 223 224 case TX_INTF_BW_20MHZ_AT_0MHZ_ANT0: 225 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT0\n", tx_intf_compatible_str); 226 mixer_cfg = 0x2001F400; 227 duc_input_ch_sel = 0; 228 ant_sel=1; 229 break; 230 231 case TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0: 232 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0\n", tx_intf_compatible_str); 233 mixer_cfg = 0x2001F602; 234 duc_input_ch_sel = 0; 235 ant_sel=1; 236 break; 237 238 case TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0: 239 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0\n", tx_intf_compatible_str); 240 mixer_cfg = 0x200202F6; 241 duc_input_ch_sel = 0; 242 ant_sel=1; 243 break; 244 245 case TX_INTF_BW_20MHZ_AT_0MHZ_ANT1: 246 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT1\n", tx_intf_compatible_str); 247 mixer_cfg = 0x2001F400; 248 duc_input_ch_sel = 0; 249 ant_sel=2; 250 break; 251 252 case TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1: 253 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1\n", tx_intf_compatible_str); 254 mixer_cfg = 0x2001F602; 255 duc_input_ch_sel = 0; 256 ant_sel=2; 257 break; 258 259 case TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1: 260 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1\n", tx_intf_compatible_str); 261 mixer_cfg = 0x200202F6; 262 duc_input_ch_sel = 0; 263 ant_sel=2; 264 break; 265 266 case TX_INTF_BYPASS: 267 printk("%s hw_init mode TX_INTF_BYPASS\n", tx_intf_compatible_str); 268 mixer_cfg = 0x200202F6; 269 duc_input_ch_sel = 0; 270 ant_sel=2; 271 break; 272 273 default: 274 printk("%s hw_init mode %d is wrong!\n", tx_intf_compatible_str, mode); 275 err=1; 276 } 277 278 if (mode!=TX_INTF_AXIS_LOOP_BACK) { 279 tx_intf_api->TX_INTF_REG_MISC_SEL_write(1<<1);// bit1: 0-connect dac to ADI dma; 1-connect dac to our intf 280 281 tx_intf_api->TX_INTF_REG_MIXER_CFG_write(mixer_cfg); 282 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 283 tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_write(duc_input_ch_sel); 284 tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_write(2); 285 tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*10)<<16)|(10*10) );//high 16bit 5GHz; low 16 bit 2.4GHz. counter speed 10MHz is assumed 286 287 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(num_dma_symbol_to_pl); 288 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps); 289 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0); 290 tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_write(420); 291 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x4); //.src_sel(slv_reg14[2:0]), 0-s00_axis_tlast,1-ap_start,2-tx_start_from_acc,3-tx_end_from_acc,4-tx_try_complete from xpu 292 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x30004); //disable interrupt 293 tx_intf_api->TX_INTF_REG_BB_GAIN_write(100); 294 tx_intf_api->TX_INTF_REG_ANT_SEL_write(ant_sel); 295 tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write((1<<3)|(2<<4)); 296 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0x434); 297 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 298 } 299 300 if (mode == TX_INTF_BYPASS) { 301 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0x100); //slv_reg10[8] 302 } 303 304 printk("%s hw_init err %d\n", tx_intf_compatible_str, err); 305 return(err); 306 } 307 308 static int dev_probe(struct platform_device *pdev) 309 { 310 struct device_node *np = pdev->dev.of_node; 311 struct resource *io; 312 int err=1; 313 314 printk("\n"); 315 316 if (np) { 317 const struct of_device_id *match; 318 319 match = of_match_node(dev_of_ids, np); 320 if (match) { 321 printk("%s dev_probe match!\n", tx_intf_compatible_str); 322 err = 0; 323 } 324 } 325 326 if (err) 327 return err; 328 329 tx_intf_api->hw_init=hw_init; 330 331 tx_intf_api->reg_read=reg_read; 332 tx_intf_api->reg_write=reg_write; 333 334 tx_intf_api->TX_INTF_REG_MULTI_RST_read=TX_INTF_REG_MULTI_RST_read; 335 tx_intf_api->TX_INTF_REG_MIXER_CFG_read=TX_INTF_REG_MIXER_CFG_read; 336 tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_read=TX_INTF_REG_WIFI_TX_MODE_read; 337 tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_read=TX_INTF_REG_IQ_SRC_SEL_read; 338 tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_read=TX_INTF_REG_CTS_TOSELF_CONFIG_read; 339 tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_read=TX_INTF_REG_START_TRANS_TO_PS_MODE_read; 340 tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read; 341 tx_intf_api->TX_INTF_REG_MISC_SEL_read=TX_INTF_REG_MISC_SEL_read; 342 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read; 343 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read; 344 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_read=TX_INTF_REG_CFG_DATA_TO_ANT_read; 345 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_read=TX_INTF_REG_S_AXIS_FIFO_TH_read; 346 tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_read=TX_INTF_REG_TX_HOLD_THRESHOLD_read; 347 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_read=TX_INTF_REG_INTERRUPT_SEL_read; 348 tx_intf_api->TX_INTF_REG_BB_GAIN_read=TX_INTF_REG_BB_GAIN_read; 349 tx_intf_api->TX_INTF_REG_ANT_SEL_read=TX_INTF_REG_ANT_SEL_read; 350 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read=TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read; 351 tx_intf_api->TX_INTF_REG_PKT_INFO_read=TX_INTF_REG_PKT_INFO_read; 352 tx_intf_api->TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read=TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read; 353 354 tx_intf_api->TX_INTF_REG_MULTI_RST_write=TX_INTF_REG_MULTI_RST_write; 355 tx_intf_api->TX_INTF_REG_MIXER_CFG_write=TX_INTF_REG_MIXER_CFG_write; 356 tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write=TX_INTF_REG_WIFI_TX_MODE_write; 357 tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_write=TX_INTF_REG_IQ_SRC_SEL_write; 358 tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_write=TX_INTF_REG_CTS_TOSELF_CONFIG_write; 359 tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_write=TX_INTF_REG_START_TRANS_TO_PS_MODE_write; 360 tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write; 361 tx_intf_api->TX_INTF_REG_MISC_SEL_write=TX_INTF_REG_MISC_SEL_write; 362 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write; 363 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write; 364 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write=TX_INTF_REG_CFG_DATA_TO_ANT_write; 365 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write=TX_INTF_REG_S_AXIS_FIFO_TH_write; 366 tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_write=TX_INTF_REG_TX_HOLD_THRESHOLD_write; 367 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write=TX_INTF_REG_INTERRUPT_SEL_write; 368 tx_intf_api->TX_INTF_REG_BB_GAIN_write=TX_INTF_REG_BB_GAIN_write; 369 tx_intf_api->TX_INTF_REG_ANT_SEL_write=TX_INTF_REG_ANT_SEL_write; 370 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write=TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write; 371 tx_intf_api->TX_INTF_REG_PKT_INFO_write=TX_INTF_REG_PKT_INFO_write; 372 373 /* Request and map I/O memory */ 374 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 375 base_addr = devm_ioremap_resource(&pdev->dev, io); 376 if (IS_ERR(base_addr)) 377 return PTR_ERR(base_addr); 378 379 printk("%s dev_probe io start 0x%08llx end 0x%08llx name %s flags 0x%08x desc 0x%08x\n", tx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); 380 printk("%s dev_probe base_addr 0x%p\n", tx_intf_compatible_str,(void*)base_addr); 381 printk("%s dev_probe tx_intf_driver_api_inst 0x%p\n", tx_intf_compatible_str, (void*)(&tx_intf_driver_api_inst) ); 382 printk("%s dev_probe tx_intf_api 0x%p\n", tx_intf_compatible_str, (void*)tx_intf_api); 383 384 printk("%s dev_probe succeed!\n", tx_intf_compatible_str); 385 386 //err = hw_init(TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 8, 8, SMALL_FPGA); 387 //err = hw_init(TX_INTF_BYPASS, 8, 8, SMALL_FPGA); 388 err = hw_init(TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 8, 8, SMALL_FPGA); // make sure dac is connected to original ad9361 dma 389 390 return err; 391 } 392 393 static int dev_remove(struct platform_device *pdev) 394 { 395 printk("\n"); 396 397 printk("%s dev_remove base_addr 0x%p\n", tx_intf_compatible_str,(void*)base_addr); 398 printk("%s dev_remove tx_intf_driver_api_inst 0x%p\n", tx_intf_compatible_str, (void*)(&tx_intf_driver_api_inst) ); 399 printk("%s dev_remove tx_intf_api 0x%p\n", tx_intf_compatible_str, (void*)tx_intf_api); 400 401 printk("%s dev_remove succeed!\n", tx_intf_compatible_str); 402 return 0; 403 } 404 405 static struct platform_driver dev_driver = { 406 .driver = { 407 .name = "sdr,tx_intf", 408 .owner = THIS_MODULE, 409 .of_match_table = dev_of_ids, 410 }, 411 .probe = dev_probe, 412 .remove = dev_remove, 413 }; 414 415 module_platform_driver(dev_driver); 416 417 MODULE_AUTHOR("Xianjun Jiao"); 418 MODULE_DESCRIPTION("sdr,tx_intf"); 419 MODULE_LICENSE("GPL v2"); 420