1*22dd0cc4SXianjun Jiao // Xianjun jiao. [email protected]; [email protected] 2*22dd0cc4SXianjun Jiao 3*22dd0cc4SXianjun Jiao // ---------------------------------------side channel------------------------------- 4*22dd0cc4SXianjun Jiao const char *side_ch_compatible_str = "sdr,side_ch"; 5*22dd0cc4SXianjun Jiao 6*22dd0cc4SXianjun Jiao //align with side_ch_control.v and all related user space, remote files 7*22dd0cc4SXianjun Jiao #define CSI_LEN 56 // length of single CSI 8*22dd0cc4SXianjun Jiao #define EQUALIZER_LEN (56-4) // for non HT, four {32767,32767} will be padded to achieve 52 (non HT should have 48) 9*22dd0cc4SXianjun Jiao #define HEADER_LEN 2 //timestamp and frequency offset 10*22dd0cc4SXianjun Jiao 11*22dd0cc4SXianjun Jiao #define MAX_NUM_DMA_SYMBOL 4096 //align with side_ch.v side_ch.h 12*22dd0cc4SXianjun Jiao 13*22dd0cc4SXianjun Jiao #define SIDE_CH_REG_MULTI_RST_ADDR (0*4) 14*22dd0cc4SXianjun Jiao #define SIDE_CH_REG_CONFIG_ADDR (1*4) 15*22dd0cc4SXianjun Jiao #define SIDE_CH_REG_NUM_DMA_SYMBOL_ADDR (2*4) //low 16bit to PS; high 16bit to PL 16*22dd0cc4SXianjun Jiao #define SIDE_CH_REG_START_DMA_TO_PS_ADDR (3*4) 17*22dd0cc4SXianjun Jiao #define SIDE_CH_REG_NUM_EQ_ADDR (4*4) 18*22dd0cc4SXianjun Jiao #define SIDE_CH_REG_FC_TARGET_ADDR (5*4) 19*22dd0cc4SXianjun Jiao #define SIDE_CH_REG_ADDR1_TARGET_ADDR (6*4) 20*22dd0cc4SXianjun Jiao #define SIDE_CH_REG_ADDR2_TARGET_ADDR (7*4) 21*22dd0cc4SXianjun Jiao 22*22dd0cc4SXianjun Jiao #define SIDE_CH_REG_M_AXIS_DATA_COUNT_ADDR (20*4) 23