1*541ccd3cSJiao Xianjun // Author: Xianjun Jiao 2*541ccd3cSJiao Xianjun // SPDX-FileCopyrightText: 2019 UGent 3a6085186SLina Ceballos // SPDX-License-Identifier: AGPL-3.0-or-later 422dd0cc4SXianjun Jiao 522dd0cc4SXianjun Jiao // ---------------------------------------side channel------------------------------- 622dd0cc4SXianjun Jiao const char *side_ch_compatible_str = "sdr,side_ch"; 722dd0cc4SXianjun Jiao 822dd0cc4SXianjun Jiao //align with side_ch_control.v and all related user space, remote files 922dd0cc4SXianjun Jiao #define CSI_LEN 56 // length of single CSI 1022dd0cc4SXianjun Jiao #define EQUALIZER_LEN (56-4) // for non HT, four {32767,32767} will be padded to achieve 52 (non HT should have 48) 1122dd0cc4SXianjun Jiao #define HEADER_LEN 2 //timestamp and frequency offset 1222dd0cc4SXianjun Jiao 13f71252c5SXianjun Jiao #define MAX_NUM_DMA_SYMBOL 8192 //align with side_ch.v side_ch.h 1422dd0cc4SXianjun Jiao 1522dd0cc4SXianjun Jiao #define SIDE_CH_REG_MULTI_RST_ADDR (0*4) 1622dd0cc4SXianjun Jiao #define SIDE_CH_REG_CONFIG_ADDR (1*4) 1722dd0cc4SXianjun Jiao #define SIDE_CH_REG_NUM_DMA_SYMBOL_ADDR (2*4) //low 16bit to PS; high 16bit to PL 18f71252c5SXianjun Jiao #define SIDE_CH_REG_IQ_CAPTURE_ADDR (3*4) 1922dd0cc4SXianjun Jiao #define SIDE_CH_REG_NUM_EQ_ADDR (4*4) 2022dd0cc4SXianjun Jiao #define SIDE_CH_REG_FC_TARGET_ADDR (5*4) 2122dd0cc4SXianjun Jiao #define SIDE_CH_REG_ADDR1_TARGET_ADDR (6*4) 2222dd0cc4SXianjun Jiao #define SIDE_CH_REG_ADDR2_TARGET_ADDR (7*4) 23f71252c5SXianjun Jiao #define SIDE_CH_REG_IQ_TRIGGER_ADDR (8*4) 24f71252c5SXianjun Jiao #define SIDE_CH_REG_RSSI_TH_ADDR (9*4) 25f71252c5SXianjun Jiao #define SIDE_CH_REG_GAIN_TH_ADDR (10*4) 26f71252c5SXianjun Jiao #define SIDE_CH_REG_PRE_TRIGGER_LEN_ADDR (11*4) 27f71252c5SXianjun Jiao #define SIDE_CH_REG_IQ_LEN_ADDR (12*4) 2822dd0cc4SXianjun Jiao 2922dd0cc4SXianjun Jiao #define SIDE_CH_REG_M_AXIS_DATA_COUNT_ADDR (20*4) 30