1d8d76f88SJiao Xianjun // Author: Xianjun Jiao, Michael Mehari, Wei Liu 2d8d76f88SJiao Xianjun // SPDX-FileCopyrightText: 2019 UGent 3a6085186SLina Ceballos // SPDX-License-Identifier: AGPL-3.0-or-later 42ee67178SXianjun Jiao 52ee67178SXianjun Jiao #ifndef OPENWIFI_SDR 62ee67178SXianjun Jiao #define OPENWIFI_SDR 72ee67178SXianjun Jiao 8109b1cfdSXianjun Jiao #include "pre_def.h" 9109b1cfdSXianjun Jiao 102ee67178SXianjun Jiao // -------------------for leds-------------------------------- 11b1dd94e3Sluz paz struct gpio_led_data { //please always align with the leds-gpio.c in linux kernel 122ee67178SXianjun Jiao struct led_classdev cdev; 132ee67178SXianjun Jiao struct gpio_desc *gpiod; 142ee67178SXianjun Jiao u8 can_sleep; 152ee67178SXianjun Jiao u8 blinking; 162ee67178SXianjun Jiao gpio_blink_set_t platform_gpio_blink_set; 172ee67178SXianjun Jiao }; 182ee67178SXianjun Jiao 19b1dd94e3Sluz paz struct gpio_leds_priv { //please always align with the leds-gpio.c in linux kernel 202ee67178SXianjun Jiao int num_leds; 212ee67178SXianjun Jiao struct gpio_led_data leds[]; 222ee67178SXianjun Jiao }; 232ee67178SXianjun Jiao 242ee67178SXianjun Jiao struct openwifi_rf_ops { 252ee67178SXianjun Jiao char *name; 262ee67178SXianjun Jiao // void (*init)(struct ieee80211_hw *); 272ee67178SXianjun Jiao // void (*stop)(struct ieee80211_hw *); 282ee67178SXianjun Jiao void (*set_chan)(struct ieee80211_hw *, struct ieee80211_conf *); 292ee67178SXianjun Jiao // u8 (*calc_rssi)(u8 agc, u8 sq); 302ee67178SXianjun Jiao }; 312ee67178SXianjun Jiao 322ee67178SXianjun Jiao struct openwifi_buffer_descriptor { 33838a9007SXianjun Jiao // u32 num_dma_byte; 34838a9007SXianjun Jiao // u32 sn; 35838a9007SXianjun Jiao // u32 hw_queue_idx; 36838a9007SXianjun Jiao // u32 retry_limit; 37838a9007SXianjun Jiao // u32 need_ack; 38947b9345SXianjun Jiao u8 prio; 39947b9345SXianjun Jiao u16 len_mpdu; 40f738aefaSmmehari u16 seq_no; 412ee67178SXianjun Jiao struct sk_buff *skb_linked; 422ee67178SXianjun Jiao dma_addr_t dma_mapping_addr; 43838a9007SXianjun Jiao // u32 reserved; 442ee67178SXianjun Jiao } __packed; 452ee67178SXianjun Jiao 462ee67178SXianjun Jiao struct openwifi_ring { 472ee67178SXianjun Jiao struct openwifi_buffer_descriptor *bds; 482ee67178SXianjun Jiao u32 bd_wr_idx; 492ee67178SXianjun Jiao u32 bd_rd_idx; 50947b9345SXianjun Jiao int stop_flag; // -1: normal run; X>=0: stop due to queueX full 51838a9007SXianjun Jiao // u32 num_dma_symbol_request; 52838a9007SXianjun Jiao // u32 reserved; 532ee67178SXianjun Jiao } __packed; 542ee67178SXianjun Jiao 552ee67178SXianjun Jiao struct openwifi_vif { 562ee67178SXianjun Jiao struct ieee80211_hw *dev; 572ee67178SXianjun Jiao 582ee67178SXianjun Jiao int idx; // this vif's idx on the dev 592ee67178SXianjun Jiao 602ee67178SXianjun Jiao /* beaconing */ 612ee67178SXianjun Jiao struct delayed_work beacon_work; 622ee67178SXianjun Jiao bool enable_beacon; 632ee67178SXianjun Jiao }; 642ee67178SXianjun Jiao 652ee67178SXianjun Jiao union u32_byte4 { 662ee67178SXianjun Jiao u32 a; 672ee67178SXianjun Jiao u8 c[4]; 682ee67178SXianjun Jiao }; 692ee67178SXianjun Jiao union u16_byte2 { 702ee67178SXianjun Jiao u16 a; 712ee67178SXianjun Jiao u8 c[2]; 722ee67178SXianjun Jiao }; 732ee67178SXianjun Jiao 742ee67178SXianjun Jiao #define MAX_NUM_LED 4 752ee67178SXianjun Jiao #define OPENWIFI_LED_MAX_NAME_LEN 32 762ee67178SXianjun Jiao 7756203843SXianjun Jiao #define NUM_TX_ANT_MASK 3 7856203843SXianjun Jiao #define NUM_RX_ANT_MASK 3 7956203843SXianjun Jiao 80d3ce582aSXianjun Jiao // -------------sdrctl reg category----------------- 81d3ce582aSXianjun Jiao enum sdrctl_reg_cat { 82d3ce582aSXianjun Jiao SDRCTL_REG_CAT_NO_USE = 0, 83d3ce582aSXianjun Jiao SDRCTL_REG_CAT_RF, 84d3ce582aSXianjun Jiao SDRCTL_REG_CAT_RX_INTF, 85d3ce582aSXianjun Jiao SDRCTL_REG_CAT_TX_INTF, 86d3ce582aSXianjun Jiao SDRCTL_REG_CAT_RX, 87d3ce582aSXianjun Jiao SDRCTL_REG_CAT_TX, 88d3ce582aSXianjun Jiao SDRCTL_REG_CAT_XPU, 89d3ce582aSXianjun Jiao SDRCTL_REG_CAT_DRV_RX, 90d3ce582aSXianjun Jiao SDRCTL_REG_CAT_DRV_TX, 91d3ce582aSXianjun Jiao SDRCTL_REG_CAT_DRV_XPU, 92d3ce582aSXianjun Jiao }; 93d3ce582aSXianjun Jiao 9411d048d9SXianjun Jiao // ------------ software and RF reg definition ------------ 95838a9007SXianjun Jiao #define MAX_NUM_DRV_REG 8 96838a9007SXianjun Jiao #define DRV_TX_REG_IDX_RATE 0 9711d048d9SXianjun Jiao #define DRV_TX_REG_IDX_RATE_HT 1 9811d048d9SXianjun Jiao #define DRV_TX_REG_IDX_RATE_VHT 2 9911d048d9SXianjun Jiao #define DRV_TX_REG_IDX_RATE_HE 3 10011d048d9SXianjun Jiao #define DRV_TX_REG_IDX_ANT_CFG 4 101838a9007SXianjun Jiao #define DRV_TX_REG_IDX_PRINT_CFG (MAX_NUM_DRV_REG-1) 102838a9007SXianjun Jiao 10311d048d9SXianjun Jiao #define DRV_RX_REG_IDX_DEMOD_TH 0 10411d048d9SXianjun Jiao #define DRV_RX_REG_IDX_ANT_CFG 4 105838a9007SXianjun Jiao #define DRV_RX_REG_IDX_PRINT_CFG (MAX_NUM_DRV_REG-1) 106838a9007SXianjun Jiao 1078598d294SXianjun Jiao #define DRV_XPU_REG_IDX_LBT_TH 0 1080a92505dSXianjun Jiao #define DRV_XPU_REG_IDX_GIT_REV (MAX_NUM_DRV_REG-1) 1090a92505dSXianjun Jiao 11011d048d9SXianjun Jiao #define MAX_NUM_RF_REG 8 11111d048d9SXianjun Jiao #define RF_TX_REG_IDX_ATT 0 112d6c1c3f7SXianjun Jiao #define RF_TX_REG_IDX_FREQ_MHZ 1 11311d048d9SXianjun Jiao #define RF_RX_REG_IDX_GAIN 4 114d6c1c3f7SXianjun Jiao #define RF_RX_REG_IDX_FREQ_MHZ 5 11511d048d9SXianjun Jiao // ------end of software and RF reg definition ------------ 116838a9007SXianjun Jiao 117088d2d18SXianjun Jiao // -------------dmesg printk control flag------------------ 118088d2d18SXianjun Jiao #define DMESG_LOG_ERROR (1<<0) 119088d2d18SXianjun Jiao #define DMESG_LOG_UNICAST (1<<1) 120088d2d18SXianjun Jiao #define DMESG_LOG_BROADCAST (1<<2) 121088d2d18SXianjun Jiao #define DMESG_LOG_NORMAL_QUEUE_STOP (1<<3) 122088d2d18SXianjun Jiao #define DMESG_LOG_ANY (0xF) 123088d2d18SXianjun Jiao // ------end of dmesg printk control flag------------------ 124088d2d18SXianjun Jiao 1252ee67178SXianjun Jiao #define MAX_NUM_VIF 4 1262ee67178SXianjun Jiao 1272ee67178SXianjun Jiao #define LEN_PHY_CRC 4 128f738aefaSmmehari #define LEN_MPDU_DELIM 4 1292ee67178SXianjun Jiao 130*342bd25aSXianjun Jiao #define MAX_NUM_HW_QUEUE 4 // number of queue in FPGA 131*342bd25aSXianjun Jiao #define MAX_NUM_SW_QUEUE 4 // number of queue in Linux, depends on the number we report by dev->queues in openwifi_dev_probe 132*342bd25aSXianjun Jiao 133*342bd25aSXianjun Jiao #define RING_ROOM_THRESHOLD (2+MAX_NUM_SW_QUEUE) // MAX_NUM_SW_QUEUE is for the room of MAX_NUM_SW_QUEUE last packets from MAX_NUM_SW_QUEUE queue before stop 134f738aefaSmmehari #define NUM_BIT_NUM_TX_BD 6 135f738aefaSmmehari #define NUM_TX_BD (1<<NUM_BIT_NUM_TX_BD) // !!! should align to the fifo size in tx_bit_intf.v 136109b1cfdSXianjun Jiao 137109b1cfdSXianjun Jiao #ifdef USE_NEW_RX_INTERRUPT 138d4661bbdSXianjun Jiao #define NUM_RX_BD 64 139109b1cfdSXianjun Jiao #else 1402ee67178SXianjun Jiao #define NUM_RX_BD 16 141109b1cfdSXianjun Jiao #endif 142109b1cfdSXianjun Jiao 1432ee67178SXianjun Jiao #define TX_BD_BUF_SIZE (8192) 144d4661bbdSXianjun Jiao #define RX_BD_BUF_SIZE (2048) 1452ee67178SXianjun Jiao 1462ee67178SXianjun Jiao #define NUM_BIT_MAX_NUM_HW_QUEUE 2 147838a9007SXianjun Jiao #define NUM_BIT_MAX_PHY_TX_SN 10 // decrease 12 to 10 to reserve 2 bits storing related linux prio idx 1482ee67178SXianjun Jiao #define MAX_PHY_TX_SN ((1<<NUM_BIT_MAX_PHY_TX_SN)-1) 1492ee67178SXianjun Jiao 1502ee67178SXianjun Jiao #define AD9361_RADIO_OFF_TX_ATT 89750 //please align with ad9361.c 1512ee67178SXianjun Jiao #define AD9361_RADIO_ON_TX_ATT 000 //please align with rf_init.sh 15256203843SXianjun Jiao #define AD9361_CTRL_OUT_EN_MASK (0xFF) 15356203843SXianjun Jiao #define AD9361_CTRL_OUT_INDEX_ANT0 (0x16) 15456203843SXianjun Jiao #define AD9361_CTRL_OUT_INDEX_ANT1 (0x17) 1552ee67178SXianjun Jiao 1562ee67178SXianjun Jiao #define SDR_SUPPORTED_FILTERS \ 1572ee67178SXianjun Jiao (FIF_ALLMULTI | \ 1582ee67178SXianjun Jiao FIF_BCN_PRBRESP_PROMISC | \ 1592ee67178SXianjun Jiao FIF_CONTROL | \ 1602ee67178SXianjun Jiao FIF_OTHER_BSS | \ 1612ee67178SXianjun Jiao FIF_PSPOLL | \ 1622ee67178SXianjun Jiao FIF_PROBE_REQ) 1632ee67178SXianjun Jiao 1642ee67178SXianjun Jiao #define HIGH_PRIORITY_DISCARD_FLAG ((~0x040)<<16) // don't force drop OTHER_BSS by high priority discard 1652ee67178SXianjun Jiao //#define HIGH_PRIORITY_DISCARD_FLAG ((~0x140)<<16) // don't force drop OTHER_BSS and PROB_REQ by high priority discard 1662ee67178SXianjun Jiao 1672ee67178SXianjun Jiao /* 5G chan 36 - chan 64*/ 1680b4b8cc7SXianjun Jiao #define SDR_5GHZ_CH36_64 REG_RULE(5150-10, 5350+10, 80, 0, 20, 0) 1690b4b8cc7SXianjun Jiao /* 5G chan 32 - chan 173*/ 1700b4b8cc7SXianjun Jiao #define SDR_5GHZ_CH32_173 REG_RULE(5160-10, 5865+10, 80, 0, 20, 0) 1712ee67178SXianjun Jiao /* 5G chan 36 - chan 48*/ 1720b4b8cc7SXianjun Jiao #define SDR_5GHZ_CH36_48 REG_RULE(5150-10, 5270+10, 80, 0, 20, 0) 1732ee67178SXianjun Jiao 1742ee67178SXianjun Jiao /* 1752ee67178SXianjun Jiao *Only these channels all allow active 1762ee67178SXianjun Jiao *scan on all world regulatory domains 1772ee67178SXianjun Jiao */ 1782ee67178SXianjun Jiao #define SDR_2GHZ_CH01_13 REG_RULE(2412-10, 2472+10, 40, 0, 20, NL80211_RRF_NO_CCK) // disable 11b 1792ee67178SXianjun Jiao #define SDR_2GHZ_CH01_14 REG_RULE(2412-10, 2484+10, 40, 0, 20, NL80211_RRF_NO_CCK) // disable 11b 1802ee67178SXianjun Jiao 1812ee67178SXianjun Jiao // regulatory.h alpha2 1822ee67178SXianjun Jiao // * 00 - World regulatory domain 1832ee67178SXianjun Jiao // * 99 - built by driver but a specific alpha2 cannot be determined 1842ee67178SXianjun Jiao // * 98 - result of an intersection between two regulatory domains 1852ee67178SXianjun Jiao // * 97 - regulatory domain has not yet been configured 1862ee67178SXianjun Jiao static const struct ieee80211_regdomain sdr_regd = { // for wiphy_apply_custom_regulatory 1872ee67178SXianjun Jiao .n_reg_rules = 2, 1882ee67178SXianjun Jiao .alpha2 = "99", 1892ee67178SXianjun Jiao .dfs_region = NL80211_DFS_ETSI, 1902ee67178SXianjun Jiao .reg_rules = { 1912ee67178SXianjun Jiao //SDR_2GHZ_CH01_13, 1922ee67178SXianjun Jiao //SDR_5GHZ_CH36_48, //Avoid radar! 1932ee67178SXianjun Jiao SDR_2GHZ_CH01_14, 1940b4b8cc7SXianjun Jiao // SDR_5GHZ_CH36_64, 1950b4b8cc7SXianjun Jiao SDR_5GHZ_CH32_173, 1962ee67178SXianjun Jiao } 1972ee67178SXianjun Jiao }; 1982ee67178SXianjun Jiao 1992ee67178SXianjun Jiao #define CHAN2G(_channel, _freq, _flags) { \ 2002ee67178SXianjun Jiao .band = NL80211_BAND_2GHZ, \ 2012ee67178SXianjun Jiao .hw_value = (_channel), \ 2022ee67178SXianjun Jiao .center_freq = (_freq), \ 2032ee67178SXianjun Jiao .flags = (_flags), \ 2042ee67178SXianjun Jiao .max_antenna_gain = 0, \ 2052ee67178SXianjun Jiao .max_power = 0, \ 2062ee67178SXianjun Jiao } 2072ee67178SXianjun Jiao 2082ee67178SXianjun Jiao #define CHAN5G(_channel, _freq, _flags) { \ 2092ee67178SXianjun Jiao .band = NL80211_BAND_5GHZ, \ 2102ee67178SXianjun Jiao .hw_value = (_channel), \ 2112ee67178SXianjun Jiao .center_freq = (_freq), \ 2122ee67178SXianjun Jiao .flags = (_flags), \ 2132ee67178SXianjun Jiao .max_antenna_gain = 0, \ 2142ee67178SXianjun Jiao .max_power = 0, \ 2152ee67178SXianjun Jiao } 2162ee67178SXianjun Jiao 2172ee67178SXianjun Jiao static const struct ieee80211_rate openwifi_5GHz_rates[] = { 2182ee67178SXianjun Jiao { .bitrate = 10, .hw_value = 0, .flags = 0}, 2192ee67178SXianjun Jiao { .bitrate = 20, .hw_value = 1, .flags = 0}, 2202ee67178SXianjun Jiao { .bitrate = 55, .hw_value = 2, .flags = 0}, 2212ee67178SXianjun Jiao { .bitrate = 110, .hw_value = 3, .flags = 0}, 2222ee67178SXianjun Jiao { .bitrate = 60, .hw_value = 4, .flags = IEEE80211_RATE_MANDATORY_A}, 2232ee67178SXianjun Jiao { .bitrate = 90, .hw_value = 5, .flags = IEEE80211_RATE_MANDATORY_A}, 2242ee67178SXianjun Jiao { .bitrate = 120, .hw_value = 6, .flags = IEEE80211_RATE_MANDATORY_A}, 2252ee67178SXianjun Jiao { .bitrate = 180, .hw_value = 7, .flags = IEEE80211_RATE_MANDATORY_A}, 2262ee67178SXianjun Jiao { .bitrate = 240, .hw_value = 8, .flags = IEEE80211_RATE_MANDATORY_A}, 2272ee67178SXianjun Jiao { .bitrate = 360, .hw_value = 9, .flags = IEEE80211_RATE_MANDATORY_A}, 2282ee67178SXianjun Jiao { .bitrate = 480, .hw_value = 10, .flags = IEEE80211_RATE_MANDATORY_A}, 2292ee67178SXianjun Jiao { .bitrate = 540, .hw_value = 11, .flags = IEEE80211_RATE_MANDATORY_A}, 2302ee67178SXianjun Jiao }; 2312ee67178SXianjun Jiao 2322ee67178SXianjun Jiao static const struct ieee80211_rate openwifi_2GHz_rates[] = { 2332ee67178SXianjun Jiao { .bitrate = 10, .hw_value = 0, .flags = 0}, 2342ee67178SXianjun Jiao { .bitrate = 20, .hw_value = 1, .flags = 0}, 2352ee67178SXianjun Jiao { .bitrate = 55, .hw_value = 2, .flags = 0}, 2362ee67178SXianjun Jiao { .bitrate = 110, .hw_value = 3, .flags = 0}, 2372ee67178SXianjun Jiao { .bitrate = 60, .hw_value = 4, .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G}, 2382ee67178SXianjun Jiao { .bitrate = 90, .hw_value = 5, .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G}, 2392ee67178SXianjun Jiao { .bitrate = 120, .hw_value = 6, .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G}, 2402ee67178SXianjun Jiao { .bitrate = 180, .hw_value = 7, .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G}, 2412ee67178SXianjun Jiao { .bitrate = 240, .hw_value = 8, .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G}, 2422ee67178SXianjun Jiao { .bitrate = 360, .hw_value = 9, .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G}, 2432ee67178SXianjun Jiao { .bitrate = 480, .hw_value = 10, .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G}, 2442ee67178SXianjun Jiao { .bitrate = 540, .hw_value = 11, .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G}, 2452ee67178SXianjun Jiao }; 2462ee67178SXianjun Jiao 2472ee67178SXianjun Jiao static const struct ieee80211_channel openwifi_2GHz_channels[] = { 2482ee67178SXianjun Jiao CHAN2G(1, 2412, 0), 2492ee67178SXianjun Jiao CHAN2G(2, 2417, 0), 2502ee67178SXianjun Jiao CHAN2G(3, 2422, 0), 2512ee67178SXianjun Jiao CHAN2G(4, 2427, 0), 2522ee67178SXianjun Jiao CHAN2G(5, 2432, 0), 2532ee67178SXianjun Jiao CHAN2G(6, 2437, 0), 2542ee67178SXianjun Jiao CHAN2G(7, 2442, 0), 2552ee67178SXianjun Jiao CHAN2G(8, 2447, 0), 2562ee67178SXianjun Jiao CHAN2G(9, 2452, 0), 2572ee67178SXianjun Jiao CHAN2G(10, 2457, 0), 2582ee67178SXianjun Jiao CHAN2G(11, 2462, 0), 2592ee67178SXianjun Jiao CHAN2G(12, 2467, 0), 2602ee67178SXianjun Jiao CHAN2G(13, 2472, 0), 2611895c3aeSXianjun Jiao // CHAN2G(14, 2484, 0), 2622ee67178SXianjun Jiao }; 2632ee67178SXianjun Jiao 2642ee67178SXianjun Jiao static const struct ieee80211_channel openwifi_5GHz_channels[] = { 2651895c3aeSXianjun Jiao // CHAN5G(32, 5160, 0), 2661895c3aeSXianjun Jiao // CHAN5G(34, 5170, 0), 2672ee67178SXianjun Jiao CHAN5G(36, 5180, 0), 2682ee67178SXianjun Jiao CHAN5G(38, 5190, 0), 2692ee67178SXianjun Jiao CHAN5G(40, 5200, 0), 2702ee67178SXianjun Jiao CHAN5G(42, 5210, 0), 2712ee67178SXianjun Jiao CHAN5G(44, 5220, 0), 2722ee67178SXianjun Jiao CHAN5G(46, 5230, 0), 2732ee67178SXianjun Jiao CHAN5G(48, 5240, 0), 2741895c3aeSXianjun Jiao // CHAN5G( 50, 5250, IEEE80211_CHAN_RADAR), 2752ee67178SXianjun Jiao CHAN5G( 52, 5260, IEEE80211_CHAN_RADAR), 2761895c3aeSXianjun Jiao // CHAN5G( 54, 5270, IEEE80211_CHAN_RADAR), 2772ee67178SXianjun Jiao CHAN5G( 56, 5280, IEEE80211_CHAN_RADAR), 2781895c3aeSXianjun Jiao // CHAN5G( 58, 5290, IEEE80211_CHAN_RADAR), 2792ee67178SXianjun Jiao CHAN5G( 60, 5300, IEEE80211_CHAN_RADAR), 2801895c3aeSXianjun Jiao // CHAN5G( 62, 5310, IEEE80211_CHAN_RADAR), 2812ee67178SXianjun Jiao CHAN5G( 64, 5320, IEEE80211_CHAN_RADAR), 2821895c3aeSXianjun Jiao // CHAN5G( 68, 5340, IEEE80211_CHAN_RADAR), 2831895c3aeSXianjun Jiao // CHAN5G( 96, 5480, IEEE80211_CHAN_RADAR), 2841895c3aeSXianjun Jiao // CHAN5G(100, 5500, IEEE80211_CHAN_RADAR), 2851895c3aeSXianjun Jiao // CHAN5G(102, 5510, IEEE80211_CHAN_RADAR), 2861895c3aeSXianjun Jiao // CHAN5G(104, 5520, IEEE80211_CHAN_RADAR), 2871895c3aeSXianjun Jiao // CHAN5G(106, 5530, IEEE80211_CHAN_RADAR), 2881895c3aeSXianjun Jiao // CHAN5G(108, 5540, IEEE80211_CHAN_RADAR), 2891895c3aeSXianjun Jiao // CHAN5G(110, 5550, IEEE80211_CHAN_RADAR), 2901895c3aeSXianjun Jiao // CHAN5G(112, 5560, IEEE80211_CHAN_RADAR), 2911895c3aeSXianjun Jiao // CHAN5G(114, 5570, IEEE80211_CHAN_RADAR), 2921895c3aeSXianjun Jiao // CHAN5G(116, 5580, IEEE80211_CHAN_RADAR), 2931895c3aeSXianjun Jiao // CHAN5G(118, 5590, IEEE80211_CHAN_RADAR), 2941895c3aeSXianjun Jiao // CHAN5G(120, 5600, IEEE80211_CHAN_RADAR), 2951895c3aeSXianjun Jiao // CHAN5G(122, 5610, IEEE80211_CHAN_RADAR), 2961895c3aeSXianjun Jiao // CHAN5G(124, 5620, IEEE80211_CHAN_RADAR), 2971895c3aeSXianjun Jiao // CHAN5G(126, 5630, IEEE80211_CHAN_RADAR), 2981895c3aeSXianjun Jiao // CHAN5G(128, 5640, IEEE80211_CHAN_RADAR), 2991895c3aeSXianjun Jiao // CHAN5G(132, 5660, IEEE80211_CHAN_RADAR), 3001895c3aeSXianjun Jiao // CHAN5G(134, 5670, IEEE80211_CHAN_RADAR), 3011895c3aeSXianjun Jiao // CHAN5G(136, 5680, IEEE80211_CHAN_RADAR), 3021895c3aeSXianjun Jiao // CHAN5G(138, 5690, IEEE80211_CHAN_RADAR), 3031895c3aeSXianjun Jiao // CHAN5G(140, 5700, IEEE80211_CHAN_RADAR), 3041895c3aeSXianjun Jiao // CHAN5G(142, 5710, IEEE80211_CHAN_RADAR), 3051895c3aeSXianjun Jiao // CHAN5G(144, 5720, IEEE80211_CHAN_RADAR), 3061895c3aeSXianjun Jiao // CHAN5G(149, 5745, IEEE80211_CHAN_RADAR), 3071895c3aeSXianjun Jiao // CHAN5G(151, 5755, IEEE80211_CHAN_RADAR), 3081895c3aeSXianjun Jiao // CHAN5G(153, 5765, IEEE80211_CHAN_RADAR), 3091895c3aeSXianjun Jiao // CHAN5G(155, 5775, IEEE80211_CHAN_RADAR), 3101895c3aeSXianjun Jiao // CHAN5G(157, 5785, IEEE80211_CHAN_RADAR), 3111895c3aeSXianjun Jiao // CHAN5G(159, 5795, IEEE80211_CHAN_RADAR), 3121895c3aeSXianjun Jiao // CHAN5G(161, 5805, IEEE80211_CHAN_RADAR), 3131895c3aeSXianjun Jiao // // CHAN5G(163, 5815, IEEE80211_CHAN_RADAR), 3141895c3aeSXianjun Jiao // CHAN5G(165, 5825, IEEE80211_CHAN_RADAR), 3151895c3aeSXianjun Jiao // CHAN5G(167, 5835, IEEE80211_CHAN_RADAR), 3161895c3aeSXianjun Jiao // CHAN5G(169, 5845, IEEE80211_CHAN_RADAR), 3171895c3aeSXianjun Jiao // CHAN5G(171, 5855, IEEE80211_CHAN_RADAR), 3181895c3aeSXianjun Jiao // CHAN5G(173, 5865, IEEE80211_CHAN_RADAR), 3192ee67178SXianjun Jiao }; 3202ee67178SXianjun Jiao 3212ee67178SXianjun Jiao static const struct ieee80211_iface_limit openwifi_if_limits[] = { 3226a9949eeSXianjun Jiao { .max = MAX_NUM_VIF, .types = BIT(NL80211_IFTYPE_STATION) }, 3236a9949eeSXianjun Jiao { .max = MAX_NUM_VIF, .types = 3242ee67178SXianjun Jiao #ifdef CONFIG_MAC80211_MESH 3252ee67178SXianjun Jiao BIT(NL80211_IFTYPE_MESH_POINT) | 3262ee67178SXianjun Jiao #endif 3272ee67178SXianjun Jiao BIT(NL80211_IFTYPE_AP)}, 3282ee67178SXianjun Jiao }; 3292ee67178SXianjun Jiao 3302ee67178SXianjun Jiao static const struct ieee80211_iface_combination openwifi_if_comb = { 3312ee67178SXianjun Jiao .limits = openwifi_if_limits, 3322ee67178SXianjun Jiao .n_limits = ARRAY_SIZE(openwifi_if_limits), 3336a9949eeSXianjun Jiao .max_interfaces = MAX_NUM_VIF, 3342ee67178SXianjun Jiao .num_different_channels = 1, 3352ee67178SXianjun Jiao .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 3362ee67178SXianjun Jiao BIT(NL80211_CHAN_WIDTH_20) | 3372ee67178SXianjun Jiao BIT(NL80211_CHAN_WIDTH_40) | 3382ee67178SXianjun Jiao BIT(NL80211_CHAN_WIDTH_80), 3392ee67178SXianjun Jiao }; 3402ee67178SXianjun Jiao 341b6d71713Smmehari static const u8 wifi_rate_table_mapping[24] = { 0, 0, 0, 0, 0, 0, 0, 0, 10, 8, 6, 4, 11, 9, 7, 5, 0, 1, 2, 3, 4, 5, 6, 7}; 342b6d71713Smmehari static const u16 wifi_rate_table[24] = { 0, 0, 0, 0, 0, 0, 0, 0, 480, 240, 120, 60, 540, 360, 180, 90, 65, 130, 195, 260, 390, 520, 585, 650}; 343b6d71713Smmehari static const u16 wifi_rate_all[20] = {10, 20, 55, 110, 60, 90, 120, 180, 240, 360, 480, 540, 65, 130, 195, 260, 390, 520, 585, 650}; 3442ee67178SXianjun Jiao static const u8 wifi_mcs_table_11b_force_up[16] = {11, 11, 11, 11, 11, 15, 10, 14, 9, 13, 8, 12, 0, 0, 0, 0}; 3452ee67178SXianjun Jiao static const u16 wifi_n_dbps_table[16] = {24, 24, 24, 24, 24, 36, 48, 72, 96, 144, 192, 216, 0, 0, 0, 0}; 346b6d71713Smmehari static const u16 wifi_n_dbps_ht_table[16] = {26, 26, 26, 26, 26, 52, 78, 104, 156, 208, 234, 260, 0, 0, 0, 0}; 3472ee67178SXianjun Jiao // static const u8 wifi_mcs_table[8] = {6,9,12,18,24,36,48,54}; 3482ee67178SXianjun Jiao // static const u8 wifi_mcs_table_phy_tx[8] = {11,15,10,14,9,13,8,12}; 3492ee67178SXianjun Jiao 350febc5adfSXianjun Jiao // ===== copy from adi-linux/drivers/iio/frequency/cf_axi_dds.c ===== 351febc5adfSXianjun Jiao struct cf_axi_dds_state { 352febc5adfSXianjun Jiao struct device *dev_spi; 353febc5adfSXianjun Jiao struct clk *clk; 354febc5adfSXianjun Jiao struct cf_axi_dds_chip_info *chip_info; 355febc5adfSXianjun Jiao struct gpio_desc *plddrbypass_gpio; 356febc5adfSXianjun Jiao struct gpio_desc *interpolation_gpio; 357febc5adfSXianjun Jiao 358febc5adfSXianjun Jiao bool standalone; 359febc5adfSXianjun Jiao bool dp_disable; 360febc5adfSXianjun Jiao bool enable; 361febc5adfSXianjun Jiao bool pl_dma_fifo_en; 362febc5adfSXianjun Jiao enum fifo_ctrl gpio_dma_fifo_ctrl; 363febc5adfSXianjun Jiao 364febc5adfSXianjun Jiao struct iio_info iio_info; 365febc5adfSXianjun Jiao size_t regs_size; 366febc5adfSXianjun Jiao void __iomem *regs; 367febc5adfSXianjun Jiao void __iomem *slave_regs; 368febc5adfSXianjun Jiao void __iomem *master_regs; 369febc5adfSXianjun Jiao u64 dac_clk; 370febc5adfSXianjun Jiao unsigned int ddr_dds_interp_en; 371febc5adfSXianjun Jiao unsigned int cached_freq[16]; 372febc5adfSXianjun Jiao unsigned int version; 373febc5adfSXianjun Jiao unsigned int have_slave_channels; 374febc5adfSXianjun Jiao unsigned int interpolation_factor; 375febc5adfSXianjun Jiao struct notifier_block clk_nb; 376febc5adfSXianjun Jiao }; 377febc5adfSXianjun Jiao // ===== end of copy from adi-linux/drivers/iio/frequency/cf_axi_dds.c ===== 378febc5adfSXianjun Jiao 379e4d5d1a3SXianjun Jiao struct openwifi_stat { 380e4d5d1a3SXianjun Jiao u32 stat_enable; 381e4d5d1a3SXianjun Jiao 382e4d5d1a3SXianjun Jiao u32 tx_prio_num[MAX_NUM_SW_QUEUE]; 383e4d5d1a3SXianjun Jiao u32 tx_prio_interrupt_num[MAX_NUM_SW_QUEUE]; 384e4d5d1a3SXianjun Jiao u32 tx_prio_stop0_fake_num[MAX_NUM_SW_QUEUE]; 385e4d5d1a3SXianjun Jiao u32 tx_prio_stop0_real_num[MAX_NUM_SW_QUEUE]; 386e4d5d1a3SXianjun Jiao u32 tx_prio_stop1_num[MAX_NUM_SW_QUEUE]; 387e4d5d1a3SXianjun Jiao u32 tx_prio_wakeup_num[MAX_NUM_SW_QUEUE]; 388e4d5d1a3SXianjun Jiao 389e4d5d1a3SXianjun Jiao u32 tx_queue_num[MAX_NUM_HW_QUEUE]; 390e4d5d1a3SXianjun Jiao u32 tx_queue_interrupt_num[MAX_NUM_HW_QUEUE]; 391e4d5d1a3SXianjun Jiao u32 tx_queue_stop0_fake_num[MAX_NUM_HW_QUEUE]; 392e4d5d1a3SXianjun Jiao u32 tx_queue_stop0_real_num[MAX_NUM_HW_QUEUE]; 393e4d5d1a3SXianjun Jiao u32 tx_queue_stop1_num[MAX_NUM_HW_QUEUE]; 394e4d5d1a3SXianjun Jiao u32 tx_queue_wakeup_num[MAX_NUM_HW_QUEUE]; 395e4d5d1a3SXianjun Jiao 396e4d5d1a3SXianjun Jiao u32 tx_data_pkt_need_ack_num_total; 397e4d5d1a3SXianjun Jiao u32 tx_data_pkt_need_ack_num_total_fail; 398e4d5d1a3SXianjun Jiao 399e4d5d1a3SXianjun Jiao u32 tx_data_pkt_need_ack_num_retx[6]; 400e4d5d1a3SXianjun Jiao u32 tx_data_pkt_need_ack_num_retx_fail[6]; 401e4d5d1a3SXianjun Jiao 402e4d5d1a3SXianjun Jiao u32 tx_data_pkt_mcs_realtime; 403e4d5d1a3SXianjun Jiao u32 tx_data_pkt_fail_mcs_realtime; 404e4d5d1a3SXianjun Jiao 405e4d5d1a3SXianjun Jiao u32 tx_mgmt_pkt_need_ack_num_total; 406e4d5d1a3SXianjun Jiao u32 tx_mgmt_pkt_need_ack_num_total_fail; 407e4d5d1a3SXianjun Jiao 408e4d5d1a3SXianjun Jiao u32 tx_mgmt_pkt_need_ack_num_retx[3]; 409e4d5d1a3SXianjun Jiao u32 tx_mgmt_pkt_need_ack_num_retx_fail[3]; 410e4d5d1a3SXianjun Jiao 411e4d5d1a3SXianjun Jiao u32 tx_mgmt_pkt_mcs_realtime; 412e4d5d1a3SXianjun Jiao u32 tx_mgmt_pkt_fail_mcs_realtime; 413e4d5d1a3SXianjun Jiao 414e4d5d1a3SXianjun Jiao u32 rx_target_sender_mac_addr; 415e4d5d1a3SXianjun Jiao u32 rx_data_ok_agc_gain_value_realtime; 416e4d5d1a3SXianjun Jiao u32 rx_data_fail_agc_gain_value_realtime; 417e4d5d1a3SXianjun Jiao u32 rx_mgmt_ok_agc_gain_value_realtime; 418e4d5d1a3SXianjun Jiao u32 rx_mgmt_fail_agc_gain_value_realtime; 419e4d5d1a3SXianjun Jiao u32 rx_ack_ok_agc_gain_value_realtime; 420e4d5d1a3SXianjun Jiao 421e4d5d1a3SXianjun Jiao u32 rx_monitor_all; 422e4d5d1a3SXianjun Jiao u32 rx_data_pkt_num_total; 423e4d5d1a3SXianjun Jiao u32 rx_data_pkt_num_fail; 424e4d5d1a3SXianjun Jiao u32 rx_mgmt_pkt_num_total; 425e4d5d1a3SXianjun Jiao u32 rx_mgmt_pkt_num_fail; 426e4d5d1a3SXianjun Jiao u32 rx_ack_pkt_num_total; 427e4d5d1a3SXianjun Jiao u32 rx_ack_pkt_num_fail; 428e4d5d1a3SXianjun Jiao 429e4d5d1a3SXianjun Jiao u32 rx_data_pkt_mcs_realtime; 430e4d5d1a3SXianjun Jiao u32 rx_data_pkt_fail_mcs_realtime; 431e4d5d1a3SXianjun Jiao u32 rx_mgmt_pkt_mcs_realtime; 432e4d5d1a3SXianjun Jiao u32 rx_mgmt_pkt_fail_mcs_realtime; 433e4d5d1a3SXianjun Jiao u32 rx_ack_pkt_mcs_realtime; 434e4d5d1a3SXianjun Jiao 435e4d5d1a3SXianjun Jiao u32 restrict_freq_mhz; 436e4d5d1a3SXianjun Jiao 437e4d5d1a3SXianjun Jiao u32 csma_cfg0; 438e4d5d1a3SXianjun Jiao u32 cw_max_min_cfg; 439e4d5d1a3SXianjun Jiao 4406bb9ef71SXianjun Jiao u32 dbg_ch0; 4416bb9ef71SXianjun Jiao u32 dbg_ch1; 4426bb9ef71SXianjun Jiao u32 dbg_ch2; 443e4d5d1a3SXianjun Jiao }; 444e4d5d1a3SXianjun Jiao 4452ee67178SXianjun Jiao #define RX_DMA_CYCLIC_MODE 4462ee67178SXianjun Jiao struct openwifi_priv { 4472ee67178SXianjun Jiao struct platform_device *pdev; 4482ee67178SXianjun Jiao struct ieee80211_vif *vif[MAX_NUM_VIF]; 4492ee67178SXianjun Jiao 4502ee67178SXianjun Jiao const struct openwifi_rf_ops *rf; 4516e3730c0Smmehari enum openwifi_fpga_type fpga_type; 4522ee67178SXianjun Jiao 4532ee67178SXianjun Jiao struct cf_axi_dds_state *dds_st; //axi_ad9361 hdl ref design module, dac channel 4542ee67178SXianjun Jiao struct axiadc_state *adc_st; //axi_ad9361 hdl ref design module, adc channel 4552ee67178SXianjun Jiao struct ad9361_rf_phy *ad9361_phy; //ad9361 chip 4562ee67178SXianjun Jiao struct ctrl_outs_control ctrl_out; 4572ee67178SXianjun Jiao 4582ee67178SXianjun Jiao int rx_freq_offset_to_lo_MHz; 4592ee67178SXianjun Jiao int tx_freq_offset_to_lo_MHz; 4602ee67178SXianjun Jiao u32 rf_bw; 4612ee67178SXianjun Jiao u32 actual_rx_lo; 462b196f496SXianjun Jiao u32 actual_tx_lo; 463bc98f5bbSthavinga u32 last_tx_quad_cal_lo; 4642ee67178SXianjun Jiao 4652ee67178SXianjun Jiao struct ieee80211_rate rates_2GHz[12]; 4662ee67178SXianjun Jiao struct ieee80211_rate rates_5GHz[12]; 4671895c3aeSXianjun Jiao struct ieee80211_channel channels_2GHz[13]; 4681895c3aeSXianjun Jiao struct ieee80211_channel channels_5GHz[11]; 4692ee67178SXianjun Jiao struct ieee80211_supported_band band_2GHz; 4702ee67178SXianjun Jiao struct ieee80211_supported_band band_5GHz; 4712ee67178SXianjun Jiao bool rfkill_off; 47256203843SXianjun Jiao u8 runtime_tx_ant_cfg; 47356203843SXianjun Jiao u8 runtime_rx_ant_cfg; 4742ee67178SXianjun Jiao 4752ee67178SXianjun Jiao int rssi_correction; // dynamic RSSI correction according to current channel in _rf_set_channel() 4762ee67178SXianjun Jiao 4772ee67178SXianjun Jiao enum rx_intf_mode rx_intf_cfg; 4782ee67178SXianjun Jiao enum tx_intf_mode tx_intf_cfg; 4792ee67178SXianjun Jiao enum openofdm_rx_mode openofdm_rx_cfg; 4802ee67178SXianjun Jiao enum openofdm_tx_mode openofdm_tx_cfg; 4812ee67178SXianjun Jiao enum xpu_mode xpu_cfg; 4822ee67178SXianjun Jiao 4832ee67178SXianjun Jiao int irq_rx; 4842ee67178SXianjun Jiao int irq_tx; 4852ee67178SXianjun Jiao 486838a9007SXianjun Jiao // u32 call_counter; 4872ee67178SXianjun Jiao u8 *rx_cyclic_buf; 4882ee67178SXianjun Jiao dma_addr_t rx_cyclic_buf_dma_mapping_addr; 4892ee67178SXianjun Jiao struct dma_chan *rx_chan; 4902ee67178SXianjun Jiao struct dma_async_tx_descriptor *rxd; 4912ee67178SXianjun Jiao dma_cookie_t rx_cookie; 4922ee67178SXianjun Jiao 493838a9007SXianjun Jiao struct openwifi_ring tx_ring[MAX_NUM_SW_QUEUE]; 4942ee67178SXianjun Jiao struct scatterlist tx_sg; 4952ee67178SXianjun Jiao struct dma_chan *tx_chan; 4962ee67178SXianjun Jiao struct dma_async_tx_descriptor *txd; 4972ee67178SXianjun Jiao dma_cookie_t tx_cookie; 498838a9007SXianjun Jiao // struct completion tx_dma_complete; 499838a9007SXianjun Jiao // bool openwifi_tx_first_time_run; 5002ee67178SXianjun Jiao 501838a9007SXianjun Jiao // int phy_tx_sn; 502838a9007SXianjun Jiao u32 slice_idx; 5032ee67178SXianjun Jiao u32 dest_mac_addr_queue_map[MAX_NUM_HW_QUEUE]; 5042ee67178SXianjun Jiao u8 mac_addr[ETH_ALEN]; 5052ee67178SXianjun Jiao u16 seqno; 5062ee67178SXianjun Jiao 5072ee67178SXianjun Jiao bool use_short_slot; 5082ee67178SXianjun Jiao u8 band; 5092ae501caSXianjun Jiao u16 channel; 5102ee67178SXianjun Jiao 511261bb9eeSmmehari u32 ampdu_reference; 512261bb9eeSmmehari 5132ee67178SXianjun Jiao u32 drv_rx_reg_val[MAX_NUM_DRV_REG]; 5142ee67178SXianjun Jiao u32 drv_tx_reg_val[MAX_NUM_DRV_REG]; 5152ee67178SXianjun Jiao u32 drv_xpu_reg_val[MAX_NUM_DRV_REG]; 51668314a46SXianjun Jiao int rf_reg_val[MAX_NUM_RF_REG]; 5178598d294SXianjun Jiao int last_auto_fpga_lbt_th; 518e4d5d1a3SXianjun Jiao 519e4d5d1a3SXianjun Jiao struct bin_attribute bin_iq; 520e4d5d1a3SXianjun Jiao u32 tx_intf_arbitrary_iq[512]; 521e4d5d1a3SXianjun Jiao u16 tx_intf_arbitrary_iq_num; 522e4d5d1a3SXianjun Jiao u8 tx_intf_iq_ctl; 523e4d5d1a3SXianjun Jiao 524e4d5d1a3SXianjun Jiao struct openwifi_stat stat; 5252ee67178SXianjun Jiao // u8 num_led; 5262ee67178SXianjun Jiao // struct led_classdev *led[MAX_NUM_LED];//zc706 has 4 user leds. please find openwifi_dev_probe to see how we get them. 5272ee67178SXianjun Jiao // char led_name[MAX_NUM_LED][OPENWIFI_LED_MAX_NAME_LEN]; 5282ee67178SXianjun Jiao 5292ee67178SXianjun Jiao spinlock_t lock; 5302ee67178SXianjun Jiao }; 5312ee67178SXianjun Jiao 5322ee67178SXianjun Jiao #endif /* OPENWIFI_SDR */ 533