1 /* 2 * axi lite register access driver 3 * SPDX-FileCopyrightText: 2019 Jiao Xianjun <[email protected]> 4 * SPDX-License-Identifier: AGPL-3.0-or-later 5 */ 6 7 #include <linux/bitops.h> 8 #include <linux/dmapool.h> 9 #include <linux/dma/xilinx_dma.h> 10 #include <linux/init.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/module.h> 15 #include <linux/of_address.h> 16 #include <linux/of_dma.h> 17 #include <linux/of_platform.h> 18 #include <linux/of_irq.h> 19 #include <linux/slab.h> 20 #include <linux/clk.h> 21 #include <linux/io-64-nonatomic-lo-hi.h> 22 23 #include "../hw_def.h" 24 25 static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design 26 27 /* IO accessors */ 28 static inline u32 reg_read(u32 reg) 29 { 30 return ioread32(base_addr + reg); 31 } 32 33 static inline void reg_write(u32 reg, u32 value) 34 { 35 iowrite32(value, base_addr + reg); 36 } 37 38 static inline u32 RX_INTF_REG_MULTI_RST_read(void){ 39 return reg_read(RX_INTF_REG_MULTI_RST_ADDR); 40 } 41 42 static inline u32 RX_INTF_REG_MIXER_CFG_read(void){ 43 return reg_read(RX_INTF_REG_MIXER_CFG_ADDR); 44 } 45 46 static inline u32 RX_INTF_REG_IQ_SRC_SEL_read(void){ 47 return reg_read(RX_INTF_REG_IQ_SRC_SEL_ADDR); 48 } 49 50 static inline u32 RX_INTF_REG_IQ_CTRL_read(void){ 51 return reg_read(RX_INTF_REG_IQ_CTRL_ADDR); 52 } 53 54 static inline u32 RX_INTF_REG_START_TRANS_TO_PS_MODE_read(void){ 55 return reg_read(RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR); 56 } 57 58 static inline u32 RX_INTF_REG_START_TRANS_TO_PS_read(void){ 59 return reg_read(RX_INTF_REG_START_TRANS_TO_PS_ADDR); 60 } 61 62 static inline u32 RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read(void){ 63 return reg_read(RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR); 64 } 65 66 static inline u32 RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read(void){ 67 return reg_read(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR); 68 } 69 70 static inline u32 RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read(void){ 71 return reg_read(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR); 72 } 73 74 static inline u32 RX_INTF_REG_CFG_DATA_TO_ANT_read(void){ 75 return reg_read(RX_INTF_REG_CFG_DATA_TO_ANT_ADDR); 76 } 77 78 static inline u32 RX_INTF_REG_ANT_SEL_read(void){ 79 return reg_read(RX_INTF_REG_ANT_SEL_ADDR); 80 } 81 82 static inline u32 RX_INTF_REG_INTERRUPT_TEST_read(void) { 83 return reg_read(RX_INTF_REG_INTERRUPT_TEST_ADDR); 84 } 85 86 static inline void RX_INTF_REG_MULTI_RST_write(u32 value){ 87 reg_write(RX_INTF_REG_MULTI_RST_ADDR, value); 88 } 89 90 static inline void RX_INTF_REG_M_AXIS_RST_write(u32 value){ 91 u32 reg_val; 92 93 if (value==0) { 94 reg_val = RX_INTF_REG_MULTI_RST_read(); 95 reg_val = ( reg_val&(~(1<<4)) ); 96 RX_INTF_REG_MULTI_RST_write(reg_val); 97 } else { 98 reg_val = RX_INTF_REG_MULTI_RST_read(); 99 reg_val = ( reg_val|(1<<4) ); 100 RX_INTF_REG_MULTI_RST_write(reg_val); 101 } 102 } 103 104 static inline void RX_INTF_REG_MIXER_CFG_write(u32 value){ 105 reg_write(RX_INTF_REG_MIXER_CFG_ADDR, value); 106 } 107 108 static inline void RX_INTF_REG_IQ_SRC_SEL_write(u32 value){ 109 reg_write(RX_INTF_REG_IQ_SRC_SEL_ADDR, value); 110 } 111 112 static inline void RX_INTF_REG_IQ_CTRL_write(u32 value){ 113 reg_write(RX_INTF_REG_IQ_CTRL_ADDR, value); 114 } 115 116 static inline void RX_INTF_REG_START_TRANS_TO_PS_MODE_write(u32 value){ 117 reg_write(RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR, value); 118 } 119 120 static inline void RX_INTF_REG_START_TRANS_TO_PS_write(u32 value){ 121 reg_write(RX_INTF_REG_START_TRANS_TO_PS_ADDR, value); 122 } 123 124 static inline void RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write(u32 value){ 125 reg_write(RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR, value); 126 } 127 128 static inline void RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(u32 value){ 129 reg_write(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR, value); 130 } 131 132 static inline void RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(u32 value){ 133 reg_write(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR, value); 134 } 135 136 static inline void RX_INTF_REG_CFG_DATA_TO_ANT_write(u32 value){ 137 reg_write(RX_INTF_REG_CFG_DATA_TO_ANT_ADDR, value); 138 } 139 140 static inline void RX_INTF_REG_BB_GAIN_write(u32 value) { 141 reg_write(RX_INTF_REG_BB_GAIN_ADDR, value); 142 } 143 144 static inline void RX_INTF_REG_ANT_SEL_write(u32 value){ 145 reg_write(RX_INTF_REG_ANT_SEL_ADDR, value); 146 } 147 148 static inline void RX_INTF_REG_INTERRUPT_TEST_write(u32 value) { 149 reg_write(RX_INTF_REG_INTERRUPT_TEST_ADDR, value); 150 } 151 152 static inline void RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(u32 value) { 153 reg_write(RX_INTF_REG_S2MM_INTR_DELAY_COUNT_ADDR, value); 154 } 155 156 static inline void RX_INTF_REG_TLAST_TIMEOUT_TOP_write(u32 value) { 157 reg_write(RX_INTF_REG_TLAST_TIMEOUT_TOP_ADDR, value); 158 } 159 160 static const struct of_device_id dev_of_ids[] = { 161 { .compatible = "sdr,rx_intf", }, 162 {} 163 }; 164 MODULE_DEVICE_TABLE(of, dev_of_ids); 165 166 static struct rx_intf_driver_api rx_intf_driver_api_inst; 167 static struct rx_intf_driver_api *rx_intf_api = &rx_intf_driver_api_inst; 168 EXPORT_SYMBOL(rx_intf_api); 169 170 static inline u32 hw_init(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps){ 171 int err=0, i; 172 u32 reg_val, mixer_cfg=0, ant_sel=0; 173 174 printk("%s hw_init mode %d\n", rx_intf_compatible_str, mode); 175 176 rx_intf_api->RX_INTF_REG_TLAST_TIMEOUT_TOP_write(7000); 177 178 //rst 179 for (i=0;i<8;i++) 180 rx_intf_api->RX_INTF_REG_MULTI_RST_write(0); 181 for (i=0;i<32;i++) 182 rx_intf_api->RX_INTF_REG_MULTI_RST_write(0xFFFFFFFF); 183 for (i=0;i<8;i++) 184 rx_intf_api->RX_INTF_REG_MULTI_RST_write(0); 185 186 rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status. will be released when openwifi_start 187 188 switch(mode) 189 { 190 case RX_INTF_AXIS_LOOP_BACK: 191 printk("%s hw_init mode RX_INTF_AXIS_LOOP_BACK\n", rx_intf_compatible_str); 192 //setting the path and mode. This must be done before our dma end reset 193 rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_write(0x15); 194 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write(1); 195 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x37);// endless mode to support sg DMA loop back, start 1 trans from sw trigger 196 197 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(num_dma_symbol_to_pl); 198 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps); 199 200 // put bb_en to constant 1 201 reg_val = rx_intf_api->RX_INTF_REG_IQ_CTRL_read(); 202 reg_val = (reg_val|0x8); 203 rx_intf_api->RX_INTF_REG_IQ_CTRL_write(reg_val); 204 205 // connect axis slave and master directly for loopback 206 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x1037); 207 208 // reset dma end point in our design 209 reg_val = rx_intf_api->RX_INTF_REG_MULTI_RST_read(); 210 reg_val = (reg_val&(~0x14) ); 211 rx_intf_api->RX_INTF_REG_MULTI_RST_write(reg_val); 212 reg_val = reg_val|(0x14); 213 rx_intf_api->RX_INTF_REG_MULTI_RST_write(reg_val); 214 reg_val = reg_val&(~0x14); 215 rx_intf_api->RX_INTF_REG_MULTI_RST_write(reg_val); 216 217 //start 1 trans now from our m_axis to ps dma 218 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(0); 219 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(1); 220 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(0); 221 break; 222 223 case RX_INTF_BW_20MHZ_AT_0MHZ_ANT0: 224 printk("%s hw_init mode DDC_BW_20MHZ_AT_0MHZ\n", rx_intf_compatible_str); 225 mixer_cfg = 0x300200F4; 226 ant_sel=0; 227 break; 228 229 case RX_INTF_BW_20MHZ_AT_0MHZ_ANT1: 230 printk("%s hw_init mode DDC_BW_20MHZ_AT_0MHZ\n", rx_intf_compatible_str); 231 mixer_cfg = 0x300200F4; 232 ant_sel=1; 233 break; 234 235 case RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0: 236 printk("%s hw_init mode DDC_BW_20MHZ_AT_N_10MHZ\n", rx_intf_compatible_str); 237 mixer_cfg = 0x300202F6; 238 ant_sel=0; 239 break; 240 241 case RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1: 242 printk("%s hw_init mode DDC_BW_20MHZ_AT_N_10MHZ\n", rx_intf_compatible_str); 243 mixer_cfg = 0x300202F6; 244 ant_sel=1; 245 break; 246 247 case RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0: 248 printk("%s hw_init mode DDC_BW_20MHZ_AT_P_10MHZ\n", rx_intf_compatible_str); 249 mixer_cfg = 0x3001F602; 250 ant_sel=0; 251 break; 252 253 case RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1: 254 printk("%s hw_init mode DDC_BW_20MHZ_AT_P_10MHZ\n", rx_intf_compatible_str); 255 mixer_cfg = 0x3001F602; 256 ant_sel=1; 257 break; 258 259 case RX_INTF_BYPASS: 260 printk("%s hw_init mode DDC_BYPASS\n", rx_intf_compatible_str); 261 mixer_cfg = 0x3001F602; 262 break; 263 264 default: 265 printk("%s hw_init mode %d is wrong!\n", rx_intf_compatible_str, mode); 266 err=1; 267 } 268 269 if (mode!=RX_INTF_AXIS_LOOP_BACK) { 270 // rx_intf_api->RX_INTF_REG_MIXER_CFG_write(mixer_cfg); --now rx doesn't have mixer anymore 271 // 0x000202F6 for: wifi ant0: -10MHz; wifi ant1: +10MHz; zigbee 4 ch ant0: -2, -7, -12, -17MHz; zigbee 4 ch ant1: +3, +8, +13, +18MHz 272 // 0x0001F602 for: wifi ant0: +10MHz; wifi ant1: -10MHz; zigbee 4 ch ant0: +3, +8, +13, +18MHz; zigbee 4 ch ant1: -2, -7, -12, -17MHz 273 // 0x0001F206 for: wifi ant0: -10MHz; wifi ant1: +10MHz; zigbee 4 ch ant0: +3, +8, +13, +18MHz; zigbee 4 ch ant1: -2, -7, -12, -17MHz 274 // 0x2101F602 for: wifi gain 4; zigbee gain 2 275 // 0xFE01F602 for: wifi gain 1/2; zigbee gain 1/4 276 // bits definitions: 277 // wifi ch selection: ant0 bit1~0; ant1 bit 9~8; ch offset: 0-0MHz; 1-5MHz; 2-10MHz; 3-15MHz(severe distortion) 278 // wifi ch +/- selection: ant0 bit2; ant1 bit 10; 0-positive; 1-negative 279 // zigbee 2M mixer +/- selection: ant0 bit3; ant1 bit 11; 0-positive; 1-negative 280 // zigbee secondary mixer +/- selection: ant0 bit4~7; ant1 bit 12~15; 0-positive; 1-negative 281 // zigbee ch slip offset: ant0 bit16; ant1 bit17; 0-select ch offset 0, 5, 10, 15; 1-select ch offset 5 10 15 20 282 // wifi gain: bit31~28; number of bits shifted to left in 2'complement code 283 // zigb gain: bit27~24; number of bits shifted to left in 2'complement code 284 // max amplitude calibration info (agc low, ddc w/o gain adj 0x0001F602): 5GHz, max amplitude 1.26e4. According to simulation, schr shrink 1bit should be enough 285 286 rx_intf_api->RX_INTF_REG_MULTI_RST_write(0); 287 rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status. will be released when openwifi_start 288 289 //rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x000); 290 rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x100); 291 //0x000-normal; 0x100-sig and fcs valid are controled by bit4 and bit0; 292 //0x111-sig and fcs high; 0x110-sig high fcs low; 0x101-sig low fcs high; 0x100-sig and fcs low 293 294 rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_write(0); 295 // 0-bw20-ch0; 1-bw2-ch0; 2-bw2-ch2; 3-bw2-ch4; 4-bw2-ch6; 5-s_axis-ch0 296 // 8-bw20-ch1; 9-bw2-ch1; 10-bw2-ch3; 11-bw2-ch5; 12-bw2-ch7; 13-s_axis-ch1 297 298 rx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(30*10); // delayed interrupt, counter clock 10MHz is assumed 299 300 rx_intf_api->RX_INTF_REG_IQ_CTRL_write(0); 301 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x10025); //now bit 5 should be 1 to let pl_to_m_axis_intf decide num_dma_symbol_to_ps automatically 302 //rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x00025); //bit16 enable_m_axis_auto_rst 303 //bit2-0: source of M AXIS transfer trigger 304 // -0 fcs_valid_from_acc 305 // -1 sig_valid_from_acc 306 // -2 sig_invalid_from_acc 307 // -3 start_1trans_s_axis_tlast_trigger 308 // -4 start_1trans_s_axis_tready_trigger 309 // -5 internal state machine together with bit5 1. By parsing signal field, num_dma_symbol_to_ps can be decided automatically 310 // -6 start_1trans_monitor_dma_to_ps_start_trigger 311 // -7 start_1trans_ext_trigger 312 //bit3: 1-fcs valid and invalid both connected; 0-only fcs valid connected (fcs_invalid_mode) 313 //bit4: 1-num_dma_symbol_to_pl from monitor; 0-num_dma_symbol_to_pl from slv_reg8 314 //bit5: 1-num_dma_symbol_to_ps from monitor; 0-num_dma_symbol_to_ps from slv_reg9 315 //bit6: 1-pl_to_m_axis_intf will try to send both ht and non-ht; 0-only send non-ht 316 //bit8: 1-endless S AXIS; 0-normal 317 //bit9: 1-endless M AXIS; 0-normal 318 //bit12: 1-direct loop back; 0-normal 319 //bit16: 1-auto m_axis rst (sig_valid_from_acc|sig_invalid_from_acc|ht_sig_valid|ht_sig_invalid|ht_unsupported); 0-normal 320 //bit24: 1-disable m_axis fifo_rst_by_fcs_invalid; 0-enable 321 //bit29,28: sig_valid_mode. 0- non-ht sig valid; 1- ht sig valid other- both 322 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(0); 323 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write(0); 324 // 0-wifi_rx packet out; 1-loopback from input of wifi_rx 325 326 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(num_dma_symbol_to_pl); 327 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps); 328 rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_write(1<<8); 329 rx_intf_api->RX_INTF_REG_BB_GAIN_write(4); 330 rx_intf_api->RX_INTF_REG_ANT_SEL_write(ant_sel); 331 332 rx_intf_api->RX_INTF_REG_MULTI_RST_write(0x14);//rst m/s axis 333 rx_intf_api->RX_INTF_REG_MULTI_RST_write(0); 334 rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status. will be released when openwifi_start 335 } 336 337 if (mode==RX_INTF_BYPASS) { 338 rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_write(0x10); //bit4 bypass enable 339 } 340 341 printk("%s hw_init err %d\n", rx_intf_compatible_str, err); 342 return(err); 343 } 344 345 static int dev_probe(struct platform_device *pdev) 346 { 347 struct device_node *np = pdev->dev.of_node; 348 struct resource *io; 349 int err=1; 350 351 printk("\n"); 352 353 if (np) { 354 const struct of_device_id *match; 355 356 match = of_match_node(dev_of_ids, np); 357 if (match) { 358 printk("%s dev_probe match!\n", rx_intf_compatible_str); 359 err = 0; 360 } 361 } 362 363 if (err) 364 return err; 365 366 rx_intf_api->hw_init=hw_init; 367 368 rx_intf_api->reg_read=reg_read; 369 rx_intf_api->reg_write=reg_write; 370 371 rx_intf_api->RX_INTF_REG_MULTI_RST_read=RX_INTF_REG_MULTI_RST_read; 372 rx_intf_api->RX_INTF_REG_MIXER_CFG_read=RX_INTF_REG_MIXER_CFG_read; 373 rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_read=RX_INTF_REG_IQ_SRC_SEL_read; 374 rx_intf_api->RX_INTF_REG_IQ_CTRL_read=RX_INTF_REG_IQ_CTRL_read; 375 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_read=RX_INTF_REG_START_TRANS_TO_PS_MODE_read; 376 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_read=RX_INTF_REG_START_TRANS_TO_PS_read; 377 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read=RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read; 378 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read; 379 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read; 380 rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_read=RX_INTF_REG_CFG_DATA_TO_ANT_read; 381 rx_intf_api->RX_INTF_REG_ANT_SEL_read=RX_INTF_REG_ANT_SEL_read; 382 rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_read=RX_INTF_REG_INTERRUPT_TEST_read; 383 384 rx_intf_api->RX_INTF_REG_MULTI_RST_write=RX_INTF_REG_MULTI_RST_write; 385 rx_intf_api->RX_INTF_REG_M_AXIS_RST_write=RX_INTF_REG_M_AXIS_RST_write; 386 rx_intf_api->RX_INTF_REG_MIXER_CFG_write=RX_INTF_REG_MIXER_CFG_write; 387 rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_write=RX_INTF_REG_IQ_SRC_SEL_write; 388 rx_intf_api->RX_INTF_REG_IQ_CTRL_write=RX_INTF_REG_IQ_CTRL_write; 389 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write=RX_INTF_REG_START_TRANS_TO_PS_MODE_write; 390 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write=RX_INTF_REG_START_TRANS_TO_PS_write; 391 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write=RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write; 392 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write; 393 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write; 394 rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_write=RX_INTF_REG_CFG_DATA_TO_ANT_write; 395 rx_intf_api->RX_INTF_REG_BB_GAIN_write=RX_INTF_REG_BB_GAIN_write; 396 rx_intf_api->RX_INTF_REG_ANT_SEL_write=RX_INTF_REG_ANT_SEL_write; 397 rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write=RX_INTF_REG_INTERRUPT_TEST_write; 398 399 rx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write=RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write; 400 rx_intf_api->RX_INTF_REG_TLAST_TIMEOUT_TOP_write=RX_INTF_REG_TLAST_TIMEOUT_TOP_write; 401 402 /* Request and map I/O memory */ 403 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 404 base_addr = devm_ioremap_resource(&pdev->dev, io); 405 if (IS_ERR(base_addr)) 406 return PTR_ERR(base_addr); 407 408 rx_intf_api->io_start = io->start; 409 rx_intf_api->base_addr = (u32)base_addr; 410 411 printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", rx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); 412 printk("%s dev_probe base_addr 0x%08x\n", rx_intf_compatible_str,(u32)base_addr); 413 printk("%s dev_probe rx_intf_driver_api_inst 0x%08x\n", rx_intf_compatible_str, (u32)(&rx_intf_driver_api_inst) ); 414 printk("%s dev_probe rx_intf_api 0x%08x\n", rx_intf_compatible_str, (u32)rx_intf_api); 415 416 printk("%s dev_probe succeed!\n", rx_intf_compatible_str); 417 418 //err = hw_init(DDC_CURRENT_CH_OFFSET_CFG,8,8); 419 err = hw_init(RX_INTF_BW_20MHZ_AT_0MHZ_ANT0,8,8); 420 421 return err; 422 } 423 424 static int dev_remove(struct platform_device *pdev) 425 { 426 printk("\n"); 427 428 printk("%s dev_remove base_addr 0x%08x\n", rx_intf_compatible_str, (u32)base_addr); 429 printk("%s dev_remove rx_intf_driver_api_inst 0x%08x\n", rx_intf_compatible_str, (u32)(&rx_intf_driver_api_inst) ); 430 printk("%s dev_remove rx_intf_api 0x%08x\n", rx_intf_compatible_str, (u32)rx_intf_api); 431 432 printk("%s dev_remove succeed!\n", rx_intf_compatible_str); 433 return 0; 434 } 435 436 static struct platform_driver dev_driver = { 437 .driver = { 438 .name = "sdr,rx_intf", 439 .owner = THIS_MODULE, 440 .of_match_table = dev_of_ids, 441 }, 442 .probe = dev_probe, 443 .remove = dev_remove, 444 }; 445 446 module_platform_driver(dev_driver); 447 448 MODULE_AUTHOR("Xianjun Jiao"); 449 MODULE_DESCRIPTION("sdr,rx_intf"); 450 MODULE_LICENSE("GPL v2"); 451