1 /* 2 * axi lite register access driver 3 * Author: Xianjun Jiao, Michael Mehari, Wei Liu 4 * SPDX-FileCopyrightText: 2019 UGent 5 * SPDX-License-Identifier: AGPL-3.0-or-later 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/dmapool.h> 10 #include <linux/dma/xilinx_dma.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/of_dma.h> 18 #include <linux/of_platform.h> 19 #include <linux/of_irq.h> 20 #include <linux/slab.h> 21 #include <linux/clk.h> 22 #include <linux/io-64-nonatomic-lo-hi.h> 23 24 #include "../hw_def.h" 25 26 static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design 27 28 /* IO accessors */ 29 static inline u32 reg_read(u32 reg) 30 { 31 return ioread32(base_addr + reg); 32 } 33 34 static inline void reg_write(u32 reg, u32 value) 35 { 36 iowrite32(value, base_addr + reg); 37 } 38 39 static inline u32 RX_INTF_REG_MULTI_RST_read(void){ 40 return reg_read(RX_INTF_REG_MULTI_RST_ADDR); 41 } 42 43 static inline u32 RX_INTF_REG_MIXER_CFG_read(void){ 44 return reg_read(RX_INTF_REG_MIXER_CFG_ADDR); 45 } 46 47 static inline u32 RX_INTF_REG_IQ_SRC_SEL_read(void){ 48 return reg_read(RX_INTF_REG_IQ_SRC_SEL_ADDR); 49 } 50 51 static inline u32 RX_INTF_REG_IQ_CTRL_read(void){ 52 return reg_read(RX_INTF_REG_IQ_CTRL_ADDR); 53 } 54 55 static inline u32 RX_INTF_REG_START_TRANS_TO_PS_MODE_read(void){ 56 return reg_read(RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR); 57 } 58 59 static inline u32 RX_INTF_REG_START_TRANS_TO_PS_read(void){ 60 return reg_read(RX_INTF_REG_START_TRANS_TO_PS_ADDR); 61 } 62 63 static inline u32 RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read(void){ 64 return reg_read(RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR); 65 } 66 67 static inline u32 RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read(void){ 68 return reg_read(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR); 69 } 70 71 static inline u32 RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read(void){ 72 return reg_read(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR); 73 } 74 75 static inline u32 RX_INTF_REG_CFG_DATA_TO_ANT_read(void){ 76 return reg_read(RX_INTF_REG_CFG_DATA_TO_ANT_ADDR); 77 } 78 79 static inline u32 RX_INTF_REG_ANT_SEL_read(void){ 80 return reg_read(RX_INTF_REG_ANT_SEL_ADDR); 81 } 82 83 static inline u32 RX_INTF_REG_INTERRUPT_TEST_read(void) { 84 return reg_read(RX_INTF_REG_INTERRUPT_TEST_ADDR); 85 } 86 87 static inline void RX_INTF_REG_MULTI_RST_write(u32 value){ 88 reg_write(RX_INTF_REG_MULTI_RST_ADDR, value); 89 } 90 91 static inline void RX_INTF_REG_M_AXIS_RST_write(u32 value){ 92 u32 reg_val; 93 94 if (value==0) { 95 reg_val = RX_INTF_REG_MULTI_RST_read(); 96 reg_val = ( reg_val&(~(1<<4)) ); 97 RX_INTF_REG_MULTI_RST_write(reg_val); 98 } else { 99 reg_val = RX_INTF_REG_MULTI_RST_read(); 100 reg_val = ( reg_val|(1<<4) ); 101 RX_INTF_REG_MULTI_RST_write(reg_val); 102 } 103 } 104 105 static inline void RX_INTF_REG_MIXER_CFG_write(u32 value){ 106 reg_write(RX_INTF_REG_MIXER_CFG_ADDR, value); 107 } 108 109 static inline void RX_INTF_REG_IQ_SRC_SEL_write(u32 value){ 110 reg_write(RX_INTF_REG_IQ_SRC_SEL_ADDR, value); 111 } 112 113 static inline void RX_INTF_REG_IQ_CTRL_write(u32 value){ 114 reg_write(RX_INTF_REG_IQ_CTRL_ADDR, value); 115 } 116 117 static inline void RX_INTF_REG_START_TRANS_TO_PS_MODE_write(u32 value){ 118 reg_write(RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR, value); 119 } 120 121 static inline void RX_INTF_REG_START_TRANS_TO_PS_write(u32 value){ 122 reg_write(RX_INTF_REG_START_TRANS_TO_PS_ADDR, value); 123 } 124 125 static inline void RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write(u32 value){ 126 reg_write(RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR, value); 127 } 128 129 static inline void RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(u32 value){ 130 reg_write(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR, value); 131 } 132 133 static inline void RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(u32 value){ 134 reg_write(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR, value); 135 } 136 137 static inline void RX_INTF_REG_CFG_DATA_TO_ANT_write(u32 value){ 138 reg_write(RX_INTF_REG_CFG_DATA_TO_ANT_ADDR, value); 139 } 140 141 static inline void RX_INTF_REG_BB_GAIN_write(u32 value) { 142 reg_write(RX_INTF_REG_BB_GAIN_ADDR, value); 143 } 144 145 static inline void RX_INTF_REG_ANT_SEL_write(u32 value){ 146 reg_write(RX_INTF_REG_ANT_SEL_ADDR, value); 147 } 148 149 static inline void RX_INTF_REG_INTERRUPT_TEST_write(u32 value) { 150 reg_write(RX_INTF_REG_INTERRUPT_TEST_ADDR, value); 151 } 152 153 static inline void RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(u32 value) { 154 reg_write(RX_INTF_REG_S2MM_INTR_DELAY_COUNT_ADDR, value); 155 } 156 157 static inline void RX_INTF_REG_TLAST_TIMEOUT_TOP_write(u32 value) { 158 reg_write(RX_INTF_REG_TLAST_TIMEOUT_TOP_ADDR, value); 159 } 160 161 static const struct of_device_id dev_of_ids[] = { 162 { .compatible = "sdr,rx_intf", }, 163 {} 164 }; 165 MODULE_DEVICE_TABLE(of, dev_of_ids); 166 167 static struct rx_intf_driver_api rx_intf_driver_api_inst; 168 static struct rx_intf_driver_api *rx_intf_api = &rx_intf_driver_api_inst; 169 EXPORT_SYMBOL(rx_intf_api); 170 171 static inline u32 hw_init(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps){ 172 int err=0, i; 173 u32 reg_val, mixer_cfg=0, ant_sel=0; 174 175 printk("%s hw_init mode %d\n", rx_intf_compatible_str, mode); 176 177 rx_intf_api->RX_INTF_REG_TLAST_TIMEOUT_TOP_write(7000); 178 179 //rst 180 for (i=0;i<8;i++) 181 rx_intf_api->RX_INTF_REG_MULTI_RST_write(0); 182 for (i=0;i<32;i++) 183 rx_intf_api->RX_INTF_REG_MULTI_RST_write(0xFFFFFFFF); 184 for (i=0;i<8;i++) 185 rx_intf_api->RX_INTF_REG_MULTI_RST_write(0); 186 187 rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status. will be released when openwifi_start 188 189 switch(mode) 190 { 191 case RX_INTF_AXIS_LOOP_BACK: 192 printk("%s hw_init mode RX_INTF_AXIS_LOOP_BACK\n", rx_intf_compatible_str); 193 //setting the path and mode. This must be done before our dma end reset 194 rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_write(0x15); 195 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write(1); 196 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x37);// endless mode to support sg DMA loop back, start 1 trans from sw trigger 197 198 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(num_dma_symbol_to_pl); 199 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps); 200 201 // put bb_en to constant 1 202 reg_val = rx_intf_api->RX_INTF_REG_IQ_CTRL_read(); 203 reg_val = (reg_val|0x8); 204 rx_intf_api->RX_INTF_REG_IQ_CTRL_write(reg_val); 205 206 // connect axis slave and master directly for loopback 207 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x1037); 208 209 // reset dma end point in our design 210 reg_val = rx_intf_api->RX_INTF_REG_MULTI_RST_read(); 211 reg_val = (reg_val&(~0x14) ); 212 rx_intf_api->RX_INTF_REG_MULTI_RST_write(reg_val); 213 reg_val = reg_val|(0x14); 214 rx_intf_api->RX_INTF_REG_MULTI_RST_write(reg_val); 215 reg_val = reg_val&(~0x14); 216 rx_intf_api->RX_INTF_REG_MULTI_RST_write(reg_val); 217 218 //start 1 trans now from our m_axis to ps dma 219 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(0); 220 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(1); 221 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(0); 222 break; 223 224 case RX_INTF_BW_20MHZ_AT_0MHZ_ANT0: 225 printk("%s hw_init mode DDC_BW_20MHZ_AT_0MHZ\n", rx_intf_compatible_str); 226 mixer_cfg = 0x300200F4; 227 ant_sel=0; 228 break; 229 230 case RX_INTF_BW_20MHZ_AT_0MHZ_ANT1: 231 printk("%s hw_init mode DDC_BW_20MHZ_AT_0MHZ\n", rx_intf_compatible_str); 232 mixer_cfg = 0x300200F4; 233 ant_sel=1; 234 break; 235 236 case RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0: 237 printk("%s hw_init mode DDC_BW_20MHZ_AT_N_10MHZ\n", rx_intf_compatible_str); 238 mixer_cfg = 0x300202F6; 239 ant_sel=0; 240 break; 241 242 case RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1: 243 printk("%s hw_init mode DDC_BW_20MHZ_AT_N_10MHZ\n", rx_intf_compatible_str); 244 mixer_cfg = 0x300202F6; 245 ant_sel=1; 246 break; 247 248 case RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0: 249 printk("%s hw_init mode DDC_BW_20MHZ_AT_P_10MHZ\n", rx_intf_compatible_str); 250 mixer_cfg = 0x3001F602; 251 ant_sel=0; 252 break; 253 254 case RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1: 255 printk("%s hw_init mode DDC_BW_20MHZ_AT_P_10MHZ\n", rx_intf_compatible_str); 256 mixer_cfg = 0x3001F602; 257 ant_sel=1; 258 break; 259 260 case RX_INTF_BYPASS: 261 printk("%s hw_init mode DDC_BYPASS\n", rx_intf_compatible_str); 262 mixer_cfg = 0x3001F602; 263 break; 264 265 default: 266 printk("%s hw_init mode %d is wrong!\n", rx_intf_compatible_str, mode); 267 err=1; 268 } 269 270 if (mode!=RX_INTF_AXIS_LOOP_BACK) { 271 // rx_intf_api->RX_INTF_REG_MIXER_CFG_write(mixer_cfg); --now rx doesn't have mixer anymore 272 // 0x000202F6 for: wifi ant0: -10MHz; wifi ant1: +10MHz; zigbee 4 ch ant0: -2, -7, -12, -17MHz; zigbee 4 ch ant1: +3, +8, +13, +18MHz 273 // 0x0001F602 for: wifi ant0: +10MHz; wifi ant1: -10MHz; zigbee 4 ch ant0: +3, +8, +13, +18MHz; zigbee 4 ch ant1: -2, -7, -12, -17MHz 274 // 0x0001F206 for: wifi ant0: -10MHz; wifi ant1: +10MHz; zigbee 4 ch ant0: +3, +8, +13, +18MHz; zigbee 4 ch ant1: -2, -7, -12, -17MHz 275 // 0x2101F602 for: wifi gain 4; zigbee gain 2 276 // 0xFE01F602 for: wifi gain 1/2; zigbee gain 1/4 277 // bits definitions: 278 // wifi ch selection: ant0 bit1~0; ant1 bit 9~8; ch offset: 0-0MHz; 1-5MHz; 2-10MHz; 3-15MHz(severe distortion) 279 // wifi ch +/- selection: ant0 bit2; ant1 bit 10; 0-positive; 1-negative 280 // zigbee 2M mixer +/- selection: ant0 bit3; ant1 bit 11; 0-positive; 1-negative 281 // zigbee secondary mixer +/- selection: ant0 bit4~7; ant1 bit 12~15; 0-positive; 1-negative 282 // zigbee ch slip offset: ant0 bit16; ant1 bit17; 0-select ch offset 0, 5, 10, 15; 1-select ch offset 5 10 15 20 283 // wifi gain: bit31~28; number of bits shifted to left in 2'complement code 284 // zigb gain: bit27~24; number of bits shifted to left in 2'complement code 285 // max amplitude calibration info (agc low, ddc w/o gain adj 0x0001F602): 5GHz, max amplitude 1.26e4. According to simulation, schr shrink 1bit should be enough 286 287 rx_intf_api->RX_INTF_REG_MULTI_RST_write(0); 288 rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status. will be released when openwifi_start 289 290 //rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x000); 291 rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x100); 292 //0x000-normal; 0x100-sig and fcs valid are controlled by bit4 and bit0; 293 //0x111-sig and fcs high; 0x110-sig high fcs low; 0x101-sig low fcs high; 0x100-sig and fcs low 294 295 rx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(30*10); // delayed interrupt, counter clock 10MHz is assumed 296 297 rx_intf_api->RX_INTF_REG_IQ_CTRL_write(0); 298 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x10025); //now bit 5 should be 1 to let pl_to_m_axis_intf decide num_dma_symbol_to_ps automatically 299 //rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x00025); //bit16 enable_m_axis_auto_rst 300 //bit2-0: source of M AXIS transfer trigger 301 // -0 fcs_valid_from_acc 302 // -1 sig_valid_from_acc 303 // -2 sig_invalid_from_acc 304 // -3 start_1trans_s_axis_tlast_trigger 305 // -4 start_1trans_s_axis_tready_trigger 306 // -5 internal state machine together with bit5 1. By parsing signal field, num_dma_symbol_to_ps can be decided automatically 307 // -6 start_1trans_monitor_dma_to_ps_start_trigger 308 // -7 start_1trans_ext_trigger 309 //bit3: 1-fcs valid and invalid both connected; 0-only fcs valid connected (fcs_invalid_mode) 310 //bit4: 1-num_dma_symbol_to_pl from monitor; 0-num_dma_symbol_to_pl from slv_reg8 311 //bit5: 1-num_dma_symbol_to_ps from monitor; 0-num_dma_symbol_to_ps from slv_reg9 312 //bit6: 1-pl_to_m_axis_intf will try to send both ht and non-ht; 0-only send non-ht 313 //bit8: 1-endless S AXIS; 0-normal 314 //bit9: 1-endless M AXIS; 0-normal 315 //bit12: 1-direct loop back; 0-normal 316 //bit16: 1-auto m_axis rst (sig_valid_from_acc|sig_invalid_from_acc|ht_sig_valid|ht_sig_invalid|ht_unsupported); 0-normal 317 //bit24: 1-disable m_axis fifo_rst_by_fcs_invalid; 0-enable 318 //bit29,28: sig_valid_mode. 0- non-ht sig valid; 1- ht sig valid other- both 319 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(OPENWIFI_MAX_SIGNAL_LEN_TH<<16); //bit31~16 max pkt length threshold 320 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write(0); 321 // 0-wifi_rx packet out; 1-loopback from input of wifi_rx 322 323 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(num_dma_symbol_to_pl); 324 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps); 325 rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_write(1<<8); 326 rx_intf_api->RX_INTF_REG_BB_GAIN_write(4); 327 rx_intf_api->RX_INTF_REG_ANT_SEL_write(ant_sel); 328 329 rx_intf_api->RX_INTF_REG_MULTI_RST_write(0x14);//rst m/s axis 330 rx_intf_api->RX_INTF_REG_MULTI_RST_write(0); 331 rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status. will be released when openwifi_start 332 } 333 334 if (mode==RX_INTF_BYPASS) { 335 rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_write(0x10); //bit4 bypass enable 336 } 337 338 printk("%s hw_init err %d\n", rx_intf_compatible_str, err); 339 return(err); 340 } 341 342 static int dev_probe(struct platform_device *pdev) 343 { 344 struct device_node *np = pdev->dev.of_node; 345 struct resource *io; 346 int err=1; 347 348 printk("\n"); 349 350 if (np) { 351 const struct of_device_id *match; 352 353 match = of_match_node(dev_of_ids, np); 354 if (match) { 355 printk("%s dev_probe match!\n", rx_intf_compatible_str); 356 err = 0; 357 } 358 } 359 360 if (err) 361 return err; 362 363 rx_intf_api->hw_init=hw_init; 364 365 rx_intf_api->reg_read=reg_read; 366 rx_intf_api->reg_write=reg_write; 367 368 rx_intf_api->RX_INTF_REG_MULTI_RST_read=RX_INTF_REG_MULTI_RST_read; 369 rx_intf_api->RX_INTF_REG_MIXER_CFG_read=RX_INTF_REG_MIXER_CFG_read; 370 rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_read=RX_INTF_REG_IQ_SRC_SEL_read; 371 rx_intf_api->RX_INTF_REG_IQ_CTRL_read=RX_INTF_REG_IQ_CTRL_read; 372 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_read=RX_INTF_REG_START_TRANS_TO_PS_MODE_read; 373 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_read=RX_INTF_REG_START_TRANS_TO_PS_read; 374 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read=RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read; 375 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read; 376 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read; 377 rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_read=RX_INTF_REG_CFG_DATA_TO_ANT_read; 378 rx_intf_api->RX_INTF_REG_ANT_SEL_read=RX_INTF_REG_ANT_SEL_read; 379 rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_read=RX_INTF_REG_INTERRUPT_TEST_read; 380 381 rx_intf_api->RX_INTF_REG_MULTI_RST_write=RX_INTF_REG_MULTI_RST_write; 382 rx_intf_api->RX_INTF_REG_M_AXIS_RST_write=RX_INTF_REG_M_AXIS_RST_write; 383 rx_intf_api->RX_INTF_REG_MIXER_CFG_write=RX_INTF_REG_MIXER_CFG_write; 384 rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_write=RX_INTF_REG_IQ_SRC_SEL_write; 385 rx_intf_api->RX_INTF_REG_IQ_CTRL_write=RX_INTF_REG_IQ_CTRL_write; 386 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write=RX_INTF_REG_START_TRANS_TO_PS_MODE_write; 387 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write=RX_INTF_REG_START_TRANS_TO_PS_write; 388 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write=RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write; 389 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write; 390 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write; 391 rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_write=RX_INTF_REG_CFG_DATA_TO_ANT_write; 392 rx_intf_api->RX_INTF_REG_BB_GAIN_write=RX_INTF_REG_BB_GAIN_write; 393 rx_intf_api->RX_INTF_REG_ANT_SEL_write=RX_INTF_REG_ANT_SEL_write; 394 rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write=RX_INTF_REG_INTERRUPT_TEST_write; 395 396 rx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write=RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write; 397 rx_intf_api->RX_INTF_REG_TLAST_TIMEOUT_TOP_write=RX_INTF_REG_TLAST_TIMEOUT_TOP_write; 398 399 /* Request and map I/O memory */ 400 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 401 base_addr = devm_ioremap_resource(&pdev->dev, io); 402 if (IS_ERR(base_addr)) 403 return PTR_ERR(base_addr); 404 405 rx_intf_api->io_start = io->start; 406 rx_intf_api->base_addr = (u32)base_addr; 407 408 printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", rx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); 409 printk("%s dev_probe base_addr 0x%08x\n", rx_intf_compatible_str,(u32)base_addr); 410 printk("%s dev_probe rx_intf_driver_api_inst 0x%08x\n", rx_intf_compatible_str, (u32)(&rx_intf_driver_api_inst) ); 411 printk("%s dev_probe rx_intf_api 0x%08x\n", rx_intf_compatible_str, (u32)rx_intf_api); 412 413 printk("%s dev_probe succeed!\n", rx_intf_compatible_str); 414 415 //err = hw_init(DDC_CURRENT_CH_OFFSET_CFG,8,8); 416 err = hw_init(RX_INTF_BW_20MHZ_AT_0MHZ_ANT0,8,8); 417 418 return err; 419 } 420 421 static int dev_remove(struct platform_device *pdev) 422 { 423 printk("\n"); 424 425 printk("%s dev_remove base_addr 0x%08x\n", rx_intf_compatible_str, (u32)base_addr); 426 printk("%s dev_remove rx_intf_driver_api_inst 0x%08x\n", rx_intf_compatible_str, (u32)(&rx_intf_driver_api_inst) ); 427 printk("%s dev_remove rx_intf_api 0x%08x\n", rx_intf_compatible_str, (u32)rx_intf_api); 428 429 printk("%s dev_remove succeed!\n", rx_intf_compatible_str); 430 return 0; 431 } 432 433 static struct platform_driver dev_driver = { 434 .driver = { 435 .name = "sdr,rx_intf", 436 .owner = THIS_MODULE, 437 .of_match_table = dev_of_ids, 438 }, 439 .probe = dev_probe, 440 .remove = dev_remove, 441 }; 442 443 module_platform_driver(dev_driver); 444 445 MODULE_AUTHOR("Xianjun Jiao"); 446 MODULE_DESCRIPTION("sdr,rx_intf"); 447 MODULE_LICENSE("GPL v2"); 448