1 /* 2 * axi lite register access driver 3 * Xianjun jiao. [email protected]; [email protected] 4 */ 5 6 #include <linux/bitops.h> 7 #include <linux/dmapool.h> 8 #include <linux/dma/xilinx_dma.h> 9 #include <linux/init.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/module.h> 14 #include <linux/of_address.h> 15 #include <linux/of_dma.h> 16 #include <linux/of_platform.h> 17 #include <linux/of_irq.h> 18 #include <linux/slab.h> 19 #include <linux/clk.h> 20 #include <linux/io-64-nonatomic-lo-hi.h> 21 #include <linux/delay.h> 22 23 #include "../hw_def.h" 24 25 static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design 26 27 /* IO accessors */ 28 static inline u32 reg_read(u32 reg) 29 { 30 return ioread32(base_addr + reg); 31 } 32 33 static inline void reg_write(u32 reg, u32 value) 34 { 35 iowrite32(value, base_addr + reg); 36 } 37 38 static inline u32 OPENOFDM_RX_REG_STATE_HISTORY_read(void){ 39 return reg_read(OPENOFDM_RX_REG_STATE_HISTORY_ADDR); 40 } 41 42 static inline void OPENOFDM_RX_REG_MULTI_RST_write(u32 Data) { 43 reg_write(OPENOFDM_RX_REG_MULTI_RST_ADDR, Data); 44 } 45 static inline void OPENOFDM_RX_REG_ENABLE_write(u32 Data) { 46 reg_write(OPENOFDM_RX_REG_ENABLE_ADDR, Data); 47 } 48 static inline void OPENOFDM_RX_REG_POWER_THRES_write(u32 Data) { 49 reg_write(OPENOFDM_RX_REG_POWER_THRES_ADDR, Data); 50 } 51 static inline void OPENOFDM_RX_REG_MIN_PLATEAU_write(u32 Data) { 52 reg_write(OPENOFDM_RX_REG_MIN_PLATEAU_ADDR, Data); 53 } 54 55 static const struct of_device_id dev_of_ids[] = { 56 { .compatible = "sdr,openofdm_rx", }, 57 {} 58 }; 59 MODULE_DEVICE_TABLE(of, dev_of_ids); 60 61 static struct openofdm_rx_driver_api openofdm_rx_driver_api_inst; 62 static struct openofdm_rx_driver_api *openofdm_rx_api = &openofdm_rx_driver_api_inst; 63 EXPORT_SYMBOL(openofdm_rx_api); 64 65 static inline u32 hw_init(enum openofdm_rx_mode mode){ 66 int err=0, i; 67 68 printk("%s hw_init mode %d\n", openofdm_rx_compatible_str, mode); 69 70 switch(mode) 71 { 72 case OPENOFDM_RX_TEST: 73 { 74 printk("%s hw_init mode OPENOFDM_RX_TEST\n", openofdm_rx_compatible_str); 75 break; 76 } 77 case OPENOFDM_RX_NORMAL: 78 { 79 printk("%s hw_init mode OPENOFDM_RX_NORMAL\n", openofdm_rx_compatible_str); 80 openofdm_rx_api->power_thres = 0; 81 openofdm_rx_api->min_plateau = 100; 82 break; 83 } 84 default: 85 { 86 printk("%s hw_init mode %d is wrong!\n", openofdm_rx_compatible_str, mode); 87 err=1; 88 } 89 } 90 printk("%s hw_init input:\npower_thres %d\nmin_plateau %d\n", 91 openofdm_rx_compatible_str, 92 openofdm_rx_api->power_thres, openofdm_rx_api->min_plateau); 93 94 // 1) power threshold configuration and reset 95 openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write(0); 96 openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(100); 97 98 //rst 99 for (i=0;i<8;i++) 100 openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0); 101 for (i=0;i<32;i++) 102 openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF); 103 for (i=0;i<8;i++) 104 openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0); 105 106 printk("%s hw_init err %d\n", openofdm_rx_compatible_str, err); 107 108 reg_write(4*4,1);//enable soft decoding 109 return(err); 110 } 111 112 static int dev_probe(struct platform_device *pdev) 113 { 114 struct device_node *np = pdev->dev.of_node; 115 struct resource *io; 116 int err=1; 117 118 printk("\n"); 119 120 if (np) { 121 const struct of_device_id *match; 122 123 match = of_match_node(dev_of_ids, np); 124 if (match) { 125 printk("%s dev_probe match!\n", openofdm_rx_compatible_str); 126 err = 0; 127 } 128 } 129 130 if (err) 131 return err; 132 133 openofdm_rx_api->hw_init=hw_init; 134 135 openofdm_rx_api->reg_read=reg_read; 136 openofdm_rx_api->reg_write=reg_write; 137 138 openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write=OPENOFDM_RX_REG_MULTI_RST_write; 139 openofdm_rx_api->OPENOFDM_RX_REG_ENABLE_write=OPENOFDM_RX_REG_ENABLE_write; 140 openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write=OPENOFDM_RX_REG_POWER_THRES_write; 141 openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write=OPENOFDM_RX_REG_MIN_PLATEAU_write; 142 143 /* Request and map I/O memory */ 144 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 145 base_addr = devm_ioremap_resource(&pdev->dev, io); 146 if (IS_ERR(base_addr)) 147 return PTR_ERR(base_addr); 148 149 printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", openofdm_rx_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); 150 printk("%s dev_probe base_addr 0x%08x\n", openofdm_rx_compatible_str,(u32)base_addr); 151 printk("%s dev_probe openofdm_rx_driver_api_inst 0x%08x\n", openofdm_rx_compatible_str, (u32)&openofdm_rx_driver_api_inst); 152 printk("%s dev_probe openofdm_rx_api 0x%08x\n", openofdm_rx_compatible_str, (u32)openofdm_rx_api); 153 154 printk("%s dev_probe succeed!\n", openofdm_rx_compatible_str); 155 156 err = hw_init(OPENOFDM_RX_NORMAL); 157 158 return err; 159 } 160 161 static int dev_remove(struct platform_device *pdev) 162 { 163 printk("\n"); 164 165 printk("%s dev_remove base_addr 0x%08x\n", openofdm_rx_compatible_str,(u32)base_addr); 166 printk("%s dev_remove openofdm_rx_driver_api_inst 0x%08x\n", openofdm_rx_compatible_str, (u32)&openofdm_rx_driver_api_inst); 167 printk("%s dev_remove openofdm_rx_api 0x%08x\n", openofdm_rx_compatible_str, (u32)openofdm_rx_api); 168 169 printk("%s dev_remove succeed!\n", openofdm_rx_compatible_str); 170 return 0; 171 } 172 173 static struct platform_driver dev_driver = { 174 .driver = { 175 .name = "sdr,openofdm_rx", 176 .owner = THIS_MODULE, 177 .of_match_table = dev_of_ids, 178 }, 179 .probe = dev_probe, 180 .remove = dev_remove, 181 }; 182 183 module_platform_driver(dev_driver); 184 185 MODULE_AUTHOR("Xianjun Jiao"); 186 MODULE_DESCRIPTION("sdr,openofdm_rx"); 187 MODULE_LICENSE("GPL v2"); 188