1 /* 2 * Author: Xianjun jiao, Michael Mehari, Wei Liu 3 * SPDX-FileCopyrightText: 2019 UGent 4 * SPDX-License-Identifier: AGPL-3.0-or-later 5 */ 6 7 #include <linux/bitops.h> 8 #include <linux/dmapool.h> 9 #include <linux/dma/xilinx_dma.h> 10 #include <linux/init.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/module.h> 15 #include <linux/of_address.h> 16 #include <linux/of_dma.h> 17 #include <linux/of_platform.h> 18 #include <linux/of_irq.h> 19 #include <linux/slab.h> 20 #include <linux/clk.h> 21 #include <linux/io-64-nonatomic-lo-hi.h> 22 #include <linux/delay.h> 23 24 #include "../hw_def.h" 25 26 static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design 27 28 /* IO accessors */ 29 static inline u32 reg_read(u32 reg) 30 { 31 return ioread32(base_addr + reg); 32 } 33 34 static inline void reg_write(u32 reg, u32 value) 35 { 36 iowrite32(value, base_addr + reg); 37 } 38 39 static inline u32 OPENOFDM_RX_REG_STATE_HISTORY_read(void){ 40 return reg_read(OPENOFDM_RX_REG_STATE_HISTORY_ADDR); 41 } 42 43 static inline void OPENOFDM_RX_REG_MULTI_RST_write(u32 Data) { 44 reg_write(OPENOFDM_RX_REG_MULTI_RST_ADDR, Data); 45 } 46 static inline void OPENOFDM_RX_REG_ENABLE_write(u32 Data) { 47 reg_write(OPENOFDM_RX_REG_ENABLE_ADDR, Data); 48 } 49 static inline void OPENOFDM_RX_REG_POWER_THRES_write(u32 Data) { 50 reg_write(OPENOFDM_RX_REG_POWER_THRES_ADDR, Data); 51 } 52 static inline void OPENOFDM_RX_REG_MIN_PLATEAU_write(u32 Data) { 53 reg_write(OPENOFDM_RX_REG_MIN_PLATEAU_ADDR, Data); 54 } 55 static inline void OPENOFDM_RX_REG_SOFT_DECODING_write(u32 Data) { 56 reg_write(OPENOFDM_RX_REG_SOFT_DECODING_ADDR, Data); 57 } 58 static const struct of_device_id dev_of_ids[] = { 59 { .compatible = "sdr,openofdm_rx", }, 60 {} 61 }; 62 MODULE_DEVICE_TABLE(of, dev_of_ids); 63 64 static struct openofdm_rx_driver_api openofdm_rx_driver_api_inst; 65 static struct openofdm_rx_driver_api *openofdm_rx_api = &openofdm_rx_driver_api_inst; 66 EXPORT_SYMBOL(openofdm_rx_api); 67 68 static inline u32 hw_init(enum openofdm_rx_mode mode){ 69 int err=0, i; 70 71 printk("%s hw_init mode %d\n", openofdm_rx_compatible_str, mode); 72 73 switch(mode) 74 { 75 case OPENOFDM_RX_TEST: 76 { 77 printk("%s hw_init mode OPENOFDM_RX_TEST\n", openofdm_rx_compatible_str); 78 break; 79 } 80 case OPENOFDM_RX_NORMAL: 81 { 82 printk("%s hw_init mode OPENOFDM_RX_NORMAL\n", openofdm_rx_compatible_str); 83 break; 84 } 85 default: 86 { 87 printk("%s hw_init mode %d is wrong!\n", openofdm_rx_compatible_str, mode); 88 err=1; 89 } 90 } 91 printk("%s hw_init input: power_thres %d dc_running_sum_th %d min_plateau %d\n", openofdm_rx_compatible_str, OPENOFDM_RX_POWER_THRES_INIT, OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT, OPENOFDM_RX_MIN_PLATEAU_INIT); 92 93 // 1) power threshold configuration and reset 94 openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write((OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT<<16)|OPENOFDM_RX_POWER_THRES_INIT); // turn on signal watchdog by default 95 openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(OPENOFDM_RX_MIN_PLATEAU_INIT); 96 openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|1); //bit1 enable soft decoding; bit31~16 max pkt length threshold 97 98 //rst 99 for (i=0;i<8;i++) 100 openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0); 101 for (i=0;i<32;i++) 102 openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF); 103 for (i=0;i<8;i++) 104 openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0); 105 106 printk("%s hw_init err %d\n", openofdm_rx_compatible_str, err); 107 108 return(err); 109 } 110 111 static int dev_probe(struct platform_device *pdev) 112 { 113 struct device_node *np = pdev->dev.of_node; 114 struct resource *io; 115 int err=1; 116 117 printk("\n"); 118 119 if (np) { 120 const struct of_device_id *match; 121 122 match = of_match_node(dev_of_ids, np); 123 if (match) { 124 printk("%s dev_probe match!\n", openofdm_rx_compatible_str); 125 err = 0; 126 } 127 } 128 129 if (err) 130 return err; 131 132 openofdm_rx_api->hw_init=hw_init; 133 134 openofdm_rx_api->reg_read=reg_read; 135 openofdm_rx_api->reg_write=reg_write; 136 137 openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write=OPENOFDM_RX_REG_MULTI_RST_write; 138 openofdm_rx_api->OPENOFDM_RX_REG_ENABLE_write=OPENOFDM_RX_REG_ENABLE_write; 139 openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write=OPENOFDM_RX_REG_POWER_THRES_write; 140 openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write=OPENOFDM_RX_REG_MIN_PLATEAU_write; 141 openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write=OPENOFDM_RX_REG_SOFT_DECODING_write; 142 143 /* Request and map I/O memory */ 144 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 145 base_addr = devm_ioremap_resource(&pdev->dev, io); 146 if (IS_ERR(base_addr)) 147 return PTR_ERR(base_addr); 148 149 printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", openofdm_rx_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); 150 printk("%s dev_probe base_addr 0x%08x\n", openofdm_rx_compatible_str,(u32)base_addr); 151 printk("%s dev_probe openofdm_rx_driver_api_inst 0x%08x\n", openofdm_rx_compatible_str, (u32)&openofdm_rx_driver_api_inst); 152 printk("%s dev_probe openofdm_rx_api 0x%08x\n", openofdm_rx_compatible_str, (u32)openofdm_rx_api); 153 154 printk("%s dev_probe succeed!\n", openofdm_rx_compatible_str); 155 156 err = hw_init(OPENOFDM_RX_NORMAL); 157 158 return err; 159 } 160 161 static int dev_remove(struct platform_device *pdev) 162 { 163 printk("\n"); 164 165 printk("%s dev_remove base_addr 0x%08x\n", openofdm_rx_compatible_str,(u32)base_addr); 166 printk("%s dev_remove openofdm_rx_driver_api_inst 0x%08x\n", openofdm_rx_compatible_str, (u32)&openofdm_rx_driver_api_inst); 167 printk("%s dev_remove openofdm_rx_api 0x%08x\n", openofdm_rx_compatible_str, (u32)openofdm_rx_api); 168 169 printk("%s dev_remove succeed!\n", openofdm_rx_compatible_str); 170 return 0; 171 } 172 173 static struct platform_driver dev_driver = { 174 .driver = { 175 .name = "sdr,openofdm_rx", 176 .owner = THIS_MODULE, 177 .of_match_table = dev_of_ids, 178 }, 179 .probe = dev_probe, 180 .remove = dev_remove, 181 }; 182 183 module_platform_driver(dev_driver); 184 185 MODULE_AUTHOR("Xianjun Jiao"); 186 MODULE_DESCRIPTION("sdr,openofdm_rx"); 187 MODULE_LICENSE("GPL v2"); 188