12ee67178SXianjun Jiao /* 22ee67178SXianjun Jiao * axi lite register access driver 32ee67178SXianjun Jiao * Xianjun jiao. [email protected]; [email protected] 42ee67178SXianjun Jiao */ 52ee67178SXianjun Jiao 62ee67178SXianjun Jiao #include <linux/bitops.h> 72ee67178SXianjun Jiao #include <linux/dmapool.h> 82ee67178SXianjun Jiao #include <linux/dma/xilinx_dma.h> 92ee67178SXianjun Jiao #include <linux/init.h> 102ee67178SXianjun Jiao #include <linux/interrupt.h> 112ee67178SXianjun Jiao #include <linux/io.h> 122ee67178SXianjun Jiao #include <linux/iopoll.h> 132ee67178SXianjun Jiao #include <linux/module.h> 142ee67178SXianjun Jiao #include <linux/of_address.h> 152ee67178SXianjun Jiao #include <linux/of_dma.h> 162ee67178SXianjun Jiao #include <linux/of_platform.h> 172ee67178SXianjun Jiao #include <linux/of_irq.h> 182ee67178SXianjun Jiao #include <linux/slab.h> 192ee67178SXianjun Jiao #include <linux/clk.h> 202ee67178SXianjun Jiao #include <linux/io-64-nonatomic-lo-hi.h> 212ee67178SXianjun Jiao #include <linux/delay.h> 222ee67178SXianjun Jiao 232ee67178SXianjun Jiao #include "../hw_def.h" 242ee67178SXianjun Jiao 252ee67178SXianjun Jiao static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design 262ee67178SXianjun Jiao 272ee67178SXianjun Jiao /* IO accessors */ 282ee67178SXianjun Jiao static inline u32 reg_read(u32 reg) 292ee67178SXianjun Jiao { 302ee67178SXianjun Jiao return ioread32(base_addr + reg); 312ee67178SXianjun Jiao } 322ee67178SXianjun Jiao 332ee67178SXianjun Jiao static inline void reg_write(u32 reg, u32 value) 342ee67178SXianjun Jiao { 352ee67178SXianjun Jiao iowrite32(value, base_addr + reg); 362ee67178SXianjun Jiao } 372ee67178SXianjun Jiao 382ee67178SXianjun Jiao static inline u32 OPENOFDM_RX_REG_STATE_HISTORY_read(void){ 392ee67178SXianjun Jiao return reg_read(OPENOFDM_RX_REG_STATE_HISTORY_ADDR); 402ee67178SXianjun Jiao } 412ee67178SXianjun Jiao 422ee67178SXianjun Jiao static inline void OPENOFDM_RX_REG_MULTI_RST_write(u32 Data) { 432ee67178SXianjun Jiao reg_write(OPENOFDM_RX_REG_MULTI_RST_ADDR, Data); 442ee67178SXianjun Jiao } 452ee67178SXianjun Jiao static inline void OPENOFDM_RX_REG_ENABLE_write(u32 Data) { 462ee67178SXianjun Jiao reg_write(OPENOFDM_RX_REG_ENABLE_ADDR, Data); 472ee67178SXianjun Jiao } 482ee67178SXianjun Jiao static inline void OPENOFDM_RX_REG_POWER_THRES_write(u32 Data) { 492ee67178SXianjun Jiao reg_write(OPENOFDM_RX_REG_POWER_THRES_ADDR, Data); 502ee67178SXianjun Jiao } 512ee67178SXianjun Jiao static inline void OPENOFDM_RX_REG_MIN_PLATEAU_write(u32 Data) { 522ee67178SXianjun Jiao reg_write(OPENOFDM_RX_REG_MIN_PLATEAU_ADDR, Data); 532ee67178SXianjun Jiao } 542ee67178SXianjun Jiao 552ee67178SXianjun Jiao static const struct of_device_id dev_of_ids[] = { 562ee67178SXianjun Jiao { .compatible = "sdr,openofdm_rx", }, 572ee67178SXianjun Jiao {} 582ee67178SXianjun Jiao }; 592ee67178SXianjun Jiao MODULE_DEVICE_TABLE(of, dev_of_ids); 602ee67178SXianjun Jiao 612ee67178SXianjun Jiao static struct openofdm_rx_driver_api openofdm_rx_driver_api_inst; 622ee67178SXianjun Jiao static struct openofdm_rx_driver_api *openofdm_rx_api = &openofdm_rx_driver_api_inst; 632ee67178SXianjun Jiao EXPORT_SYMBOL(openofdm_rx_api); 642ee67178SXianjun Jiao 652ee67178SXianjun Jiao static inline u32 hw_init(enum openofdm_rx_mode mode){ 66*4ecf49bbSJiao Xianjun int err=0, i; 672ee67178SXianjun Jiao 682ee67178SXianjun Jiao printk("%s hw_init mode %d\n", openofdm_rx_compatible_str, mode); 692ee67178SXianjun Jiao 702ee67178SXianjun Jiao switch(mode) 712ee67178SXianjun Jiao { 722ee67178SXianjun Jiao case OPENOFDM_RX_TEST: 732ee67178SXianjun Jiao { 742ee67178SXianjun Jiao printk("%s hw_init mode OPENOFDM_RX_TEST\n", openofdm_rx_compatible_str); 752ee67178SXianjun Jiao break; 762ee67178SXianjun Jiao } 772ee67178SXianjun Jiao case OPENOFDM_RX_NORMAL: 782ee67178SXianjun Jiao { 792ee67178SXianjun Jiao printk("%s hw_init mode OPENOFDM_RX_NORMAL\n", openofdm_rx_compatible_str); 802ee67178SXianjun Jiao openofdm_rx_api->power_thres = 0; 812ee67178SXianjun Jiao openofdm_rx_api->min_plateau = 100; 822ee67178SXianjun Jiao break; 832ee67178SXianjun Jiao } 842ee67178SXianjun Jiao default: 852ee67178SXianjun Jiao { 862ee67178SXianjun Jiao printk("%s hw_init mode %d is wrong!\n", openofdm_rx_compatible_str, mode); 872ee67178SXianjun Jiao err=1; 882ee67178SXianjun Jiao } 892ee67178SXianjun Jiao } 902ee67178SXianjun Jiao printk("%s hw_init input:\npower_thres %d\nmin_plateau %d\n", 912ee67178SXianjun Jiao openofdm_rx_compatible_str, 922ee67178SXianjun Jiao openofdm_rx_api->power_thres, openofdm_rx_api->min_plateau); 932ee67178SXianjun Jiao 942ee67178SXianjun Jiao // 1) power threshold configuration and reset 952ee67178SXianjun Jiao openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write(0); 962ee67178SXianjun Jiao openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(100); 972ee67178SXianjun Jiao 98*4ecf49bbSJiao Xianjun //rst 99*4ecf49bbSJiao Xianjun for (i=0;i<8;i++) 100*4ecf49bbSJiao Xianjun openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0); 101*4ecf49bbSJiao Xianjun for (i=0;i<32;i++) 1022ee67178SXianjun Jiao openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF); 103*4ecf49bbSJiao Xianjun for (i=0;i<8;i++) 1042ee67178SXianjun Jiao openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0); 1052ee67178SXianjun Jiao 1062ee67178SXianjun Jiao printk("%s hw_init err %d\n", openofdm_rx_compatible_str, err); 1072ee67178SXianjun Jiao 1082ee67178SXianjun Jiao reg_write(4*4,1);//enable soft decoding 1092ee67178SXianjun Jiao return(err); 1102ee67178SXianjun Jiao } 1112ee67178SXianjun Jiao 1122ee67178SXianjun Jiao static int dev_probe(struct platform_device *pdev) 1132ee67178SXianjun Jiao { 1142ee67178SXianjun Jiao struct device_node *np = pdev->dev.of_node; 1152ee67178SXianjun Jiao struct resource *io; 1162ee67178SXianjun Jiao int err=1; 1172ee67178SXianjun Jiao 1182ee67178SXianjun Jiao printk("\n"); 1192ee67178SXianjun Jiao 1202ee67178SXianjun Jiao if (np) { 1212ee67178SXianjun Jiao const struct of_device_id *match; 1222ee67178SXianjun Jiao 1232ee67178SXianjun Jiao match = of_match_node(dev_of_ids, np); 1242ee67178SXianjun Jiao if (match) { 1252ee67178SXianjun Jiao printk("%s dev_probe match!\n", openofdm_rx_compatible_str); 1262ee67178SXianjun Jiao err = 0; 1272ee67178SXianjun Jiao } 1282ee67178SXianjun Jiao } 1292ee67178SXianjun Jiao 1302ee67178SXianjun Jiao if (err) 1312ee67178SXianjun Jiao return err; 1322ee67178SXianjun Jiao 1332ee67178SXianjun Jiao openofdm_rx_api->hw_init=hw_init; 1342ee67178SXianjun Jiao 1352ee67178SXianjun Jiao openofdm_rx_api->reg_read=reg_read; 1362ee67178SXianjun Jiao openofdm_rx_api->reg_write=reg_write; 1372ee67178SXianjun Jiao 1382ee67178SXianjun Jiao openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write=OPENOFDM_RX_REG_MULTI_RST_write; 1392ee67178SXianjun Jiao openofdm_rx_api->OPENOFDM_RX_REG_ENABLE_write=OPENOFDM_RX_REG_ENABLE_write; 1402ee67178SXianjun Jiao openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write=OPENOFDM_RX_REG_POWER_THRES_write; 1412ee67178SXianjun Jiao openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write=OPENOFDM_RX_REG_MIN_PLATEAU_write; 1422ee67178SXianjun Jiao 1432ee67178SXianjun Jiao /* Request and map I/O memory */ 1442ee67178SXianjun Jiao io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1452ee67178SXianjun Jiao base_addr = devm_ioremap_resource(&pdev->dev, io); 1462ee67178SXianjun Jiao if (IS_ERR(base_addr)) 1472ee67178SXianjun Jiao return PTR_ERR(base_addr); 1482ee67178SXianjun Jiao 1492ee67178SXianjun Jiao printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", openofdm_rx_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); 1502ee67178SXianjun Jiao printk("%s dev_probe base_addr 0x%08x\n", openofdm_rx_compatible_str,(u32)base_addr); 1512ee67178SXianjun Jiao printk("%s dev_probe openofdm_rx_driver_api_inst 0x%08x\n", openofdm_rx_compatible_str, (u32)&openofdm_rx_driver_api_inst); 1522ee67178SXianjun Jiao printk("%s dev_probe openofdm_rx_api 0x%08x\n", openofdm_rx_compatible_str, (u32)openofdm_rx_api); 1532ee67178SXianjun Jiao 1542ee67178SXianjun Jiao printk("%s dev_probe succeed!\n", openofdm_rx_compatible_str); 1552ee67178SXianjun Jiao 1562ee67178SXianjun Jiao err = hw_init(OPENOFDM_RX_NORMAL); 1572ee67178SXianjun Jiao 1582ee67178SXianjun Jiao return err; 1592ee67178SXianjun Jiao } 1602ee67178SXianjun Jiao 1612ee67178SXianjun Jiao static int dev_remove(struct platform_device *pdev) 1622ee67178SXianjun Jiao { 1632ee67178SXianjun Jiao printk("\n"); 1642ee67178SXianjun Jiao 1652ee67178SXianjun Jiao printk("%s dev_remove base_addr 0x%08x\n", openofdm_rx_compatible_str,(u32)base_addr); 1662ee67178SXianjun Jiao printk("%s dev_remove openofdm_rx_driver_api_inst 0x%08x\n", openofdm_rx_compatible_str, (u32)&openofdm_rx_driver_api_inst); 1672ee67178SXianjun Jiao printk("%s dev_remove openofdm_rx_api 0x%08x\n", openofdm_rx_compatible_str, (u32)openofdm_rx_api); 1682ee67178SXianjun Jiao 1692ee67178SXianjun Jiao printk("%s dev_remove succeed!\n", openofdm_rx_compatible_str); 1702ee67178SXianjun Jiao return 0; 1712ee67178SXianjun Jiao } 1722ee67178SXianjun Jiao 1732ee67178SXianjun Jiao static struct platform_driver dev_driver = { 1742ee67178SXianjun Jiao .driver = { 1752ee67178SXianjun Jiao .name = "sdr,openofdm_rx", 1762ee67178SXianjun Jiao .owner = THIS_MODULE, 1772ee67178SXianjun Jiao .of_match_table = dev_of_ids, 1782ee67178SXianjun Jiao }, 1792ee67178SXianjun Jiao .probe = dev_probe, 1802ee67178SXianjun Jiao .remove = dev_remove, 1812ee67178SXianjun Jiao }; 1822ee67178SXianjun Jiao 1832ee67178SXianjun Jiao module_platform_driver(dev_driver); 1842ee67178SXianjun Jiao 1852ee67178SXianjun Jiao MODULE_AUTHOR("Xianjun Jiao"); 1862ee67178SXianjun Jiao MODULE_DESCRIPTION("sdr,openofdm_rx"); 1872ee67178SXianjun Jiao MODULE_LICENSE("GPL v2"); 188