12ee67178SXianjun Jiao /* 2a3cbb385SJiao Xianjun * Author: Xianjun jiao, Michael Mehari, Wei Liu 3a3cbb385SJiao Xianjun * SPDX-FileCopyrightText: 2019 UGent 4a6085186SLina Ceballos * SPDX-License-Identifier: AGPL-3.0-or-later 52ee67178SXianjun Jiao */ 62ee67178SXianjun Jiao 72ee67178SXianjun Jiao #include <linux/bitops.h> 82ee67178SXianjun Jiao #include <linux/dmapool.h> 92ee67178SXianjun Jiao #include <linux/dma/xilinx_dma.h> 102ee67178SXianjun Jiao #include <linux/init.h> 112ee67178SXianjun Jiao #include <linux/interrupt.h> 122ee67178SXianjun Jiao #include <linux/io.h> 132ee67178SXianjun Jiao #include <linux/iopoll.h> 142ee67178SXianjun Jiao #include <linux/module.h> 152ee67178SXianjun Jiao #include <linux/of_address.h> 162ee67178SXianjun Jiao #include <linux/of_dma.h> 172ee67178SXianjun Jiao #include <linux/of_platform.h> 182ee67178SXianjun Jiao #include <linux/of_irq.h> 192ee67178SXianjun Jiao #include <linux/slab.h> 202ee67178SXianjun Jiao #include <linux/clk.h> 212ee67178SXianjun Jiao #include <linux/io-64-nonatomic-lo-hi.h> 222ee67178SXianjun Jiao #include <linux/delay.h> 232ee67178SXianjun Jiao 242ee67178SXianjun Jiao #include "../hw_def.h" 252ee67178SXianjun Jiao 262ee67178SXianjun Jiao static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design 272ee67178SXianjun Jiao 282ee67178SXianjun Jiao /* IO accessors */ 292ee67178SXianjun Jiao static inline u32 reg_read(u32 reg) 302ee67178SXianjun Jiao { 312ee67178SXianjun Jiao return ioread32(base_addr + reg); 322ee67178SXianjun Jiao } 332ee67178SXianjun Jiao 342ee67178SXianjun Jiao static inline void reg_write(u32 reg, u32 value) 352ee67178SXianjun Jiao { 362ee67178SXianjun Jiao iowrite32(value, base_addr + reg); 372ee67178SXianjun Jiao } 382ee67178SXianjun Jiao 392ee67178SXianjun Jiao static inline u32 OPENOFDM_RX_REG_STATE_HISTORY_read(void){ 402ee67178SXianjun Jiao return reg_read(OPENOFDM_RX_REG_STATE_HISTORY_ADDR); 412ee67178SXianjun Jiao } 422ee67178SXianjun Jiao 432ee67178SXianjun Jiao static inline void OPENOFDM_RX_REG_MULTI_RST_write(u32 Data) { 442ee67178SXianjun Jiao reg_write(OPENOFDM_RX_REG_MULTI_RST_ADDR, Data); 452ee67178SXianjun Jiao } 462ee67178SXianjun Jiao static inline void OPENOFDM_RX_REG_ENABLE_write(u32 Data) { 472ee67178SXianjun Jiao reg_write(OPENOFDM_RX_REG_ENABLE_ADDR, Data); 482ee67178SXianjun Jiao } 492ee67178SXianjun Jiao static inline void OPENOFDM_RX_REG_POWER_THRES_write(u32 Data) { 502ee67178SXianjun Jiao reg_write(OPENOFDM_RX_REG_POWER_THRES_ADDR, Data); 512ee67178SXianjun Jiao } 522ee67178SXianjun Jiao static inline void OPENOFDM_RX_REG_MIN_PLATEAU_write(u32 Data) { 532ee67178SXianjun Jiao reg_write(OPENOFDM_RX_REG_MIN_PLATEAU_ADDR, Data); 542ee67178SXianjun Jiao } 55e1c2ba09SXianjun Jiao static inline void OPENOFDM_RX_REG_SOFT_DECODING_write(u32 Data) { 56e1c2ba09SXianjun Jiao reg_write(OPENOFDM_RX_REG_SOFT_DECODING_ADDR, Data); 57e1c2ba09SXianjun Jiao } 58e273351bSXianjun Jiao static inline void OPENOFDM_RX_REG_FFT_WIN_SHIFT_write(u32 Data) { 59e273351bSXianjun Jiao reg_write(OPENOFDM_RX_REG_FFT_WIN_SHIFT_ADDR, Data); 60e273351bSXianjun Jiao } 612ee67178SXianjun Jiao static const struct of_device_id dev_of_ids[] = { 622ee67178SXianjun Jiao { .compatible = "sdr,openofdm_rx", }, 632ee67178SXianjun Jiao {} 642ee67178SXianjun Jiao }; 652ee67178SXianjun Jiao MODULE_DEVICE_TABLE(of, dev_of_ids); 662ee67178SXianjun Jiao 672ee67178SXianjun Jiao static struct openofdm_rx_driver_api openofdm_rx_driver_api_inst; 682ee67178SXianjun Jiao static struct openofdm_rx_driver_api *openofdm_rx_api = &openofdm_rx_driver_api_inst; 692ee67178SXianjun Jiao EXPORT_SYMBOL(openofdm_rx_api); 702ee67178SXianjun Jiao 712ee67178SXianjun Jiao static inline u32 hw_init(enum openofdm_rx_mode mode){ 724ecf49bbSJiao Xianjun int err=0, i; 732ee67178SXianjun Jiao 742ee67178SXianjun Jiao printk("%s hw_init mode %d\n", openofdm_rx_compatible_str, mode); 752ee67178SXianjun Jiao 762ee67178SXianjun Jiao switch(mode) 772ee67178SXianjun Jiao { 782ee67178SXianjun Jiao case OPENOFDM_RX_TEST: 792ee67178SXianjun Jiao { 802ee67178SXianjun Jiao printk("%s hw_init mode OPENOFDM_RX_TEST\n", openofdm_rx_compatible_str); 812ee67178SXianjun Jiao break; 822ee67178SXianjun Jiao } 832ee67178SXianjun Jiao case OPENOFDM_RX_NORMAL: 842ee67178SXianjun Jiao { 852ee67178SXianjun Jiao printk("%s hw_init mode OPENOFDM_RX_NORMAL\n", openofdm_rx_compatible_str); 862ee67178SXianjun Jiao break; 872ee67178SXianjun Jiao } 882ee67178SXianjun Jiao default: 892ee67178SXianjun Jiao { 902ee67178SXianjun Jiao printk("%s hw_init mode %d is wrong!\n", openofdm_rx_compatible_str, mode); 912ee67178SXianjun Jiao err=1; 922ee67178SXianjun Jiao } 932ee67178SXianjun Jiao } 9412b235cdSXianjun Jiao printk("%s hw_init input: power_thres %d dc_running_sum_th %d min_plateau %d\n", openofdm_rx_compatible_str, OPENOFDM_RX_POWER_THRES_INIT, OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT, OPENOFDM_RX_MIN_PLATEAU_INIT); 952ee67178SXianjun Jiao 962ee67178SXianjun Jiao // 1) power threshold configuration and reset 97585a5601SXianjun Jiao openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write((OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT<<16)|OPENOFDM_RX_POWER_THRES_INIT); // turn on signal watchdog by default 98585a5601SXianjun Jiao openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(OPENOFDM_RX_MIN_PLATEAU_INIT); 9926825b8bSXianjun Jiao openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|(OPENWIFI_MIN_SIGNAL_LEN_TH<<12)|1); //bit1 enable soft decoding; bit15~12 min pkt length threshold; bit31~16 max pkt length threshold 100*2a5da37cSXianjun Jiao openofdm_rx_api->OPENOFDM_RX_REG_FFT_WIN_SHIFT_write((OPENOFDM_RX_SMALL_EQ_OUT_COUNTER_TH<<4)|OPENOFDM_RX_FFT_WIN_SHIFT_INIT); 1012ee67178SXianjun Jiao 1024ecf49bbSJiao Xianjun //rst 1034ecf49bbSJiao Xianjun for (i=0;i<8;i++) 1044ecf49bbSJiao Xianjun openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0); 1054ecf49bbSJiao Xianjun for (i=0;i<32;i++) 1062ee67178SXianjun Jiao openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF); 1074ecf49bbSJiao Xianjun for (i=0;i<8;i++) 1082ee67178SXianjun Jiao openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0); 1092ee67178SXianjun Jiao 1102ee67178SXianjun Jiao printk("%s hw_init err %d\n", openofdm_rx_compatible_str, err); 1112ee67178SXianjun Jiao 1122ee67178SXianjun Jiao return(err); 1132ee67178SXianjun Jiao } 1142ee67178SXianjun Jiao 1152ee67178SXianjun Jiao static int dev_probe(struct platform_device *pdev) 1162ee67178SXianjun Jiao { 1172ee67178SXianjun Jiao struct device_node *np = pdev->dev.of_node; 1182ee67178SXianjun Jiao struct resource *io; 1192ee67178SXianjun Jiao int err=1; 1202ee67178SXianjun Jiao 1212ee67178SXianjun Jiao printk("\n"); 1222ee67178SXianjun Jiao 1232ee67178SXianjun Jiao if (np) { 1242ee67178SXianjun Jiao const struct of_device_id *match; 1252ee67178SXianjun Jiao 1262ee67178SXianjun Jiao match = of_match_node(dev_of_ids, np); 1272ee67178SXianjun Jiao if (match) { 1282ee67178SXianjun Jiao printk("%s dev_probe match!\n", openofdm_rx_compatible_str); 1292ee67178SXianjun Jiao err = 0; 1302ee67178SXianjun Jiao } 1312ee67178SXianjun Jiao } 1322ee67178SXianjun Jiao 1332ee67178SXianjun Jiao if (err) 1342ee67178SXianjun Jiao return err; 1352ee67178SXianjun Jiao 1362ee67178SXianjun Jiao openofdm_rx_api->hw_init=hw_init; 1372ee67178SXianjun Jiao 1382ee67178SXianjun Jiao openofdm_rx_api->reg_read=reg_read; 1392ee67178SXianjun Jiao openofdm_rx_api->reg_write=reg_write; 1402ee67178SXianjun Jiao 1412ee67178SXianjun Jiao openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write=OPENOFDM_RX_REG_MULTI_RST_write; 1422ee67178SXianjun Jiao openofdm_rx_api->OPENOFDM_RX_REG_ENABLE_write=OPENOFDM_RX_REG_ENABLE_write; 1432ee67178SXianjun Jiao openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write=OPENOFDM_RX_REG_POWER_THRES_write; 1442ee67178SXianjun Jiao openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write=OPENOFDM_RX_REG_MIN_PLATEAU_write; 145e1c2ba09SXianjun Jiao openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write=OPENOFDM_RX_REG_SOFT_DECODING_write; 146e273351bSXianjun Jiao openofdm_rx_api->OPENOFDM_RX_REG_FFT_WIN_SHIFT_write=OPENOFDM_RX_REG_FFT_WIN_SHIFT_write; 1472ee67178SXianjun Jiao 1482ee67178SXianjun Jiao /* Request and map I/O memory */ 1492ee67178SXianjun Jiao io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1502ee67178SXianjun Jiao base_addr = devm_ioremap_resource(&pdev->dev, io); 1512ee67178SXianjun Jiao if (IS_ERR(base_addr)) 1522ee67178SXianjun Jiao return PTR_ERR(base_addr); 1532ee67178SXianjun Jiao 1542ee67178SXianjun Jiao printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", openofdm_rx_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); 1552ee67178SXianjun Jiao printk("%s dev_probe base_addr 0x%08x\n", openofdm_rx_compatible_str,(u32)base_addr); 1562ee67178SXianjun Jiao printk("%s dev_probe openofdm_rx_driver_api_inst 0x%08x\n", openofdm_rx_compatible_str, (u32)&openofdm_rx_driver_api_inst); 1572ee67178SXianjun Jiao printk("%s dev_probe openofdm_rx_api 0x%08x\n", openofdm_rx_compatible_str, (u32)openofdm_rx_api); 1582ee67178SXianjun Jiao 1592ee67178SXianjun Jiao printk("%s dev_probe succeed!\n", openofdm_rx_compatible_str); 1602ee67178SXianjun Jiao 1612ee67178SXianjun Jiao err = hw_init(OPENOFDM_RX_NORMAL); 1622ee67178SXianjun Jiao 1632ee67178SXianjun Jiao return err; 1642ee67178SXianjun Jiao } 1652ee67178SXianjun Jiao 1662ee67178SXianjun Jiao static int dev_remove(struct platform_device *pdev) 1672ee67178SXianjun Jiao { 1682ee67178SXianjun Jiao printk("\n"); 1692ee67178SXianjun Jiao 1702ee67178SXianjun Jiao printk("%s dev_remove base_addr 0x%08x\n", openofdm_rx_compatible_str,(u32)base_addr); 1712ee67178SXianjun Jiao printk("%s dev_remove openofdm_rx_driver_api_inst 0x%08x\n", openofdm_rx_compatible_str, (u32)&openofdm_rx_driver_api_inst); 1722ee67178SXianjun Jiao printk("%s dev_remove openofdm_rx_api 0x%08x\n", openofdm_rx_compatible_str, (u32)openofdm_rx_api); 1732ee67178SXianjun Jiao 1742ee67178SXianjun Jiao printk("%s dev_remove succeed!\n", openofdm_rx_compatible_str); 1752ee67178SXianjun Jiao return 0; 1762ee67178SXianjun Jiao } 1772ee67178SXianjun Jiao 1782ee67178SXianjun Jiao static struct platform_driver dev_driver = { 1792ee67178SXianjun Jiao .driver = { 1802ee67178SXianjun Jiao .name = "sdr,openofdm_rx", 1812ee67178SXianjun Jiao .owner = THIS_MODULE, 1822ee67178SXianjun Jiao .of_match_table = dev_of_ids, 1832ee67178SXianjun Jiao }, 1842ee67178SXianjun Jiao .probe = dev_probe, 1852ee67178SXianjun Jiao .remove = dev_remove, 1862ee67178SXianjun Jiao }; 1872ee67178SXianjun Jiao 1882ee67178SXianjun Jiao module_platform_driver(dev_driver); 1892ee67178SXianjun Jiao 1902ee67178SXianjun Jiao MODULE_AUTHOR("Xianjun Jiao"); 1912ee67178SXianjun Jiao MODULE_DESCRIPTION("sdr,openofdm_rx"); 1922ee67178SXianjun Jiao MODULE_LICENSE("GPL v2"); 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