1ce2baff7SHavingaThijs<!-- 2ce2baff7SHavingaThijsAuthor: Thijs Havinga 3ce2baff7SHavingaThijsSPDX-FileCopyrightText: 2019 UGent 4ce2baff7SHavingaThijsSPDX-License-Identifier: AGPL-3.0-or-later 5ce2baff7SHavingaThijs--> 65025d47bSJiao Xianjun 75025d47bSJiao XianjunFCCM2023 Poster: [Thijs Havinga, et al. Accelerating FPGA-Based Wi-Fi Transceiver Design and Prototyping by High-Level Synthesis](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Thijs-FCCM2023-poster.jpg) 85025d47bSJiao Xianjun 9*c11f6dddSThijs Havinga[Longer/detailed info about the poster](https://arxiv.org/abs/2305.13351) 10ce2baff7SHavingaThijs 11ce2baff7SHavingaThijsIn order to speed up or ease FPGA development, it is possible to use High-Level Synthesis (HLS) for creating core baseband processing modules of openwifi. We have already programmed the receiver modules channel estimation and equalization in C++ and converted to Verilog using Vitis HLS. In order to use openwifi with these HLS modules, follow the [build instructions](#build-instructions). 12ce2baff7SHavingaThijsIn order to modify these modules within Vitis HLS, follow [the instructions below](#modify-the-code-using-vitis-hls). 13ce2baff7SHavingaThijs 14ce2baff7SHavingaThijs## Build instructions 15ce2baff7SHavingaThijs 16ce2baff7SHavingaThijsFollow the [Build FPGA](https://github.com/open-sdr/openwifi-hw#build-fpga) instructions till before generating ip_repo. In order to switch to the HLS-version of openofdm_rx, use the following commands: 17ce2baff7SHavingaThijs 18ce2baff7SHavingaThijs``` 19ce2baff7SHavingaThijscd ip/openofdm_rx 20ce2baff7SHavingaThijsgit checkout dot11zynq_hls 21ce2baff7SHavingaThijs``` 22ce2baff7SHavingaThijs 23ce2baff7SHavingaThijsNow continue with the instructions. Before generating the bitstream, update the openofdm_rx IP by making sure it is selected under "IP Status" and click "Upgrade Selected". Afterwards, continue with the instructions to generate the bitstream. 24ce2baff7SHavingaThijs 25ce2baff7SHavingaThijs## Modify the code using Vitis HLS 26ce2baff7SHavingaThijsWhen in the `openwifi-hw` folder, make sure to run: 27ce2baff7SHavingaThijs``` 28ce2baff7SHavingaThijs./get_ip_openofdm_rx.sh 29ce2baff7SHavingaThijscd ip/openofdm_rx 30ce2baff7SHavingaThijsgit checkout dot11zynq_hls 31ce2baff7SHavingaThijs``` 32ce2baff7SHavingaThijsThen start Vitis HLS and create a new project. Import either all source files (except those ending on '_test.cpp') in the [ch_gain_cal](https://github.com/open-sdr/openofdm/tree/dot11zynq_hls/hls/ch_gain_cal) or [equalizer](https://github.com/open-sdr/openofdm/tree/dot11zynq_hls/hls/equalizer) folder to modify the channel estimation or equalizer module, respectively. Choose either 'equalizer' or 'ch_gain_cal' as top-level module. Next, select `equalizer_test.cpp` or `ch_gain_cal_test.cpp` as testbench file. In 'Part selection', select the right part corresponding to your board. 33ce2baff7SHavingaThijs 34ce2baff7SHavingaThijsAfter modifying the code and making sure C simulation and cosimulation is running fine, select 'Export RTL', which will generate a ZIP file with a folder `hdl/verilog` containing the generated Verilog files. Replace the current folder `openwifi-hw/ip/openofdm_rx/hls/equalizer/hdl/verilog/` (or `.../ch_gain_cal/hdl/verilog`) with this folder and change the `openofdm_rx.tcl` file to include the newly generated Verilog files. See [here](https://github.com/open-sdr/openofdm/blob/dot11zynq_hls/openofdm_rx.tcl#L268) for an example. If you modified the top-level function arguments, you will need to interface them accordingly in [dot11.v](https://github.com/open-sdr/openofdm/blob/dot11zynq_hls/verilog/dot11.v). 35ce2baff7SHavingaThijs 36ce2baff7SHavingaThijsNow follow the [Build FPGA](https://github.com/open-sdr/openwifi-hw#build-fpga) instructions, starting at the step "Generate ip_repo for the top level FPGA project". It will then use the modified .tcl file to include the correct files for your modified HLS module and build the FPGA using it. 37ce2baff7SHavingaThijs 38ce2baff7SHavingaThijsA similar approach can be followed to create other HLS modules, where you would need to execute these steps in the folder of the IP to be modified and integrate the modules in the corresponding top-level Verilog file. 39
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