1a6085186SLina Ceballos<!-- 2bf0f292dSJiao XianjunAuthor: Xianjun jiao 334772970SJiao XianjunSPDX-FileCopyrightText: 2019 UGent 4a6085186SLina CeballosSPDX-License-Identifier: AGPL-3.0-or-later 5a6085186SLina Ceballos--> 6a6085186SLina Ceballos 79e514886SXianjun JiaoApplication notes collect many small topics about using openwifi in different scenarios/modes. 89e514886SXianjun Jiao 99e514886SXianjun Jiao- [Use openwifi on the w-iLab.t testbed remotely](https://doc.ilabt.imec.be/ilabt/wilab/tutorials/openwifi.html) 109e514886SXianjun Jiao- [Communication between two SDR boards under AP and client mode](ap-client-two-sdr.md) 119e514886SXianjun Jiao- [Communication between two SDR boards under ad-hoc mode](ad-hoc-two-sdr.md) 1222dd0cc4SXianjun Jiao- [From CSI (Channel State Information) to CSI (Chip State Information)](csi.md) 13a4eb2001SXianjun Jiao- [WiFi CSI radar via self CSI capturing](radar-self-csi.md) 14b1bb66b0SJiao Xianjun- [Capture IQ sample, AGC gain, RSSI with many types of trigger condition](iq.md) 1523ba65e4SXianjun Jiao- [Capture dual antenna TX/RX IQ for multi-purpose (capture collision)](iq_2ant.md) 167eea2988SXianjun Jiao- [WiFi packet, CSI and IQ sample self loopback test (over-the-air and FPGA internal)](packet-iq-self-loopback-test.md) 17672df6f0SXianjun Jiao- [IEEE 802.11n (Wi-Fi 4)](ieee80211n.md) 18317bf9ddSJiao Xianjun- [802.11 packet injection and fuzzing](inject_80211.md) 19d14d06e5SXianjun Jiao- [CSI fuzzer](csi_fuzzer.md) 2017cfeb0bSXianjun Jiao- [Access counter/statistics in FPGA](perf_counter.md) 2117cfeb0bSXianjun Jiao- [Access counter/statistics in driver](driver_stat.md) 2290a96182SXianjun Jiao- [Frequent/usual trick on controlling Gain/Att/Frequency/CCA/LBT/CSMA/CW/Sensitivity/etc](frequent_trick.md) 2340773b78SXianjun Jiao- [Driver and FPGA dynamic reloading](drv_fpga_dynamic_loading.md) 24*ecbb2314SJiao Xianjun- [owfuzz: a WiFi protocol fuzzing tool using openwifi.](https://github.com/alipay/WiFi-Protocol-Fuzzing-Tool) [[**Vulnerabilities**]](https://github.com/alipay/Owfuzz#discovered-vulnerabilities) 25ce2baff7SHavingaThijs- [Build FPGA with High-Level Synthesis modules](hls.md) 26