1da2a8350SJiao Xianjun# Openwifi document 22ee67178SXianjun Jiao<img src="./openwifi-detail.jpg" width="1100"> 32ee67178SXianjun Jiao 44f977aa9SJiao XianjunAbove figure shows software and hardware/FPGA modules that compose the openwifi design. The module name is equal/similar to the source code file name. Driver module source codes are in openwifi/driver/. FPGA module source codes are in openwifi-hw repository. The user space tool sdrctl source code are in openwifi/user_space/sdrctl_src/. 52ee67178SXianjun Jiao 6da2a8350SJiao Xianjun- [Driver and software overall principle](#Driver-and-software-overall-principle) 710d539beSJiao Xianjun- [sdrctl command](#sdrctl-command) 8da2a8350SJiao Xianjun- [Rx packet flow and filtering config](#Rx-packet-flow-and-filtering-config) 9da2a8350SJiao Xianjun- [Tx packet flow and config](#Tx-packet-flow-and-config) 10da2a8350SJiao Xianjun- [Regulation and channel config](#Regulation-and-channel-config) 11da2a8350SJiao Xianjun- [Analog and digital frequency design](#Analog-and-digital-frequency-design) 12da2a8350SJiao Xianjun- [Debug methods](#Debug-methods) 13*bf6ebc28SJiao Xianjun- [Application notes](app_notes) 145f436b3cSJiao Xianjun 15da2a8350SJiao Xianjun## Driver and software overall principle 165f436b3cSJiao Xianjun 174f977aa9SJiao Xianjun[Linux mac80211 subsystem](https://www.kernel.org/doc/html/v4.16/driver-api/80211/mac80211.html), as a part of [Linux wireless](https://wireless.wiki.kernel.org/en/developers/documentation/mac80211), defines a set of APIs ([ieee80211_ops](https://www.kernel.org/doc/html/v4.9/80211/mac80211.html#c.ieee80211_ops)) to rule the Wi-Fi chip driver behavior. SoftMAC Wi-Fi chip driver implements (subset of) those APIs. That is why Linux can support so many Wi-Fi chips of different chip vendors. 185f436b3cSJiao Xianjun 195f436b3cSJiao Xianjunopenwifi driver (sdr.c) implements following APIs of ieee80211_ops: 205f436b3cSJiao Xianjun- **tx**. It is called when upper layer has a packet to send 215f436b3cSJiao Xianjun- **start**. It is called when NIC up. (ifconfig sdr0 up) 225f436b3cSJiao Xianjun- **stop**. It is called when NIC down. (ifconfig sdr0 down) 235f436b3cSJiao Xianjun- **add_interface**. It is called when NIC is created 245f436b3cSJiao Xianjun- **remove_interface**. It is called when NIC is deleted 255f436b3cSJiao Xianjun- **config**. It is called when upper layer wants to change channel/frequency (like the scan operation) 265f436b3cSJiao Xianjun- **bss_info_changed**. It is called when upper layer believe some BSS parameters need to be changed (BSSID, TX power, beacon interval, etc) 275f436b3cSJiao Xianjun- **conf_tx**. It is called when upper layer needs to config/change some tx parameters (AIFS, CW_MIN, CW_MAX, TXOP, etc) 286a6fa9b4Sweiliu1011- **prepare_multicast**. It is called when upper layer needs to prepare multicast, currently only a empty function hook is present. 294ecf49bbSJiao Xianjun- **configure_filter**. It is called when upper layer wants to config/change the [frame filtering](#Rx-packet-flow-and-filtering-config) rule in FPGA. 305f436b3cSJiao Xianjun- **rfkill_poll**. It is called when upper layer wants to know the RF status (ON/OFF). 315f436b3cSJiao Xianjun- **get_tsf**. It is called when upper layer wants to get 64bit FPGA timer value (TSF - Timing synchronization function) 325f436b3cSJiao Xianjun- **set_tsf**. It is called when upper layer wants to set 64bit FPGA timer value 335f436b3cSJiao Xianjun- **reset_tsf**. It is called when upper layer wants to reset 64bit FPGA timer value 345f436b3cSJiao Xianjun- **set_rts_threshold**. It is called when upper layer wants to change the threshold (packet length) for turning on RTS mechanism 355f436b3cSJiao Xianjun- **testmode_cmd**. It is called when upper layer has test command for us. [sdrctl command](#sdrctl-command) message is handled by this function. 365f436b3cSJiao Xianjun 376a6fa9b4Sweiliu1011Above APIs are called by upper layer (Linux mac80211 subsystem). When they are called, the driver (sdr.c) will do necessary job over SDR platform. If necessary, the driver will call other component drivers, like tx_intf_api/rx_intf_api/openofdm_tx_api/openofdm_rx_api/xpu_api, for help. 385f436b3cSJiao Xianjun 394f977aa9SJiao XianjunAfter receiving a packet from the air, FPGA will raise interrupt (if the frame filtering rule allows) to Linux, then the function openwifi_rx_interrupt() of openwifi driver (sdr.c) will be triggered. In that function, ieee80211_rx_irqsafe() API is used to give the packet and related information (timestamp, rssi, etc) to upper layer. 4010d539beSJiao Xianjun 416a6fa9b4Sweiliu1011The packet sending is initiated by upper layer. After the packet is sent by the driver over FPGA to the air, the upper layer will expect a sending report from the driver. Each time FPGA sends a packet, an interrupt will be raised to Linux and trigger openwifi_tx_interrupt(). This function will report the sending result (failed? succeeded? number of retransmissions, etc.) to upper layer via ieee80211_tx_status_irqsafe() API. 425f436b3cSJiao Xianjun 435f436b3cSJiao Xianjun## sdrctl command 442ee67178SXianjun Jiao 4562591d26Sweiliu1011Besides the Linux native Wi-Fi control programs, such as ifconfig/iw/iwconfig/iwlist/wpa_supplicant/hostapd/etc, openwifi offers a user space tool sdrctl to access openwifi specific functionalities, such as time sharing of the interface between two network slices, you may find more details of the slicing mechanism [here](https://doc.ilabt.imec.be/ilabt/wilab/tutorials/openwifi.html#sdr-tx-time-slicing). 4662591d26Sweiliu1011 4762591d26Sweiliu1011sdrctl is implemented as nl80211 testmode command and communicates with openwifi driver (function openwifi_testmode_cmd() in sdr.c) via Linux nl80211--cfg80211--mac80211 path 482ee67178SXianjun Jiao 49da2a8350SJiao Xianjun### Get and set a parameter 502ee67178SXianjun Jiao``` 512ee67178SXianjun Jiaosdrctl dev sdr0 get para_name 522ee67178SXianjun Jiaosdrctl dev sdr0 set para_name value 532ee67178SXianjun Jiao``` 5462591d26Sweiliu1011para_name|meaning|comment 552ee67178SXianjun Jiao---------|-------|---- 564ecf49bbSJiao Xianjunslice_idx|the slice that will be set/get|0~3. After finishing all slice config, **set slice_idx to 4** to synchronize all slices. Otherwize the start/end of different slices have different actual time 574ecf49bbSJiao Xianjunaddr|target MAC address of tx slice_idx|32bit. for address 6c:fd:b9:4c:b1:c1, you set b94cb1c1 584ecf49bbSJiao Xianjunslice_total|tx slice_idx cycle length in us|for length 50ms, you set 49999 594ecf49bbSJiao Xianjunslice_start|tx slice_idx cycle start time in us|for start at 10ms, you set 10000 604ecf49bbSJiao Xianjunslice_end| tx slice_idx cycle end time in us|for end at 40ms, you set 39999 61e63d1ec3SXianjun Jiaotsf| sets TSF value| it requires two values "high_TSF low_TSF". Decimal 622ee67178SXianjun Jiao 63da2a8350SJiao Xianjun### Get and set a register of a module 642ee67178SXianjun Jiao``` 652ee67178SXianjun Jiaosdrctl dev sdr0 get reg module_name reg_idx 662ee67178SXianjun Jiaosdrctl dev sdr0 set reg module_name reg_idx reg_value 672ee67178SXianjun Jiao``` 681bbbbdc7SJiao Xianjunmodule_name refers to the name of driver functionality, can be drv_rx/drv_tx/drv_xpu. Related registers are defined in sdr.h (drv_rx_reg_val/drv_tx_reg_val/drv_xpu_reg_val) 692ee67178SXianjun Jiao 701bbbbdc7SJiao Xianjunmodule_name rf/rx_intf/tx_intf/rx/tx/xpu refer to RF (ad9xxx front-end) and FPGA modules (rx_intf/tx_intf/openofdm_rx/openofdm_tx/xpu). Related register addresses are defined in hw_def.h. 712ee67178SXianjun Jiao 72404ff4e0SJiao Xianjunmodule_name: **drv_rx** 732ee67178SXianjun Jiao 7462591d26Sweiliu1011reg_idx|meaning|comment 752ee67178SXianjun Jiao-------|-------|---- 762ee67178SXianjun Jiao1|rx antenna selection|0:rx1, 1:rx2. After this command, you should down and up sdr0 by ifconfig, but not reload sdr0 driver via ./wgd.sh 774ecf49bbSJiao Xianjun7|dmesg print control|bit0:error msg (0:OFF, 1:ON); bit1:regular msg (0:OFF, 1:ON) 782ee67178SXianjun Jiao 79404ff4e0SJiao Xianjun(In the **comment** column, you may get a list of **decimalvalue(0xhexvalue):explanation** for a register, only use the **decimalvalue** in the sdrctl command) 80404ff4e0SJiao Xianjun 81404ff4e0SJiao Xianjunmodule_name: **drv_tx** 822ee67178SXianjun Jiao 8362591d26Sweiliu1011reg_idx|meaning|comment 842ee67178SXianjun Jiao-------|-------|---- 852ee67178SXianjun Jiao0|override Linux rate control of tx unicast data packet|4:6M, 5:9M, 6:12M, 7:18M, 8:24M, 9:36M, 10:48M, 11:54M 862ee67178SXianjun Jiao1|tx antenna selection|0:tx1, 1:tx2. After this command, you should down and up sdr0 by ifconfig, but not reload sdr0 driver via ./wgd.sh 874ecf49bbSJiao Xianjun7|dmesg print control|bit0:error msg (0:OFF, 1:ON); bit1:regular msg (0:OFF, 1:ON) 882ee67178SXianjun Jiao 89404ff4e0SJiao Xianjunmodule_name: **drv_xpu** 902ee67178SXianjun Jiao 9162591d26Sweiliu1011reg_idx|meaning|comment 922ee67178SXianjun Jiao-------|-------|---- 93e240bea2SJiao Xianjun7|git revision when build the driver|example: return value 0071bc74 means git revision is 071bc74 (the 1st 0 must be removed!) 942ee67178SXianjun Jiao 95404ff4e0SJiao Xianjunmodule_name: **rf** 962ee67178SXianjun Jiao 9762591d26Sweiliu1011reg_idx|meaning|comment 982ee67178SXianjun Jiao-------|-------|---- 9962591d26Sweiliu1011x|x|to be defined 1002ee67178SXianjun Jiao 101404ff4e0SJiao Xianjunmodule_name: **rx_intf** 1022ee67178SXianjun Jiao 10362591d26Sweiliu1011reg_idx|meaning|comment 1042ee67178SXianjun Jiao-------|-------|---- 1052ee67178SXianjun Jiao2|enable/disable rx interrupt|256(0x100):disable, 0:enable 1062ee67178SXianjun Jiao 107404ff4e0SJiao Xianjunmodule_name: **tx_intf** 1082ee67178SXianjun Jiao 10962591d26Sweiliu1011reg_idx|meaning|comment 1102ee67178SXianjun Jiao-------|-------|---- 111b73660adSXianjun Jiao13|tx I/Q digital gain before DUC|current optimal value: 100 1122ee67178SXianjun Jiao14|enable/disable tx interrupt|196672(0x30040):disable, 64(0x40):enable 1132ee67178SXianjun Jiao 114404ff4e0SJiao Xianjunmodule_name: **rx** 1152ee67178SXianjun Jiao 11662591d26Sweiliu1011reg_idx|meaning|comment 1172ee67178SXianjun Jiao-------|-------|---- 1182ee67178SXianjun Jiao20|history of PHY rx state|read only. If the last digit readback is always 3, it means the Viterbi decoder stops working 1192ee67178SXianjun Jiao 120404ff4e0SJiao Xianjunmodule_name: **tx** 1212ee67178SXianjun Jiao 12262591d26Sweiliu1011reg_idx|meaning|comment 1232ee67178SXianjun Jiao-------|-------|---- 1242ee67178SXianjun Jiao1|pilot scrambler initial state|lowest 7 bits are used. 0x7E by default in openofdm_tx.c 1252ee67178SXianjun Jiao2|data scrambler initial state|lowest 7 bits are used. 0x7F by default in openofdm_tx.c 1262ee67178SXianjun Jiao 127404ff4e0SJiao Xianjunmodule_name: **xpu** 1282ee67178SXianjun Jiao 12962591d26Sweiliu1011reg_idx|meaning|comment 1302ee67178SXianjun Jiao-------|-------|---- 131365a7066SJiao Xianjun1|mute rx I/Q when tx|0:mute (default), 1:unmute, which means rx baseband will receive our own tx signal. Rx packet and tx packet (such as ACK) can be monitored in FPGA for timing analysis 1322ee67178SXianjun Jiao2|TSF timer low 32bit write|only write this register won't trigger the TSF timer reload. should use together with register for high 32bit 1332ee67178SXianjun Jiao3|TSF timer high 32bit write|falling edge of MSB will trigger the TSF timer reload, which means write '1' then '0' to MSB 1342ee67178SXianjun Jiao4|band and channel number setting|see enum openwifi_band in hw_def.h. it will be set automatically by Linux. normally you shouldn't set it 13510d539beSJiao Xianjun11|max number of retransmission in FPGA|normally number of retransmissions controlled by Linux in real-time. If you write non-zeros value to this register, it will override Linux real-time setting 1362ee67178SXianjun Jiao19|CSMA enable/disable|3758096384(0xe0000000): disable, 3:enable 1370669334cSJiao Xianjun27|FPGA packet filter config|check openwifi_configure_filter in sdr.c. also [mac80211 frame filtering](https://www.kernel.org/doc/html/v4.9/80211/mac80211.html#frame-filtering) 1382ee67178SXianjun Jiao28|BSSID address low 32bit for BSSID filtering|normally it is set by Linux in real-time automatically 1392ee67178SXianjun Jiao29|BSSID address high 32bit for BSSID filtering|normally it is set by Linux in real-time automatically 1402ee67178SXianjun Jiao30|openwifi MAC address low 32bit| 1412ee67178SXianjun Jiao31|openwifi MAC address high 32bit|check XPU_REG_MAC_ADDR_write in sdr.c to see how we set MAC address to FPGA when NIC start 1422ee67178SXianjun Jiao58|TSF runtime value low 32bit|read only 1432ee67178SXianjun Jiao59|TSF runtime value high 32bit|read only 144e1d42e15SJiao Xianjun63|git revision when build the FPGA|example: return value 065272ac means git revision is 65272ac (the 1st 0 must be removed!) 1455f436b3cSJiao Xianjun 146da2a8350SJiao Xianjun## Rx packet flow and filtering config 1475f436b3cSJiao Xianjun 1484f977aa9SJiao XianjunAfter FPGA receives a packet, no matter the FCS/CRC is correct or not it will raise interrupt to Linux if the frame filtering rule allows. openwifi_rx_interrupt() function in sdr.c will be triggered to do necessary operation and give the information to upper layer (Linux mac80211 subsystem). 1495f436b3cSJiao Xianjun 15010d539beSJiao Xianjun- frame filtering 15110d539beSJiao Xianjun 1520273d862SJiao XianjunThe FPGA frame filtering configuration is done in real-time by function openwifi_configure_filter() in sdr.c. The filter_flag together with **HIGH_PRIORITY_DISCARD_FLAG** finally go to pkt_filter_ctl.v of xpu module in FPGA, and control how FPGA does frame filtering. Openwifi has the capability to capture all received packets even if the CRC is bad. You just need to set the NIC to monitor mode by iwconfig command (check monitor_ch.sh in user_space directory). In monitor mode, openwifi_configure_filter() will set **MONITOR_ALL** to the frame filtering module pkt_filter_ctl.v in FPGA. This makes sure transfer all received packets to Linux mac80211 via rx interrupt. 15310d539beSJiao Xianjun 15410d539beSJiao Xianjun- main rx interrupt operations in openwifi_rx_interrupt() 1554f977aa9SJiao Xianjun - get raw content from DMA buffer. When Linux receives interrupt from FPGA rx_intf module, the content has been ready in Linux DMA buffer 15610d539beSJiao Xianjun - parse extra information inserted by FPGA in the DMA buffer 15710d539beSJiao Xianjun - TSF timer value 1584f977aa9SJiao Xianjun - raw RSSI value that will be converted to actual RSSI in dBm by different correction in different bands/channels 15910d539beSJiao Xianjun - packet length and MCS 16010d539beSJiao Xianjun - FCS is valid or not 16110d539beSJiao Xianjun - send packet content and necessary extra information to upper layer via ieee80211_rx_irqsafe() 1625f436b3cSJiao Xianjun 163da2a8350SJiao Xianjun## Tx packet flow and config 1645f436b3cSJiao Xianjun 16510d539beSJiao XianjunLinux mac80211 subsystem calls openwifi_tx() to initiate a packet sending. 16610d539beSJiao Xianjun 16710d539beSJiao Xianjun- main operations in openwifi_tx() 16810d539beSJiao Xianjun - get necessary information from the packet header (struct ieee80211_hdr) for future FPGA configuration use 16910d539beSJiao Xianjun - packet length and MCS 1704f977aa9SJiao Xianjun - unicast or broadcast? does it need ACK? how many retransmissions at most are allowed to be tried by FPGA in case ACK is not received in time? 17110d539beSJiao Xianjun - which time slice in FPGA the packet should go? 17210d539beSJiao Xianjun - should RTS-CTS be used? (Send RTS and wait for CTS before actually send the data packet) 17310d539beSJiao Xianjun - should CTS-to-self be used? (Send CTS-to-self packet before sending the data packet. You can force this on by force_use_cts_protect = true;) 17410d539beSJiao Xianjun - should a sequence number be set for this packet? 1754f977aa9SJiao Xianjun - generate SIGNAL field according to length and MCS information. Insert it before the packet for the future openofdm_tx FPGA module use 1764f977aa9SJiao Xianjun - generate FPGA/PHY sequence number (priv->phy_tx_sn) for internal use (cross check between Linux and FPGA) 1774f977aa9SJiao Xianjun - config FPGA register according to the above information to make sure FPGA do correct actions according to the packet specific requirement. 17810d539beSJiao Xianjun - fire DMA transmission from Linux to one of FPGA tx queues. The packet may not be sent immediately if there are still some packets in FPGA tx queue (FPGA does the queue packet transmission according to channel and low MAC state) 17910d539beSJiao Xianjun 1804f977aa9SJiao XianjunEach time when FPGA sends a packet, an interrupt will be raised to Linux reporting the packet sending result. This interrupt handler is openwifi_tx_interrupt(). 18110d539beSJiao Xianjun 18210d539beSJiao Xianjun- main operations in openwifi_tx_interrupt() 1834f977aa9SJiao Xianjun - get necessary information/status of the packet just sent by FPGA 1844f977aa9SJiao Xianjun - packet length and sequence number to capture abnormal situation (cross checking between Linux and FPGA) 1854f977aa9SJiao Xianjun - packet sending result: packet is sent successfully (FPGA receives ACK for this packet) or not. How many retransmissions are used for the packet sending (in case FPGA doesn't receive ACK in time, FPGA will do retransmission immediately) 18610d539beSJiao Xianjun - send above information to upper layer (Linux mac80211 subsystem) via ieee80211_tx_status_irqsafe() 1872309afd4SJiao Xianjun 188da2a8350SJiao Xianjun## Regulation and channel config 1890273d862SJiao Xianjun 1900273d862SJiao XianjunSDR is a powerful tool for research. It is the user's duty to align with local spectrum regulation. 1910273d862SJiao Xianjun 1920273d862SJiao XianjunThis section explains how openwifi config the frequency/channel range and change it in real-time. After knowing the mechanism, you can try to extend frequency/channel by yourself. 1930273d862SJiao Xianjun 194da2a8350SJiao Xianjun### Frequency range 1950273d862SJiao Xianjun 1960273d862SJiao XianjunWhen openwifi driver is loaded, openwifi_dev_probe() will be executed. Following two lines configure the frequency range: 1970273d862SJiao Xianjun``` 1980273d862SJiao Xianjundev->wiphy->regulatory_flags = xxx 1990273d862SJiao Xianjunwiphy_apply_custom_regulatory(dev->wiphy, &sdr_regd); 2000273d862SJiao Xianjun``` 2010273d862SJiao Xianjunsdr_regd is the predefined variable in sdr.h. You can search the definition/meaning of its type: struct ieee80211_regdomain. 2020273d862SJiao XianjunThen not difficult to find out how to change the frequency range in SDR_2GHZ_CH01_14 and SDR_5GHZ_CH36_64. 2030273d862SJiao Xianjun 204da2a8350SJiao Xianjun### Supported channel 2050273d862SJiao Xianjun 2069d96e692SJiao XianjunThe supported channel list is defined in openwifi_2GHz_channels and openwifi_5GHz_channels in sdr.h. If you change the number of supported channels, make sure you also change the frequency range in sdr_regd accordingly and also array size of the following two fields in the struct openwifi_priv: 2070273d862SJiao Xianjun``` 2080273d862SJiao Xianjunstruct ieee80211_channel channels_2GHz[14]; 2090273d862SJiao Xianjunstruct ieee80211_channel channels_5GHz[11]; 2100273d862SJiao Xianjun``` 2110273d862SJiao XianjunFinally, the supported channel list is transferred to Linux mac80211 when openwifi driver is loaded by following two lines in openwifi_dev_probe(): 2120273d862SJiao Xianjun``` 2130273d862SJiao Xianjundev->wiphy->bands[NL80211_BAND_2GHZ] = &(priv->band_2GHz); 2140273d862SJiao Xianjundev->wiphy->bands[NL80211_BAND_5GHZ] = &(priv->band_5GHz); 2150273d862SJiao Xianjun``` 2160273d862SJiao Xianjun 217da2a8350SJiao Xianjun### Real-time channel setting 2180273d862SJiao Xianjun 21988c09b72SJiao XianjunLinux mac80211 (struct ieee80211_ops openwifi_ops in sdr.c) uses the "config" API to configure channel frequency and some other parameters in real-time (such as during scanning or channel setting by iwconfig). It is hooked to openwifi_config() in sdr.c, and supports only frequency setting currently. The real execution of frequency setting falls to ad9361_rf_set_channel() via the "set_chan" field of struct openwifi_rf_ops ad9361_rf_ops in sdr.c. Besides tuning RF front-end (AD9361), the ad9361_rf_set_channel() also handles RSSI compensation for different frequencies and FPGA configurations (SIFS, etc) for different bands. 2200273d862SJiao Xianjun 221da2a8350SJiao Xianjun## Analog and digital frequency design 222da2a8350SJiao Xianjun 22395d09ab9SJiao XianjunFollowing figure shows the current openwifi analog and digital frequency design strategy. The Tx RF center frequency is tuned with 10MHz offset deliberately to ease Tx Lo leakage suppressed by Rx filter. This RF offset is pre-compensated by Tx DUC (Digital Up Converter) in FPGA (duc_bank_core.bd used by tx_intf.v). It combines AD9361's bandwidth, frequency, sampling rate and FPGA's digital down/up converter (ddc_bank_core.bd/duc_bank_core.bd) setting to achieve this example spectrum arrangement. Values in the figure are configurable in the openwifi design. Please be noticed that **ddc_bank_core.bd is not used anymore**. Because the digital and analog RX Lo is the same, mixer is not needed. Decimation by 2 is implemented in adc_intv.v. 224da2a8350SJiao Xianjun 225da2a8350SJiao Xianjun 226da2a8350SJiao XianjunAbove spectrum setting has two benefits: 227da2a8350SJiao Xianjun- The Tx Lo leakage is suppressed by Rx filter 228da2a8350SJiao Xianjun- The centered Rx Lo and single channel Rx analog filter leads to more easy/accurate RSSI estimation in FPGA (together with real-time AD9361 AGC gain value accessed via FPGA GPIO) 229da2a8350SJiao Xianjun 2300168c125SJiao XianjunFollowing figure shows the detailed configuration point in AD9361, driver (sdr.c/tx_intf.c/rx_intf.c/ad9361.c/etc) and related FPGA modules. 2310168c125SJiao Xianjun 2320168c125SJiao Xianjun 233da2a8350SJiao Xianjun## Debug methods 2342309afd4SJiao Xianjun 2352309afd4SJiao Xianjun### dmesg 2362309afd4SJiao Xianjun 2374ecf49bbSJiao XianjunTo debug/see the basic driver behaviour, you could turn on message printing by 2384ecf49bbSJiao Xianjun``` 2394ecf49bbSJiao XianjunSee all printing: 2404ecf49bbSJiao Xianjun./sdrctl dev sdr0 set reg drv_tx 7 3 2414ecf49bbSJiao Xianjun./sdrctl dev sdr0 set reg drv_rx 7 3 2424ecf49bbSJiao XianjunSee only error printing: 2434ecf49bbSJiao Xianjun./sdrctl dev sdr0 set reg drv_tx 7 1 2444ecf49bbSJiao Xianjun./sdrctl dev sdr0 set reg drv_rx 7 1 2454ecf49bbSJiao XianjunSee only regular printing: 2464ecf49bbSJiao Xianjun./sdrctl dev sdr0 set reg drv_tx 7 2 2474ecf49bbSJiao Xianjun./sdrctl dev sdr0 set reg drv_rx 7 2 2484ecf49bbSJiao XianjunTurn off printing: 2494ecf49bbSJiao Xianjun./sdrctl dev sdr0 set reg drv_tx 7 0 2504ecf49bbSJiao Xianjun./sdrctl dev sdr0 set reg drv_rx 7 0 2514ecf49bbSJiao Xianjun``` 2524ecf49bbSJiao Xianjunand use dmesg command in Linux to see those messages. openwifi driver prints normal tx/rx packet information when a packet is sent or received. The driver also prints WARNING information if it feels something abnormal happens. You can search "printk" in sdr.c to see all the printing points. 2532309afd4SJiao Xianjun 2542309afd4SJiao Xianjun- tx printing example 2552309afd4SJiao Xianjun 2564ecf49bbSJiao Xianjun sdr,sdr openwifi_tx: 84bytes 48M FC0208 DI002c addr1/2/3:b0481ada2ef2/66554433222a/66554433222a SC2100 flag40000012 retr6 ack1 prio2 q2 wr4 rd3 2572309afd4SJiao Xianjun - printing from sdr driver, openwifi_tx function. 2584ecf49bbSJiao Xianjun - 84bytes: packet size (length field in SIGNAL) 2594ecf49bbSJiao Xianjun - 48M: MCS (rate field in SIGNAL) 2604ecf49bbSJiao Xianjun - FC0208: Frame Control field, which means type data, subtype data, to DS 0, from DS 1 (a packet from AP to client). 2612309afd4SJiao Xianjun - DI002c: Duration/ID field 0x002c. How many us this packet will occupy the channel (including waiting for ACK). 2624ecf49bbSJiao Xianjun - addr1/2/3: address fields. Target MAC address b0481ada2ef2, source MAC address 66554433222a (openwifi). 2634ecf49bbSJiao Xianjun - SC2100: Sequence Control field 0x2100, which means that the driver inserts sequence number 0x2100 to the packet under request of upper layer. 2642309afd4SJiao Xianjun - flag40000012: flags field from upper layer struct ieee80211_tx_info (first fragment? need ACK? need sequence number insertion? etc.). Here is 0x40000012. 2654ecf49bbSJiao Xianjun - retry6: upper layer tells us the maximum number of retransmissions for this packet is 6. 2662309afd4SJiao Xianjun - ack1: upper layer tells us this packet needs ACK. 2674ecf49bbSJiao Xianjun - prio2: Linux select priority queue 2 for this packet (0:VO voice, 1:VI video, 2:BE best effort and 3:BK background) 2684ecf49bbSJiao Xianjun - q2: the packet goes to FPGA queue 2. (You can change the mapping between Linux priority and FPGA queue in sdr.c) 2694ecf49bbSJiao Xianjun - wr4 rd3: the write/read index of buffer (shared buffer between the active openwifi_tx and background openwifi_tx_interrupt). 2702309afd4SJiao Xianjun 2712309afd4SJiao Xianjun- rx printing example 2722309afd4SJiao Xianjun 2734ecf49bbSJiao Xianjun sdr,sdr openwifi_rx_interrupt: 28bytes 24M FC0108 DI002c addr1/2/3:66554433222a/b0481ada2ef2/66554433222a SC4760 fcs1 buf_idx13 -30dBm 2742309afd4SJiao Xianjun - printing from sdr driver, openwifi_rx_interrupt function. 2754ecf49bbSJiao Xianjun - 28bytes: packet size (length field in SIGNAL) 2764ecf49bbSJiao Xianjun - 24M: MCS (rate field in SIGNAL) 2774ecf49bbSJiao Xianjun - FC0108: Frame Control field 0x0108, which means type data, subtype data, to DS 1, from DS 0 (a packet client to openwifi AP). 2782309afd4SJiao Xianjun - DI002c: Duration/ID field 0x002c. How many us this packet will occupy the channel (including waiting for ACK). 2794ecf49bbSJiao Xianjun - addr1/2/3: address fields. Target MAC address 66554433222a (openwifi), source MAC address b0481ada2ef2. 2804ecf49bbSJiao Xianjun - SC4760: Sequence Control field 0x4760, which means that the packet includes sequence number 0x4760 (under request of upper layer of the peer). 2814ecf49bbSJiao Xianjun - fcs1: FCS/CRC is OK. (fcs0 means bad CRC) 2824ecf49bbSJiao Xianjun - buf_idx13: current rx packet DMA buffer index 13. 2834ecf49bbSJiao Xianjun - -30dBm: signal strength of this received packet. 2842309afd4SJiao Xianjun 285da2a8350SJiao Xianjun### Native Linux tools 2862309afd4SJiao Xianjun 2872309afd4SJiao XianjunFor protocol, many native Linux tools you still could rely on. Such as tcpdump. 2882309afd4SJiao Xianjun 2892309afd4SJiao Xianjun### FPGA 2902309afd4SJiao Xianjun 2914f977aa9SJiao XianjunFor FPGA itself, FPGA developer could use Xilinx ILA tools to analyze FPGA signals. Spying on those state machines in xpu/tx_intf/rx_intf would be very helpful for understanding/debugging Wi-Fi low level funtionalities. 292