1*10465441SEvalZero#include "cpuconfig.h" 2*10465441SEvalZero 3*10465441SEvalZero//#include "iorx62n.h" 4*10465441SEvalZero EXTERN _rt_thread_switch_interrupt_flag 5*10465441SEvalZero EXTERN _rt_interrupt_from_thread 6*10465441SEvalZero EXTERN _rt_interrupt_to_thread 7*10465441SEvalZero EXTERN _rt_hw_hard_fault_exception 8*10465441SEvalZero EXTERN _rt_hw_cpu_shutdown 9*10465441SEvalZero 10*10465441SEvalZero /*PUBLIC _Interrupt_SWINT*/ 11*10465441SEvalZero PUBLIC ___interrupt_27 12*10465441SEvalZero PUBLIC ___interrupt_0 13*10465441SEvalZero RSEG CODE:CODE(4) 14*10465441SEvalZero 15*10465441SEvalZero;/* 16*10465441SEvalZero; * rt_base_t rt_hw_interrupt_disable(); 17*10465441SEvalZero; */ 18*10465441SEvalZero PUBLIC _rt_hw_interrupt_disable 19*10465441SEvalZero_rt_hw_interrupt_disable: 20*10465441SEvalZero MVTIPL #MAX_SYSCALL_INTERRUPT_PRIORITY 21*10465441SEvalZero RTS 22*10465441SEvalZero 23*10465441SEvalZero;/* 24*10465441SEvalZero; * void rt_hw_interrupt_enable(rt_base_t level); 25*10465441SEvalZero; */ 26*10465441SEvalZero PUBLIC _rt_hw_interrupt_enable 27*10465441SEvalZero_rt_hw_interrupt_enable: 28*10465441SEvalZero MVTIPL #KERNEL_INTERRUPT_PRIORITY 29*10465441SEvalZero RTS 30*10465441SEvalZero 31*10465441SEvalZero; r0 --> swith from thread stack 32*10465441SEvalZero; r1 --> swith to thread stack 33*10465441SEvalZero; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack 34*10465441SEvalZero___interrupt_27: 35*10465441SEvalZero 36*10465441SEvalZero/* enable interrupt because enter the interrupt,it will be clear */ 37*10465441SEvalZero SETPSW I 38*10465441SEvalZero MVTIPL #MAX_SYSCALL_INTERRUPT_PRIORITY 39*10465441SEvalZero PUSH.L R15 40*10465441SEvalZero 41*10465441SEvalZero/* justage if it should switch thread*/ 42*10465441SEvalZero MOV.L #_rt_thread_switch_interrupt_flag, R15 43*10465441SEvalZero MOV.L [ R15 ], R15 44*10465441SEvalZero CMP #0, R15 45*10465441SEvalZero BEQ notask_exit 46*10465441SEvalZero/* clean the flag*/ 47*10465441SEvalZero MOV.L #_rt_thread_switch_interrupt_flag, R15 48*10465441SEvalZero MOV.L #0, [ R15 ] 49*10465441SEvalZero 50*10465441SEvalZero/* justage if it should save the register*/ 51*10465441SEvalZero MOV.L #_rt_interrupt_from_thread, R15 52*10465441SEvalZero MOV.L [ R15 ], R15 53*10465441SEvalZero CMP #0, R15 54*10465441SEvalZero BEQ need_modify_isp 55*10465441SEvalZero /*save register*/ 56*10465441SEvalZero MVFC USP, R15 57*10465441SEvalZero SUB #12, R15 58*10465441SEvalZero MVTC R15, USP 59*10465441SEvalZero MOV.L [ R0 ], [ R15 ] ;PSW 60*10465441SEvalZero MOV.L 4[ R0 ], 4[ R15 ];PC 61*10465441SEvalZero MOV.L 8[ R0 ], 8[ R15 ] ;R15 62*10465441SEvalZero ADD #12, R0 63*10465441SEvalZero SETPSW U 64*10465441SEvalZero PUSHM R1-R14 65*10465441SEvalZero MVFC FPSW, R15 66*10465441SEvalZero PUSH.L R15 67*10465441SEvalZero MVFACHI R15 68*10465441SEvalZero PUSH.L R15 69*10465441SEvalZero MVFACMI R15 ; Middle order word. 70*10465441SEvalZero SHLL #16, R15 ; Shifted left as it is restored to the low orde r w 71*10465441SEvalZero PUSH.L R15 72*10465441SEvalZero /*save thread stack pointer and switch to new thread*/ 73*10465441SEvalZero MOV.L #_rt_interrupt_from_thread, R15 74*10465441SEvalZero MOV.L [ R15 ], R15 75*10465441SEvalZero MOV.L R0, [ R15 ] 76*10465441SEvalZero BRA swtich_to_thread 77*10465441SEvalZeroneed_modify_isp: 78*10465441SEvalZero MVFC ISP, R15 79*10465441SEvalZero ADD #12, R15 80*10465441SEvalZero MVTC R15, ISP 81*10465441SEvalZeroswtich_to_thread: 82*10465441SEvalZero SETPSW U 83*10465441SEvalZero MOV.L #_rt_interrupt_to_thread, R15 84*10465441SEvalZero MOV.L [ R15 ], R15 85*10465441SEvalZero MOV.L [ R15 ], R0 86*10465441SEvalZero POP R15 87*10465441SEvalZero MVTACLO R15 88*10465441SEvalZero POP R15 89*10465441SEvalZero MVTACHI R15 90*10465441SEvalZero POP R15 91*10465441SEvalZero MVTC R15, FPSW 92*10465441SEvalZero POPM R1-R15 93*10465441SEvalZero BRA pendsv_exit 94*10465441SEvalZeronotask_exit: 95*10465441SEvalZero POP R15 96*10465441SEvalZeropendsv_exit: 97*10465441SEvalZero 98*10465441SEvalZero MVTIPL #KERNEL_INTERRUPT_PRIORITY 99*10465441SEvalZero RTE 100*10465441SEvalZero NOP 101*10465441SEvalZero NOP 102*10465441SEvalZero/*exception interrupt*/ 103*10465441SEvalZero___interrupt_0: 104*10465441SEvalZero PUSH.L R15 105*10465441SEvalZero /*save the register for infomation*/ 106*10465441SEvalZero MVFC USP, R15 107*10465441SEvalZero SUB #12, R15 108*10465441SEvalZero MVTC R15, USP 109*10465441SEvalZero MOV.L [ R0 ], [ R15 ] ;PSW 110*10465441SEvalZero MOV.L 4[ R0 ], 4[ R15 ];PC 111*10465441SEvalZero MOV.L 8[ R0 ], 8[ R15 ] ;R15 112*10465441SEvalZero ADD #12, R0 113*10465441SEvalZero SETPSW U 114*10465441SEvalZero PUSHM R1-R14 115*10465441SEvalZero MVFC FPSW, R15 116*10465441SEvalZero PUSH.L R15 117*10465441SEvalZero MVFACHI R15 118*10465441SEvalZero PUSH.L R15 119*10465441SEvalZero MVFACMI R15 ; Middle order word. 120*10465441SEvalZero SHLL #16, R15 ; Shifted left as it is restored to the low orde r w 121*10465441SEvalZero PUSH.L R15 122*10465441SEvalZero /*save the exception infomation add R1 as a parameter of 123*10465441SEvalZero * function rt_hw_hard_fault_exception 124*10465441SEvalZero */ 125*10465441SEvalZero MOV.L R0, R1 126*10465441SEvalZero BRA _rt_hw_hard_fault_exception 127*10465441SEvalZero BRA _rt_hw_cpu_shutdown 128*10465441SEvalZero RTE 129*10465441SEvalZero NOP 130*10465441SEvalZero NOP 131*10465441SEvalZero END 132*10465441SEvalZero 133